1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2015-2016 Intel Corp. 4 * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) 5 * Copyright 2019 Google LLC 6 */ 7 8#ifndef _ASM_ARCH_PM_H 9#define _ASM_ARCH_PM_H 10 11#include <power/acpi_pmc.h> 12 13#define PMC_GPE_SW_31_0 0 14#define PMC_GPE_SW_63_32 1 15#define PMC_GPE_NW_31_0 3 16#define PMC_GPE_NW_63_32 4 17#define PMC_GPE_NW_95_64 5 18#define PMC_GPE_N_31_0 6 19#define PMC_GPE_N_63_32 7 20#define PMC_GPE_W_31_0 9 21 22#define IRQ_REG 0x106c 23#define SCI_IRQ_SHIFT 24 24#define SCI_IRQ_MASK (0xff << SCI_IRQ_SHIFT) 25#define SCIS_IRQ9 9 26#define SCIS_IRQ10 10 27#define SCIS_IRQ11 11 28#define SCIS_IRQ20 20 29#define SCIS_IRQ21 21 30#define SCIS_IRQ22 22 31#define SCIS_IRQ23 23 32 33/* P-state configuration */ 34#define PSS_MAX_ENTRIES 8 35#define PSS_RATIO_STEP 2 36#define PSS_LATENCY_TRANSITION 10 37#define PSS_LATENCY_BUSMASTER 10 38 39#ifndef __ASSEMBLY__ 40/* Track power state from reset to log events */ 41struct __packed chipset_power_state { 42 u16 pm1_sts; 43 u16 pm1_en; 44 u32 pm1_cnt; 45 u32 gpe0_sts[GPE0_REG_MAX]; 46 u32 gpe0_en[GPE0_REG_MAX]; 47 u16 tco1_sts; 48 u16 tco2_sts; 49 u32 prsts; 50 u32 gen_pmcon1; 51 u32 gen_pmcon2; 52 u32 gen_pmcon3; 53 u32 prev_sleep_state; 54}; 55#endif /* !__ASSEMBLY__ */ 56 57#endif 58