1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6#include <common.h>
7#include <cpu_func.h>
8#include <init.h>
9#include <pci.h>
10#include <qfw.h>
11#include <dm/platdata.h>
12#include <asm/irq.h>
13#include <asm/post.h>
14#include <asm/processor.h>
15#include <asm/arch/device.h>
16#include <asm/arch/qemu.h>
17
18static bool i440fx;
19
20#if CONFIG_IS_ENABLED(QFW_PIO)
21U_BOOT_DRVINFO(x86_qfw_pio) = {
22	.name = "qfw_pio",
23};
24#endif
25
26static void enable_pm_piix(void)
27{
28	u8 en;
29	u16 cmd;
30
31	/* Set the PM I/O base */
32	pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
33
34	/* Enable access to the PM I/O space */
35	pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd);
36	cmd |= PCI_COMMAND_IO;
37	pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
38
39	/* PM I/O Space Enable (PMIOSE) */
40	pci_read_config8(PIIX_PM, PMREGMISC, &en);
41	en |= PMIOSE;
42	pci_write_config8(PIIX_PM, PMREGMISC, en);
43}
44
45static void enable_pm_ich9(void)
46{
47	/* Set the PM I/O base */
48	pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
49}
50
51void qemu_chipset_init(void)
52{
53	u16 device, xbcs;
54	int pam, i;
55
56	/*
57	 * i440FX and Q35 chipset have different PAM register offset, but with
58	 * the same bitfield layout. Here we determine the offset based on its
59	 * PCI device ID.
60	 */
61	pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
62	i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
63	pam = i440fx ? I440FX_PAM : Q35_PAM;
64
65	/*
66	 * Initialize Programmable Attribute Map (PAM) Registers
67	 *
68	 * Configure legacy segments C/D/E/F to system RAM
69	 */
70	for (i = 0; i < PAM_NUM; i++)
71		pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
72
73	if (i440fx) {
74		/*
75		 * Enable legacy IDE I/O ports decode
76		 *
77		 * Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
78		 * However Linux ata_piix driver does sanity check on these two
79		 * registers to see whether legacy ports decode is turned on.
80		 * This is to make Linux ata_piix driver happy.
81		 */
82		pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
83		pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
84
85		/* Enable I/O APIC */
86		pci_read_config16(PIIX_ISA, XBCS, &xbcs);
87		xbcs |= APIC_EN;
88		pci_write_config16(PIIX_ISA, XBCS, xbcs);
89
90		enable_pm_piix();
91	} else {
92		/* Configure PCIe ECAM base address */
93		pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
94				   CONFIG_PCIE_ECAM_BASE | BAR_EN);
95
96		enable_pm_ich9();
97	}
98}
99
100#if CONFIG_IS_ENABLED(X86_32BIT_INIT)
101int arch_cpu_init(void)
102{
103	post_code(POST_CPU_INIT);
104
105	return x86_cpu_init_f();
106}
107
108int checkcpu(void)
109{
110	return 0;
111}
112
113int print_cpuinfo(void)
114{
115	post_code(POST_CPU_INFO);
116	return default_print_cpuinfo();
117}
118#endif
119
120int arch_early_init_r(void)
121{
122	qemu_chipset_init();
123
124	return 0;
125}
126
127#ifdef CONFIG_GENERATE_MP_TABLE
128int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
129{
130	u8 irq;
131
132	if (i440fx) {
133		/*
134		 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
135		 * connected to I/O APIC INTPIN#16-19. Instead they are routed
136		 * to an irq number controled by the PIRQ routing register.
137		 */
138		pci_read_config8(PCI_BDF(bus, dev, func),
139				 PCI_INTERRUPT_LINE, &irq);
140	} else {
141		/*
142		 * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
143		 * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
144		 */
145		irq = pirq < 8 ? pirq + 16 : pirq + 12;
146	}
147
148	return irq;
149}
150#endif
151