1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Run U-Boot in 32/64-bit mode" 9 default X86_RUN_32BIT 10 help 11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode 12 even on 64-bit machines. In this case SPL is not used, and U-Boot 13 runs directly from the reset vector (via 16-bit start-up). 14 15 Alternatively it can be run as a 64-bit binary, thus requiring a 16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit 17 start-up) then jumps to U-Boot in 64-bit mode. 18 19 For now, 32-bit mode is recommended, as 64-bit is still 20 experimental and is missing a lot of features. 21 22config X86_RUN_32BIT 23 bool "32-bit" 24 help 25 Build U-Boot as a 32-bit binary with no SPL. This is the currently 26 supported normal setup. U-Boot will stay in 32-bit mode even on 27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch 28 to 64-bit just before starting the kernel. Only the bottom 4GB of 29 memory can be accessed through normal means, although 30 arch_phys_memset() can be used for basic access to other memory. 31 32config X86_RUN_64BIT 33 bool "64-bit" 34 select X86_64 35 select SPL if !EFI_APP 36 select SPL_SEPARATE_BSS if !EFI_APP 37 help 38 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is 39 experimental and many features are missing. U-Boot SPL starts up, 40 runs through the 16-bit and 32-bit init, then switches to 64-bit 41 mode and jumps to U-Boot proper. 42 43endchoice 44 45config X86_64 46 bool 47 48config SPL_X86_64 49 bool 50 depends on SPL 51 52choice 53 prompt "Mainboard vendor" 54 default VENDOR_EMULATION 55 56config VENDOR_ADVANTECH 57 bool "advantech" 58 59config VENDOR_CONGATEC 60 bool "congatec" 61 62config VENDOR_COREBOOT 63 bool "coreboot" 64 65config VENDOR_DFI 66 bool "dfi" 67 68config VENDOR_EFI 69 bool "efi" 70 71config VENDOR_EMULATION 72 bool "emulation" 73 74config VENDOR_GOOGLE 75 bool "Google" 76 77config VENDOR_INTEL 78 bool "Intel" 79 80endchoice 81 82# subarchitectures-specific options below 83config INTEL_MID 84 bool "Intel MID platform support" 85 select REGMAP 86 select SYSCON 87 help 88 Select to build a U-Boot capable of supporting Intel MID 89 (Mobile Internet Device) platform systems which do not have 90 the PCI legacy interfaces. 91 92 If you are building for a PC class system say N here. 93 94 Intel MID platforms are based on an Intel processor and 95 chipset which consume less power than most of the x86 96 derivatives. 97 98# board-specific options below 99source "board/advantech/Kconfig" 100source "board/congatec/Kconfig" 101source "board/coreboot/Kconfig" 102source "board/dfi/Kconfig" 103source "board/efi/Kconfig" 104source "board/emulation/Kconfig" 105source "board/google/Kconfig" 106source "board/intel/Kconfig" 107 108# platform-specific options below 109source "arch/x86/cpu/apollolake/Kconfig" 110source "arch/x86/cpu/baytrail/Kconfig" 111source "arch/x86/cpu/braswell/Kconfig" 112source "arch/x86/cpu/broadwell/Kconfig" 113source "arch/x86/cpu/coreboot/Kconfig" 114source "arch/x86/cpu/ivybridge/Kconfig" 115source "arch/x86/cpu/efi/Kconfig" 116source "arch/x86/cpu/qemu/Kconfig" 117source "arch/x86/cpu/quark/Kconfig" 118source "arch/x86/cpu/queensbay/Kconfig" 119source "arch/x86/cpu/slimbootloader/Kconfig" 120source "arch/x86/cpu/tangier/Kconfig" 121 122# architecture-specific options below 123 124config AHCI 125 default y 126 127config SYS_MALLOC_F_LEN 128 default 0x800 129 130config RAMBASE 131 hex 132 default 0x100000 133 134config XIP_ROM_SIZE 135 hex 136 depends on X86_RESET_VECTOR 137 default ROM_SIZE 138 139config CPU_ADDR_BITS 140 int 141 default 36 142 143config HPET_ADDRESS 144 hex 145 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 146 147config SMM_TSEG 148 bool 149 150config SMM_TSEG_SIZE 151 hex 152 153config X86_RESET_VECTOR 154 bool 155 select BINMAN 156 157# The following options control where the 16-bit and 32-bit init lies 158# If SPL is enabled then it normally holds this init code, and U-Boot proper 159# is normally a 64-bit build. 160# 161# The 16-bit init refers to the reset vector and the small amount of code to 162# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, 163# or missing altogether if U-Boot is started from EFI or coreboot. 164# 165# The 32-bit init refers to processor init, running binary blobs including 166# FSP, setting up interrupts and anything else that needs to be done in 167# 32-bit code. It is normally in the same place as 16-bit init if that is 168# enabled (i.e. they are both in SPL, or both in U-Boot proper). 169config X86_16BIT_INIT 170 bool 171 depends on X86_RESET_VECTOR 172 default y if X86_RESET_VECTOR && !SPL 173 help 174 This is enabled when 16-bit init is in U-Boot proper 175 176config SPL_X86_16BIT_INIT 177 bool 178 depends on X86_RESET_VECTOR 179 default y if X86_RESET_VECTOR && SPL && !TPL 180 help 181 This is enabled when 16-bit init is in SPL 182 183config TPL_X86_16BIT_INIT 184 bool 185 depends on X86_RESET_VECTOR 186 default y if X86_RESET_VECTOR && TPL 187 help 188 This is enabled when 16-bit init is in TPL 189 190config X86_32BIT_INIT 191 bool 192 depends on X86_RESET_VECTOR 193 default y if X86_RESET_VECTOR && !SPL 194 help 195 This is enabled when 32-bit init is in U-Boot proper 196 197config SPL_X86_32BIT_INIT 198 bool 199 depends on X86_RESET_VECTOR 200 default y if X86_RESET_VECTOR && SPL 201 help 202 This is enabled when 32-bit init is in SPL 203 204config USE_EARLY_BOARD_INIT 205 bool 206 207config RESET_SEG_START 208 hex 209 depends on X86_RESET_VECTOR 210 default 0xffff0000 211 212config RESET_VEC_LOC 213 hex 214 depends on X86_RESET_VECTOR 215 default 0xfffffff0 216 217config SYS_X86_START16 218 hex 219 depends on X86_RESET_VECTOR 220 default 0xfffff800 221 222config HAVE_X86_FIT 223 bool 224 help 225 Enable inclusion of an Intel Firmware Interface Table (FIT) into the 226 image. This table is supposed to point to microcode and the like. So 227 far it is just a fixed table with the minimum set of headers, so that 228 it is actually present. 229 230config X86_LOAD_FROM_32_BIT 231 bool "Boot from a 32-bit program" 232 help 233 Define this to boot U-Boot from a 32-bit program which sets 234 the GDT differently. This can be used to boot directly from 235 any stage of coreboot, for example, bypassing the normal 236 payload-loading feature. 237 238config BOARD_ROMSIZE_KB_512 239 bool 240config BOARD_ROMSIZE_KB_1024 241 bool 242config BOARD_ROMSIZE_KB_2048 243 bool 244config BOARD_ROMSIZE_KB_4096 245 bool 246config BOARD_ROMSIZE_KB_8192 247 bool 248config BOARD_ROMSIZE_KB_16384 249 bool 250 251choice 252 prompt "ROM chip size" 253 depends on X86_RESET_VECTOR 254 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 255 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 256 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 257 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 258 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 259 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 260 help 261 Select the size of the ROM chip you intend to flash U-Boot on. 262 263 The build system will take care of creating a u-boot.rom file 264 of the matching size. 265 266config UBOOT_ROMSIZE_KB_512 267 bool "512 KB" 268 help 269 Choose this option if you have a 512 KB ROM chip. 270 271config UBOOT_ROMSIZE_KB_1024 272 bool "1024 KB (1 MB)" 273 help 274 Choose this option if you have a 1024 KB (1 MB) ROM chip. 275 276config UBOOT_ROMSIZE_KB_2048 277 bool "2048 KB (2 MB)" 278 help 279 Choose this option if you have a 2048 KB (2 MB) ROM chip. 280 281config UBOOT_ROMSIZE_KB_4096 282 bool "4096 KB (4 MB)" 283 help 284 Choose this option if you have a 4096 KB (4 MB) ROM chip. 285 286config UBOOT_ROMSIZE_KB_8192 287 bool "8192 KB (8 MB)" 288 help 289 Choose this option if you have a 8192 KB (8 MB) ROM chip. 290 291config UBOOT_ROMSIZE_KB_16384 292 bool "16384 KB (16 MB)" 293 help 294 Choose this option if you have a 16384 KB (16 MB) ROM chip. 295 296endchoice 297 298# Map the config names to an integer (KB). 299config UBOOT_ROMSIZE_KB 300 int 301 default 512 if UBOOT_ROMSIZE_KB_512 302 default 1024 if UBOOT_ROMSIZE_KB_1024 303 default 2048 if UBOOT_ROMSIZE_KB_2048 304 default 4096 if UBOOT_ROMSIZE_KB_4096 305 default 8192 if UBOOT_ROMSIZE_KB_8192 306 default 16384 if UBOOT_ROMSIZE_KB_16384 307 308# Map the config names to a hex value (bytes). 309config ROM_SIZE 310 hex 311 default 0x80000 if UBOOT_ROMSIZE_KB_512 312 default 0x100000 if UBOOT_ROMSIZE_KB_1024 313 default 0x200000 if UBOOT_ROMSIZE_KB_2048 314 default 0x400000 if UBOOT_ROMSIZE_KB_4096 315 default 0x800000 if UBOOT_ROMSIZE_KB_8192 316 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 317 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 318 319config HAVE_INTEL_ME 320 bool "Platform requires Intel Management Engine" 321 help 322 Newer higher-end devices have an Intel Management Engine (ME) 323 which is a very large binary blob (typically 1.5MB) which is 324 required for the platform to work. This enforces a particular 325 SPI flash format. You will need to supply the me.bin file in 326 your board directory. 327 328config X86_RAMTEST 329 bool "Perform a simple RAM test after SDRAM initialisation" 330 help 331 If there is something wrong with SDRAM then the platform will 332 often crash within U-Boot or the kernel. This option enables a 333 very simple RAM test that quickly checks whether the SDRAM seems 334 to work correctly. It is not exhaustive but can save time by 335 detecting obvious failures. 336 337config FLASH_DESCRIPTOR_FILE 338 string "Flash descriptor binary filename" 339 depends on HAVE_INTEL_ME || FSP_VERSION2 340 default "descriptor.bin" 341 help 342 The filename of the file to use as flash descriptor in the 343 board directory. 344 345config INTEL_ME_FILE 346 string "Intel Management Engine binary filename" 347 depends on HAVE_INTEL_ME 348 default "me.bin" 349 help 350 The filename of the file to use as Intel Management Engine in the 351 board directory. 352 353config USE_HOB 354 bool "Use HOB (Hand-Off Block)" 355 help 356 Select this option to access HOB (Hand-Off Block) data structures 357 and parse HOBs. This HOB infra structure can be reused with 358 different solutions across different platforms. 359 360config HAVE_FSP 361 bool "Add an Firmware Support Package binary" 362 depends on !EFI 363 select USE_HOB 364 select HAS_ROM 365 help 366 Select this option to add an Firmware Support Package binary to 367 the resulting U-Boot image. It is a binary blob which U-Boot uses 368 to set up SDRAM and other chipset specific initialization. 369 370 Note: Without this binary U-Boot will not be able to set up its 371 SDRAM so will not boot. 372 373config USE_CAR 374 bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up" 375 default y if !HAVE_FSP 376 help 377 Select this option if your board uses CAR init code, typically in a 378 car.S file, to get some initial memory for code execution. This is 379 common with Intel CPUs which don't use FSP. 380 381choice 382 prompt "FSP version" 383 depends on HAVE_FSP 384 default FSP_VERSION1 385 help 386 Selects the FSP version to use. Intel has published several versions 387 of the FSP External Architecture Specification and this allows 388 selection of the version number used by a particular SoC. 389 390config FSP_VERSION1 391 bool "FSP version 1.x" 392 help 393 This covers versions 1.0 and 1.1a. See here for details: 394 https://github.com/IntelFsp/fsp/wiki 395 396config FSP_VERSION2 397 bool "FSP version 2.x" 398 select DM_EVENT 399 help 400 This covers versions 2.0 and 2.1. See here for details: 401 https://github.com/IntelFsp/fsp/wiki 402 403endchoice 404 405config FSP_FILE 406 string "Firmware Support Package binary filename" 407 depends on FSP_VERSION1 408 default "fsp.bin" 409 help 410 The filename of the file to use as Firmware Support Package binary 411 in the board directory. 412 413config FSP_ADDR 414 hex "Firmware Support Package binary location" 415 depends on FSP_VERSION1 416 default 0xfffc0000 417 help 418 FSP is not Position Independent Code (PIC) and the whole FSP has to 419 be rebased if it is placed at a location which is different from the 420 perferred base address specified during the FSP build. Use Intel's 421 Binary Configuration Tool (BCT) to do the rebase. 422 423 The default base address of 0xfffc0000 indicates that the binary must 424 be located at offset 0xc0000 from the beginning of a 1MB flash device. 425 426if FSP_VERSION2 427 428config FSP_FILE_T 429 string "Firmware Support Package binary filename (Temp RAM)" 430 default "fsp_t.bin" 431 help 432 The filename of the file to use for the temporary-RAM init phase from 433 the Firmware Support Package binary. Put this in the board directory. 434 It is used to set up an initial area of RAM which can be used for the 435 stack and other purposes, while bringing up the main system DRAM. 436 437config FSP_ADDR_T 438 hex "Firmware Support Package binary location (Temp RAM)" 439 default 0xffff8000 440 help 441 FSP is not Position-Independent Code (PIC) and FSP components have to 442 be rebased if placed at a location which is different from the 443 perferred base address specified during the FSP build. Use Intel's 444 Binary Configuration Tool (BCT) to do the rebase. 445 446config FSP_FILE_M 447 string "Firmware Support Package binary filename (Memory Init)" 448 default "fsp_m.bin" 449 help 450 The filename of the file to use for the RAM init phase from the 451 Firmware Support Package binary. Put this in the board directory. 452 It is used to set up the main system DRAM and runs in SPL, once 453 temporary RAM (CAR) is working. 454 455config FSP_FILE_S 456 string "Firmware Support Package binary filename (Silicon Init)" 457 default "fsp_s.bin" 458 help 459 The filename of the file to use for the Silicon init phase from the 460 Firmware Support Package binary. Put this in the board directory. 461 It is used to set up the silicon to work correctly and must be 462 executed after DRAM is running. 463 464config IFWI_INPUT_FILE 465 string "Filename containing FIT (Firmware Interface Table) with IFWI" 466 default "fitimage.bin" 467 help 468 The IFWI is obtained by running a tool on this file to extract the 469 IFWI. Put this in the board directory. The IFWI contains U-Boot TPL, 470 microcode and other internal items. 471 472endif 473 474config FSP_TEMP_RAM_ADDR 475 hex 476 depends on FSP_VERSION1 477 default 0x2000000 478 help 479 Stack top address which is used in fsp_init() after DRAM is ready and 480 CAR is disabled. 481 482config FSP_SYS_MALLOC_F_LEN 483 hex 484 depends on FSP_VERSION1 485 default 0x100000 486 help 487 Additional size of malloc() pool before relocation. 488 489config FSP_USE_UPD 490 bool 491 depends on FSP_VERSION1 492 default y if !NORTHBRIDGE_INTEL_IVYBRIDGE 493 help 494 Most FSPs use UPD data region for some FSP customization. But there 495 are still some FSPs that might not even have UPD. For such FSPs, 496 override this to n in their platform Kconfig files. 497 498config FSP_BROKEN_HOB 499 bool 500 depends on FSP_VERSION1 501 help 502 Indicate some buggy FSPs that does not report memory used by FSP 503 itself as reserved in the resource descriptor HOB. Select this to 504 tell U-Boot to do some additional work to ensure U-Boot relocation 505 do not overwrite the important boot service data which is used by 506 FSP, otherwise the subsequent call to fsp_notify() will fail. 507 508config ENABLE_MRC_CACHE 509 bool "Enable MRC cache" 510 depends on !EFI && !SYS_COREBOOT 511 help 512 Enable this feature to cause MRC data to be cached in NV storage 513 to be used for speeding up boot time on future reboots and/or 514 power cycles. 515 516 For platforms that use Intel FSP for the memory initialization, 517 please check FSP output HOB via U-Boot command 'fsp hob' to see 518 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h). 519 If such GUID does not exist, MRC cache is not available on such 520 platform (eg: Intel Queensbay), which means selecting this option 521 here does not make any difference. 522 523config HAVE_MRC 524 bool "Add a System Agent binary" 525 select HAS_ROM 526 depends on !HAVE_FSP 527 help 528 Select this option to add a System Agent binary to 529 the resulting U-Boot image. MRC stands for Memory Reference Code. 530 It is a binary blob which U-Boot uses to set up SDRAM. 531 532 Note: Without this binary U-Boot will not be able to set up its 533 SDRAM so will not boot. 534 535config CACHE_MRC_BIN 536 bool 537 depends on HAVE_MRC 538 help 539 Enable caching for the memory reference code binary. This uses an 540 MTRR (memory type range register) to turn on caching for the section 541 of SPI flash that contains the memory reference code. This makes 542 SDRAM init run faster. 543 544config CACHE_MRC_SIZE_KB 545 int 546 depends on HAVE_MRC 547 default 512 548 help 549 Sets the size of the cached area for the memory reference code. 550 This ends at the end of SPI flash (address 0xffffffff) and is 551 measured in KB. Typically this is set to 512, providing for 0.5MB 552 of cached space. 553 554config DCACHE_RAM_BASE 555 hex 556 depends on HAVE_MRC 557 help 558 Sets the base of the data cache area in memory space. This is the 559 start address of the cache-as-RAM (CAR) area and the address varies 560 depending on the CPU. Once CAR is set up, read/write memory becomes 561 available at this address and can be used temporarily until SDRAM 562 is working. 563 564config DCACHE_RAM_SIZE 565 hex 566 depends on HAVE_MRC 567 default 0x40000 568 help 569 Sets the total size of the data cache area in memory space. This 570 sets the size of the cache-as-RAM (CAR) area. Note that much of the 571 CAR space is required by the MRC. The CAR space available to U-Boot 572 is normally at the start and typically extends to 1/4 or 1/2 of the 573 available size. 574 575config DCACHE_RAM_MRC_VAR_SIZE 576 hex 577 depends on HAVE_MRC 578 help 579 This is the amount of CAR (Cache as RAM) reserved for use by the 580 memory reference code. This depends on the implementation of the 581 memory reference code and must be set correctly or the board will 582 not boot. 583 584config HAVE_REFCODE 585 bool "Add a Reference Code binary" 586 help 587 Select this option to add a Reference Code binary to the resulting 588 U-Boot image. This is an Intel binary blob that handles system 589 initialisation, in this case the PCH and System Agent. 590 591 Note: Without this binary (on platforms that need it such as 592 broadwell) U-Boot will be missing some critical setup steps. 593 Various peripherals may fail to work. 594 595config HAVE_MICROCODE 596 bool "Board requires a microcode binary" 597 default y if !FSP_VERSION2 598 help 599 Enable this if the board requires microcode to be loaded on boot. 600 Typically this is handed by the FSP for modern boards, but for 601 some older boards, it must be programmed by U-Boot, and that form 602 part of the image. 603 604config SMP 605 bool "Enable Symmetric Multiprocessing" 606 help 607 Enable use of more than one CPU in U-Boot and the Operating System 608 when loaded. Each CPU will be started up and information can be 609 obtained using the 'cpu' command. If this option is disabled, then 610 only one CPU will be enabled regardless of the number of CPUs 611 available. 612 613config SMP_AP_WORK 614 bool 615 depends on SMP 616 help 617 Allow APs to do other work after initialisation instead of going 618 to sleep. 619 620config MAX_CPUS 621 int "Maximum number of CPUs permitted" 622 depends on SMP 623 default 4 624 help 625 When using multi-CPU chips it is possible for U-Boot to start up 626 more than one CPU. The stack memory used by all of these CPUs is 627 pre-allocated so at present U-Boot wants to know the maximum 628 number of CPUs that may be present. Set this to at least as high 629 as the number of CPUs in your system (it uses about 4KB of RAM for 630 each CPU). 631 632config AP_STACK_SIZE 633 hex 634 depends on SMP 635 default 0x1000 636 help 637 Each additional CPU started by U-Boot requires its own stack. This 638 option sets the stack size used by each CPU and directly affects 639 the memory used by this initialisation process. Typically 4KB is 640 enough space. 641 642config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED 643 bool 644 help 645 This option indicates that the turbo mode setting is not package 646 scoped. i.e. turbo_enable() needs to be called on not just the 647 bootstrap processor (BSP). 648 649config HAVE_VGA_BIOS 650 bool "Add a VGA BIOS image" 651 help 652 Select this option if you have a VGA BIOS image that you would 653 like to add to your ROM. 654 655config VGA_BIOS_FILE 656 string "VGA BIOS image filename" 657 depends on HAVE_VGA_BIOS 658 default "vga.bin" 659 help 660 The filename of the VGA BIOS image in the board directory. 661 662config VGA_BIOS_ADDR 663 hex "VGA BIOS image location" 664 depends on HAVE_VGA_BIOS 665 default 0xfff90000 666 help 667 The location of VGA BIOS image in the SPI flash. For example, base 668 address of 0xfff90000 indicates that the image will be put at offset 669 0x90000 from the beginning of a 1MB flash device. 670 671config HAVE_VBT 672 bool "Add a Video BIOS Table (VBT) image" 673 depends on HAVE_FSP 674 help 675 Select this option if you have a Video BIOS Table (VBT) image that 676 you would like to add to your ROM. This is normally required if you 677 are using an Intel FSP firmware that is complaint with spec 1.1 or 678 later to initialize the integrated graphics device (IGD). 679 680 Video BIOS Table, or VBT, provides platform and board specific 681 configuration information to the driver that is not discoverable 682 or available through other means. By other means the most used 683 method here is to read EDID table from the attached monitor, over 684 Display Data Channel (DDC) using two pin I2C serial interface. VBT 685 configuration is related to display hardware and is available via 686 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM). 687 688config VBT_FILE 689 string "Video BIOS Table (VBT) image filename" 690 depends on HAVE_VBT 691 default "vbt.bin" 692 help 693 The filename of the file to use as Video BIOS Table (VBT) image 694 in the board directory. 695 696config VBT_ADDR 697 hex "Video BIOS Table (VBT) image location" 698 depends on HAVE_VBT 699 default 0xfff90000 700 help 701 The location of Video BIOS Table (VBT) image in the SPI flash. For 702 example, base address of 0xfff90000 indicates that the image will 703 be put at offset 0x90000 from the beginning of a 1MB flash device. 704 705config VIDEO_FSP 706 bool "Enable FSP framebuffer driver support" 707 depends on HAVE_VBT && VIDEO 708 help 709 Turn on this option to enable a framebuffer driver when U-Boot is 710 using Video BIOS Table (VBT) image for FSP firmware to initialize 711 the integrated graphics device. 712 713config ROM_TABLE_ADDR 714 hex 715 default 0xf0000 716 help 717 All x86 tables happen to like the address range from 0x0f0000 718 to 0x100000. We use 0xf0000 as the starting address to store 719 those tables, including PIRQ routing table, Multi-Processor 720 table and ACPI table. 721 722config ROM_TABLE_SIZE 723 hex 724 default 0x10000 725 726config X86_HARDFP 727 bool "Support hardware floating point" 728 help 729 U-Boot generally does not make use of floating point. Where this is 730 needed, it can be enabled using this option. This adjusts the 731 start-up code for 64-bit mode and changes the compiler options for 732 64-bit to enable SSE. 733 734config HAVE_ITSS 735 bool "Enable ITSS" 736 help 737 Select this to include the driver for the Interrupt Timer 738 Subsystem (ITSS) which is found on several Intel devices. 739 740config HAVE_P2SB 741 bool "Enable P2SB" 742 depends on P2SB 743 help 744 Select this to include the driver for the Primary to 745 Sideband Bridge (P2SB) which is found on several Intel 746 devices. 747 748menu "System tables" 749 depends on !EFI && !SYS_COREBOOT 750 751config GENERATE_PIRQ_TABLE 752 bool "Generate a PIRQ table" 753 help 754 Generate a PIRQ routing table for this board. The PIRQ routing table 755 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 756 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 757 It specifies the interrupt router information as well how all the PCI 758 devices' interrupt pins are wired to PIRQs. 759 760config GENERATE_SFI_TABLE 761 bool "Generate a SFI (Simple Firmware Interface) table" 762 help 763 The Simple Firmware Interface (SFI) provides a lightweight method 764 for platform firmware to pass information to the operating system 765 via static tables in memory. Kernel SFI support is required to 766 boot on SFI-only platforms. If you have ACPI tables then these are 767 used instead. 768 769 U-Boot writes this table in write_sfi_table() just before booting 770 the OS. 771 772 For more information, see http://simplefirmware.org 773 774config GENERATE_MP_TABLE 775 bool "Generate an MP (Multi-Processor) table" 776 help 777 Generate an MP (Multi-Processor) table for this board. The MP table 778 provides a way for the operating system to support for symmetric 779 multiprocessing as well as symmetric I/O interrupt handling with 780 the local APIC and I/O APIC. 781 782config ACPI_GNVS_EXTERNAL 783 bool 784 help 785 Put the GNVS (Global Non-Volatile Sleeping) table separate from the 786 DSDT and add a pointer to the table from the DSDT. This allows 787 U-Boot to better control the address of the GNVS. 788 789endmenu 790 791config HAVE_ACPI_RESUME 792 bool "Enable ACPI S3 resume" 793 select ENABLE_MRC_CACHE 794 help 795 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping 796 state where all system context is lost except system memory. U-Boot 797 is responsible for restoring the machine state as it was before sleep. 798 It needs restore the memory controller, without overwriting memory 799 which is not marked as reserved. For the peripherals which lose their 800 registers, U-Boot needs to write the original value. When everything 801 is done, U-Boot needs to find out the wakeup vector provided by OSes 802 and jump there. 803 804config S3_VGA_ROM_RUN 805 bool "Re-run VGA option ROMs on S3 resume" 806 depends on HAVE_ACPI_RESUME 807 help 808 Execute VGA option ROMs in U-Boot when resuming from S3. Normally 809 this is needed when graphics console is being used in the kernel. 810 811 Turning it off can reduce some resume time, but be aware that your 812 graphics console won't work without VGA options ROMs. Set it to N 813 if your kernel is only on a serial console. 814 815config STACK_SIZE_RESUME 816 hex 817 depends on HAVE_ACPI_RESUME 818 default 0x1000 819 help 820 Estimated U-Boot's runtime stack size that needs to be reserved 821 during an ACPI S3 resume. 822 823config MAX_PIRQ_LINKS 824 int 825 default 8 826 help 827 This variable specifies the number of PIRQ interrupt links which are 828 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 829 Some newer chipsets offer more than four links, commonly up to PIRQH. 830 831config IRQ_SLOT_COUNT 832 int 833 default 128 834 help 835 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 836 which in turns forms a table of exact 4KiB. The default value 128 837 should be enough for most boards. If this does not fit your board, 838 change it according to your needs. 839 840config PCIE_ECAM_BASE 841 hex 842 default 0xe0000000 843 help 844 This is the memory-mapped address of PCI configuration space, which 845 is only available through the Enhanced Configuration Access 846 Mechanism (ECAM) with PCI Express. It can be set up almost 847 anywhere. Before it is set up, it is possible to access PCI 848 configuration space through I/O access, but memory access is more 849 convenient. Using this, PCI can be scanned and configured. This 850 should be set to a region that does not conflict with memory 851 assigned to PCI devices - i.e. the memory and prefetch regions, as 852 passed to pci_set_region(). 853 854config PCIE_ECAM_SIZE 855 hex 856 default 0x10000000 857 help 858 This is the size of memory-mapped address of PCI configuration space, 859 which is only available through the Enhanced Configuration Access 860 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 861 so a default 0x10000000 size covers all of the 256 buses which is the 862 maximum number of PCI buses as defined by the PCI specification. 863 864config I8259_PIC 865 bool "Enable Intel 8259 compatible interrupt controller" 866 default y 867 help 868 Intel 8259 ISA compatible chipset incorporates two 8259 (master and 869 slave) interrupt controllers. Include this to have U-Boot set up 870 the interrupt correctly. 871 872config APIC 873 bool "Enable Intel Advanced Programmable Interrupt Controller" 874 default y 875 help 876 The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible 877 for catching interrupts and distributing them to one or more CPU 878 cores. In most cases there are some LAPICs (local) for each core and 879 one I/O APIC. This conjunction is found on most modern x86 systems. 880 881config PINCTRL_ICH6 882 bool 883 help 884 Intel ICH6 compatible chipset pinctrl driver. It needs to work 885 together with the ICH6 compatible gpio driver. 886 887config I8254_TIMER 888 bool 889 default y 890 help 891 Intel 8254 timer contains three counters which have fixed uses. 892 Include this to have U-Boot set up the timer correctly. 893 894config SEABIOS 895 bool "Support booting SeaBIOS" 896 help 897 SeaBIOS is an open source implementation of a 16-bit X86 BIOS. 898 It can run in an emulator or natively on X86 hardware with the use 899 of coreboot/U-Boot. By turning on this option, U-Boot prepares 900 all the configuration tables that are necessary to boot SeaBIOS. 901 902 Check http://www.seabios.org/SeaBIOS for details. 903 904config HIGH_TABLE_SIZE 905 hex "Size of configuration tables which reside in high memory" 906 default 0x10000 907 depends on SEABIOS 908 help 909 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all 910 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot 911 puts a copy of configuration tables in high memory region which 912 is reserved on the stack before relocation. The region size is 913 determined by this option. 914 915 Increse it if the default size does not fit the board's needs. 916 This is most likely due to a large ACPI DSDT table is used. 917 918config INTEL_CAR_CQOS 919 bool "Support Intel Cache Quality of Service" 920 help 921 Cache Quality of Service allows more fine-grained control of cache 922 usage. As result, it is possible to set up a portion of L2 cache for 923 CAR and use the remainder for actual caching. 924 925# 926# Each bit in QOS mask controls this many bytes. This is calculated as: 927# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS 928# 929config CACHE_QOS_SIZE_PER_BIT 930 hex 931 depends on INTEL_CAR_CQOS 932 default 0x20000 # 128 KB 933 934config X86_OFFSET_U_BOOT 935 hex "Offset of U-Boot in ROM image" 936 depends on HAVE_TEXT_BASE 937 default TEXT_BASE 938 939config X86_OFFSET_SPL 940 hex "Offset of SPL in ROM image" 941 depends on SPL && X86 942 default SPL_TEXT_BASE 943 944config ACPI_GPE 945 bool "Support ACPI general-purpose events" 946 help 947 Enable a driver for ACPI GPEs to allow peripherals to send interrupts 948 via ACPI to the OS. In U-Boot this is only used when U-Boot itself 949 needs access to these interrupts. This can happen when it uses a 950 peripheral that is set up to use GPEs and so cannot use the normal 951 GPIO mechanism for polling an input. 952 953 See https://queue.acm.org/blogposting.cfm?id=18977 for more info 954 955config SPL_ACPI_GPE 956 bool "Support ACPI general-purpose events in SPL" 957 depends on SPL 958 help 959 Enable a driver for ACPI GPEs to allow peripherals to send interrupts 960 via ACPI to the OS. In U-Boot this is only used when U-Boot itself 961 needs access to these interrupts. This can happen when it uses a 962 peripheral that is set up to use GPEs and so cannot use the normal 963 GPIO mechanism for polling an input. 964 965 See https://queue.acm.org/blogposting.cfm?id=18977 for more info 966 967config TPL_ACPI_GPE 968 bool "Support ACPI general-purpose events in TPL" 969 depends on TPL 970 help 971 Enable a driver for ACPI GPEs to allow peripherals to send interrupts 972 via ACPI to the OS. In U-Boot this is only used when U-Boot itself 973 needs access to these interrupts. This can happen when it uses a 974 peripheral that is set up to use GPEs and so cannot use the normal 975 GPIO mechanism for polling an input. 976 977 See https://queue.acm.org/blogposting.cfm?id=18977 for more info 978 979config SA_PCIEX_LENGTH 980 hex 981 default 0x10000000 if (PCIEX_LENGTH_256MB) 982 default 0x8000000 if (PCIEX_LENGTH_128MB) 983 default 0x4000000 if (PCIEX_LENGTH_64MB) 984 default 0x10000000 985 help 986 This option allows you to select length of PCIEX region. 987 988config PCIEX_LENGTH_256MB 989 bool 990 991config PCIEX_LENGTH_128MB 992 bool 993 994config PCIEX_LENGTH_64MB 995 bool 996 997config INTEL_SOC 998 bool 999 help 1000 This is enabled on Intel SoCs that can support various advanced 1001 features such as power management (requiring asm/arch/pm.h), system 1002 agent (asm/arch/systemagent.h) and an I/O map for ACPI 1003 (asm/arch/iomap.h). 1004 1005 This cannot be selected in a defconfig file. It must be enabled by a 1006 'select' in the SoC's Kconfig. 1007 1008if INTEL_SOC 1009 1010config INTEL_ACPIGEN 1011 bool "Support ACPI table generation for Intel SoCs" 1012 depends on ACPIGEN 1013 help 1014 This option adds some functions used for programmatic generation of 1015 ACPI tables on Intel SoCs. This provides features for writing CPU 1016 information such as P states and T stages. Also included is a way 1017 to create a GNVS table and set it up. 1018 1019config INTEL_GMA_ACPI 1020 bool "Generate ACPI table for Intel GMA graphics" 1021 help 1022 The Intel GMA graphics driver in Linux expects an ACPI table 1023 which describes the layout of the registers and the display 1024 connected to the device. Enable this option to create this 1025 table so that graphics works correctly. 1026 1027config INTEL_GENERIC_WIFI 1028 bool "Enable generation of ACPI tables for Intel WiFi" 1029 help 1030 Select this option to provide code to a build generic WiFi ACPI table 1031 for Intel WiFi devices. This is not a WiFi driver and offers no 1032 network functionality. It is only here to generate the ACPI tables 1033 required by Linux. 1034 1035config INTEL_GMA_SWSMISCI 1036 bool 1037 help 1038 Select this option for Atom-based platforms which use the SWSMISCI 1039 register (0xe0) rather than the SWSCI register (0xe8). 1040 1041endif # INTEL_SOC 1042 1043config COREBOOT_SYSINFO 1044 bool "Support reading coreboot sysinfo" 1045 default y if SYS_COREBOOT 1046 help 1047 Select this option to read the coreboot sysinfo table on start-up, 1048 if present. This is written by coreboot before it exits and provides 1049 various pieces of information about the running system, including 1050 display, memory and build information. It is stored in 1051 struct sysinfo_t after parsing by get_coreboot_info(). 1052 1053config SPL_COREBOOT_SYSINFO 1054 bool "Support reading coreboot sysinfo" 1055 depends on SPL 1056 default y if COREBOOT_SYSINFO 1057 help 1058 Select this option to read the coreboot sysinfo table in SPL, 1059 if present. This is written by coreboot before it exits and provides 1060 various pieces of information about the running system, including 1061 display, memory and build information. It is stored in 1062 struct sysinfo_t after parsing by get_coreboot_info(). 1063 1064config ZBOOT 1065 bool "Support the zImage format" 1066 default y 1067 help 1068 Enable this to support booting the x86-specific zImage format. This 1069 uses a special, binary format containing information about the Linux 1070 format to boot. 1071 1072endmenu 1073