157429Smarkm/* SPDX-License-Identifier: GPL-2.0 */ 257429Smarkm/* 357429Smarkm * R9A06G032 sysctrl IDs 457429Smarkm * 557429Smarkm * Copyright (C) 2018 Renesas Electronics Europe Limited 665674Skris * 765674Skris * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> 865674Skris */ 965674Skris 1065674Skris#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ 1157429Smarkm#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ 1276262Sgreen 1376262Sgreen#define R9A06G032_CLK_PLL_USB 1 1476262Sgreen#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ 1565674Skris#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ 1665674Skris#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ 1765674Skris#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ 1865674Skris#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ 1965674Skris#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ 2065674Skris#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ 2165674Skris#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ 2265674Skris#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ 2365674Skris#define R9A06G032_CLK_25_PG4 26 2465674Skris#define R9A06G032_CLK_25_PG5 27 2565674Skris#define R9A06G032_CLK_25_PG6 28 2665674Skris#define R9A06G032_CLK_25_PG7 29 2765674Skris#define R9A06G032_CLK_25_PG8 30 2865674Skris#define R9A06G032_CLK_ADC 31 2965674Skris#define R9A06G032_CLK_ECAT100 32 3065674Skris#define R9A06G032_CLK_HSR100 33 3165674Skris#define R9A06G032_CLK_I2C0 34 3265674Skris#define R9A06G032_CLK_I2C1 35 3365674Skris#define R9A06G032_CLK_MII_REF 36 3465674Skris#define R9A06G032_CLK_NAND 37 3565674Skris#define R9A06G032_CLK_NOUSBP2_PG6 38 36296633Sdes#define R9A06G032_CLK_P1_PG2 39 3799050Sdes#define R9A06G032_CLK_P1_PG3 40 38296633Sdes#define R9A06G032_CLK_P1_PG4 41 3957429Smarkm#define R9A06G032_CLK_P4_PG3 42 4057429Smarkm#define R9A06G032_CLK_P4_PG4 43 4157429Smarkm#define R9A06G032_CLK_P6_PG1 44 4257429Smarkm#define R9A06G032_CLK_P6_PG2 45 4376262Sgreen#define R9A06G032_CLK_P6_PG3 46 4457429Smarkm#define R9A06G032_CLK_P6_PG4 47 4557429Smarkm#define R9A06G032_CLK_PCI_USB 48 46113911Sdes#define R9A06G032_CLK_QSPI0 49 47181111Sdes#define R9A06G032_CLK_QSPI1 50 4857429Smarkm#define R9A06G032_CLK_RGMII_REF 51 49181111Sdes#define R9A06G032_CLK_RMII_REF 52 50204917Sdes#define R9A06G032_CLK_SDIO0 53 51255767Sdes#define R9A06G032_CLK_SDIO1 54 5257429Smarkm#define R9A06G032_CLK_SERCOS100 55 5357429Smarkm#define R9A06G032_CLK_SLCD 56 5457429Smarkm#define R9A06G032_CLK_SPI0 57 5557429Smarkm#define R9A06G032_CLK_SPI1 58 5692559Sdes#define R9A06G032_CLK_SPI2 59 5757429Smarkm#define R9A06G032_CLK_SPI3 60 5865674Skris#define R9A06G032_CLK_SPI4 61 59113911Sdes#define R9A06G032_CLK_SPI5 62 6060576Skris#define R9A06G032_CLK_SWITCH 63 6157429Smarkm#define R9A06G032_HCLK_ECAT125 65 62157019Sdes#define R9A06G032_HCLK_PINCONFIG 66 6357429Smarkm#define R9A06G032_HCLK_SERCOS 67 64294328Sdes#define R9A06G032_HCLK_SGPIO2 68 65181111Sdes#define R9A06G032_HCLK_SGPIO3 69 6658585Skris#define R9A06G032_HCLK_SGPIO4 70 6757429Smarkm#define R9A06G032_HCLK_TIMER0 71 6857429Smarkm#define R9A06G032_HCLK_TIMER1 72 69157019Sdes#define R9A06G032_HCLK_USBF 73 7092559Sdes#define R9A06G032_HCLK_USBH 74 7199050Sdes#define R9A06G032_HCLK_USBPM 75 7257429Smarkm#define R9A06G032_CLK_48_PG_F 76 7358585Skris#define R9A06G032_CLK_48_PG4 77 7458585Skris#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ 7557429Smarkm#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ 7657429Smarkm#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ 7757429Smarkm#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */ 7857429Smarkm#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ 79126277Sdes#define R9A06G032_HCLK_CAN0 85 80126277Sdes#define R9A06G032_HCLK_CAN1 86 81157019Sdes#define R9A06G032_HCLK_DELTASIGMA 87 82157019Sdes#define R9A06G032_HCLK_PWMPTO 88 8357429Smarkm#define R9A06G032_HCLK_RSV 89 8457429Smarkm#define R9A06G032_HCLK_SGPIO0 90 8557429Smarkm#define R9A06G032_HCLK_SGPIO1 91 8676262Sgreen#define R9A06G032_RTOS_MDC 92 87162856Sdes#define R9A06G032_CLK_CM3 93 8876262Sgreen#define R9A06G032_CLK_DDRC 94 8957429Smarkm#define R9A06G032_CLK_ECAT25 95 9057429Smarkm#define R9A06G032_CLK_HSR50 96 9157429Smarkm#define R9A06G032_CLK_HW_RTOS 97 92126277Sdes#define R9A06G032_CLK_SERCOS50 98 93126277Sdes#define R9A06G032_HCLK_ADC 99 94126277Sdes#define R9A06G032_HCLK_CM3 100 95126277Sdes#define R9A06G032_HCLK_CRYPTO_EIP150 101 96126277Sdes#define R9A06G032_HCLK_CRYPTO_EIP93 102 97126277Sdes#define R9A06G032_HCLK_DDRC 103 98126277Sdes#define R9A06G032_HCLK_DMA0 104 99126277Sdes#define R9A06G032_HCLK_DMA1 105 10057429Smarkm#define R9A06G032_HCLK_GMAC0 106 10176262Sgreen#define R9A06G032_HCLK_GMAC1 107 102181111Sdes#define R9A06G032_HCLK_GPIO0 108 103181111Sdes#define R9A06G032_HCLK_GPIO1 109 104181111Sdes#define R9A06G032_HCLK_GPIO2 110 105181111Sdes#define R9A06G032_HCLK_HSR 111 106181111Sdes#define R9A06G032_HCLK_I2C0 112 107181111Sdes#define R9A06G032_HCLK_I2C1 113 108181111Sdes#define R9A06G032_HCLK_LCD 114 109181111Sdes#define R9A06G032_HCLK_MSEBI_M 115 110181111Sdes#define R9A06G032_HCLK_MSEBI_S 116 111181111Sdes#define R9A06G032_HCLK_NAND 117 112181111Sdes#define R9A06G032_HCLK_PG_I 118 113181111Sdes#define R9A06G032_HCLK_PG19 119 114181111Sdes#define R9A06G032_HCLK_PG20 120 115181111Sdes#define R9A06G032_HCLK_PG3 121 116240075Sdes#define R9A06G032_HCLK_PG4 122 117240075Sdes#define R9A06G032_HCLK_QSPI0 123 118181111Sdes#define R9A06G032_HCLK_QSPI1 124 119181111Sdes#define R9A06G032_HCLK_ROM 125 120181111Sdes#define R9A06G032_HCLK_RTC 126 121181111Sdes#define R9A06G032_HCLK_SDIO0 127 122181111Sdes#define R9A06G032_HCLK_SDIO1 128 123204917Sdes#define R9A06G032_HCLK_SEMAP 129 124204917Sdes#define R9A06G032_HCLK_SPI0 130 125204917Sdes#define R9A06G032_HCLK_SPI1 131 126204917Sdes#define R9A06G032_HCLK_SPI2 132 127204917Sdes#define R9A06G032_HCLK_SPI3 133 128204917Sdes#define R9A06G032_HCLK_SPI4 134 129204917Sdes#define R9A06G032_HCLK_SPI5 135 130204917Sdes#define R9A06G032_HCLK_SWITCH 136 131204917Sdes#define R9A06G032_HCLK_SWITCH_RG 137 132126277Sdes#define R9A06G032_HCLK_UART0 138 133126277Sdes#define R9A06G032_HCLK_UART1 139 134126277Sdes#define R9A06G032_HCLK_UART2 140 135126277Sdes#define R9A06G032_HCLK_UART3 141 136126277Sdes#define R9A06G032_HCLK_UART4 142 137126277Sdes#define R9A06G032_HCLK_UART5 143 13857429Smarkm#define R9A06G032_HCLK_UART6 144 13958585Skris#define R9A06G032_HCLK_UART7 145 140204917Sdes#define R9A06G032_CLK_UART0 146 141204917Sdes#define R9A06G032_CLK_UART1 147 14258585Skris#define R9A06G032_CLK_UART2 148 14358585Skris#define R9A06G032_CLK_UART3 149 144113911Sdes#define R9A06G032_CLK_UART4 150 145113911Sdes#define R9A06G032_CLK_UART5 151 146113911Sdes#define R9A06G032_CLK_UART6 152 14769591Sgreen#define R9A06G032_CLK_UART7 153 148255767Sdes 149255767Sdes#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ 150255767Sdes