1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2022 StarFive Technology Co., Ltd. 4 * Author: Yanhong Wang<yanhong.wang@starfivetech.com> 5 */ 6#include <asm/arch/eeprom.h> 7#include <asm/csr.h> 8#include <asm/sections.h> 9#include <dm.h> 10#include <linux/sizes.h> 11#include <log.h> 12#include <init.h> 13 14#define CSR_U74_FEATURE_DISABLE 0x7c1 15 16DECLARE_GLOBAL_DATA_PTR; 17 18static bool check_ddr_size(phys_size_t size) 19{ 20 switch (size) { 21 case SZ_2: 22 case SZ_4: 23 case SZ_8: 24 case SZ_16: 25 return true; 26 default: 27 return false; 28 } 29} 30 31int spl_dram_init(void) 32{ 33 int ret; 34 struct udevice *dev; 35 phys_size_t size; 36 37 ret = fdtdec_setup_mem_size_base(); 38 if (ret) 39 return ret; 40 41 /* Read the definition of the DDR size from eeprom, and if not, 42 * use the definition in DT 43 */ 44 size = (get_ddr_size_from_eeprom() >> 16) & 0xFF; 45 if (check_ddr_size(size)) 46 gd->ram_size = size << 30; 47 48 /* DDR init */ 49 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 50 if (ret) { 51 debug("DRAM init failed: %d\n", ret); 52 return ret; 53 } 54 55 return 0; 56} 57 58void harts_early_init(void) 59{ 60 /* 61 * Feature Disable CSR 62 * 63 * Clear feature disable CSR to '0' to turn on all features for 64 * each core. This operation must be in M-mode. 65 */ 66 if (CONFIG_IS_ENABLED(RISCV_MMODE)) 67 csr_write(CSR_U74_FEATURE_DISABLE, 0); 68} 69