1menu "RISC-V architecture"
2	depends on RISCV
3
4config SYS_ARCH
5	default "riscv"
6
7choice
8	prompt "Target select"
9	optional
10
11config TARGET_ANDES_AE350
12	bool "Support Andes ae350"
13
14config TARGET_MICROCHIP_ICICLE
15	bool "Support Microchip PolarFire-SoC Icicle Board"
16
17config TARGET_MILKV_DUO
18	bool "Support Milk-v Duo Board"
19
20config TARGET_OPENPITON_RISCV64
21	bool "Support RISC-V cores on OpenPiton SoC"
22
23config TARGET_QEMU_VIRT
24	bool "Support QEMU Virt Board"
25	select BOARD_LATE_INIT
26
27config TARGET_SIFIVE_UNLEASHED
28	bool "Support SiFive Unleashed Board"
29
30config TARGET_SIFIVE_UNMATCHED
31	bool "Support SiFive Unmatched Board"
32	select SYS_CACHE_SHIFT_6
33
34config TARGET_SIPEED_MAIX
35	bool "Support Sipeed Maix Board"
36	select SYS_CACHE_SHIFT_6
37
38config TARGET_STARFIVE_VISIONFIVE2
39	bool "Support StarFive VisionFive2 Board"
40	select BOARD_LATE_INIT
41
42config TARGET_TH1520_LPI4A
43	bool "Support Sipeed's TH1520 Lichee PI 4A Board"
44	select SYS_CACHE_SHIFT_6
45
46config TARGET_XILINX_MBV
47	bool "Support AMD/Xilinx MicroBlaze V"
48
49endchoice
50
51config SYS_ICACHE_OFF
52	bool "Do not enable icache"
53	help
54	  Do not enable instruction cache in U-Boot.
55
56config SPL_SYS_ICACHE_OFF
57	bool "Do not enable icache in SPL"
58	depends on SPL
59	default SYS_ICACHE_OFF
60	help
61	  Do not enable instruction cache in SPL.
62
63config SYS_DCACHE_OFF
64	bool "Do not enable dcache"
65	help
66	  Do not enable data cache in U-Boot.
67
68config SPL_SYS_DCACHE_OFF
69	bool "Do not enable dcache in SPL"
70	depends on SPL
71	default SYS_DCACHE_OFF
72	help
73	  Do not enable data cache in SPL.
74
75config SPL_ZERO_MEM_BEFORE_USE
76	bool "Zero memory before use"
77	depends on SPL
78	help
79	  Zero stack/GD/malloc area in SPL before using them, this is needed for
80	  Sifive core devices that uses L2 cache to store SPL.
81
82# board-specific options below
83source "board/andestech/ae350/Kconfig"
84source "board/emulation/qemu-riscv/Kconfig"
85source "board/microchip/mpfs_icicle/Kconfig"
86source "board/openpiton/riscv64/Kconfig"
87source "board/sifive/unleashed/Kconfig"
88source "board/sifive/unmatched/Kconfig"
89source "board/sipeed/maix/Kconfig"
90source "board/sophgo/milkv_duo/Kconfig"
91source "board/starfive/visionfive2/Kconfig"
92source "board/thead/th1520_lpi4a/Kconfig"
93source "board/xilinx/mbv/Kconfig"
94
95# platform-specific options below
96source "arch/riscv/cpu/andes/Kconfig"
97source "arch/riscv/cpu/cv1800b/Kconfig"
98source "arch/riscv/cpu/fu540/Kconfig"
99source "arch/riscv/cpu/fu740/Kconfig"
100source "arch/riscv/cpu/generic/Kconfig"
101source "arch/riscv/cpu/jh7110/Kconfig"
102
103# architecture-specific options below
104
105choice
106	prompt "Base ISA"
107	default ARCH_RV32I
108
109config ARCH_RV32I
110	bool "RV32I"
111	select 32BIT
112	help
113	  Choose this option to target the RV32I base integer instruction set.
114
115config ARCH_RV64I
116	bool "RV64I"
117	select 64BIT
118	select PHYS_64BIT
119	help
120	  Choose this option to target the RV64I base integer instruction set.
121
122endchoice
123
124config FRAMEPOINTER
125	bool "Build with frame pointer for stack unwinding"
126	help
127	  Choose this option to use the frame pointer so the stack can be
128	  unwound if needed. This is useful for tracing where faults came
129	  from as the source may be several functions back
130
131	  If you say Y here, then the code size will be increased due to
132	  having to store the fp.
133
134config SPL_FRAMEPOINTER
135	bool "Build SPL with frame pointer for stack unwinding"
136	help
137	  Choose this option to use the frame pointer so the stack can be
138	  unwound if needed. This is useful for tracing where faults came
139	  from as the source may be several functions back
140
141	  If you say Y here, then the code size will be increased due to
142	  having to store the fp.
143
144choice
145	prompt "Code Model"
146	default CMODEL_MEDLOW
147
148config CMODEL_MEDLOW
149	bool "medium low code model"
150	help
151	  U-Boot and its statically defined symbols must lie within a single 2 GiB
152	  address range and must lie between absolute addresses -2 GiB and +2 GiB.
153
154config CMODEL_MEDANY
155	bool "medium any code model"
156	help
157	  U-Boot and its statically defined symbols must be within any single 2 GiB
158	  address range.
159
160endchoice
161
162choice
163	prompt "Run Mode"
164	default RISCV_MMODE
165
166config RISCV_MMODE
167	bool "Machine"
168	help
169	  Choose this option to build U-Boot for RISC-V M-Mode.
170
171config RISCV_SMODE
172	bool "Supervisor"
173	imply DEBUG_UART
174	help
175	  Choose this option to build U-Boot for RISC-V S-Mode.
176
177endchoice
178
179choice
180	prompt "SPL Run Mode"
181	default SPL_RISCV_MMODE
182	depends on SPL
183
184config SPL_RISCV_MMODE
185	bool "Machine"
186	help
187	  Choose this option to build U-Boot SPL for RISC-V M-Mode.
188
189config SPL_RISCV_SMODE
190	bool "Supervisor"
191	help
192	  Choose this option to build U-Boot SPL for RISC-V S-Mode.
193
194endchoice
195
196config RISCV_ISA_C
197	bool "Emit compressed instructions"
198	default y
199	help
200	  Adds "C" to the ISA subsets that the toolchain is allowed to emit
201	  when building U-Boot, which results in compressed instructions in the
202	  U-Boot binary.
203
204config RISCV_ISA_F
205	bool "Standard extension for Single-Precision Floating Point"
206	default y
207	help
208	  Adds "F" to the ISA string passed to the compiler.
209
210config RISCV_ISA_D
211	bool "Standard extension for Double-Precision Floating Point"
212	depends on RISCV_ISA_F
213	default y
214	help
215	  Adds "D" to the ISA string passed to the compiler and changes the
216	  riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
217	  lp64d.
218
219config RISCV_ISA_ZBB
220	bool "Zbb extension support for bit manipulation instructions"
221	help
222	  Adds ZBB extension (basic bit manipulation) to the ISA subsets
223	  that the toolchain is allowed to emit when building U-Boot.
224	  The Zbb extension provides instructions to accelerate a number
225	  of bit-specific operations (count bit population, sign extending,
226	  bitrotation, etc) and enables optimized string routines.
227
228menu "Use assembly optimized implementation of string routines"
229
230config USE_ARCH_STRLEN
231	bool "Use an assembly optimized implementation of strlen"
232	default y
233	depends on RISCV_ISA_ZBB
234	help
235	  Enable the generation of an optimized version of strlen using
236	  Zbb extension.
237
238config SPL_USE_ARCH_STRLEN
239	bool "Use an assembly optimized implementation of strlen for SPL"
240	default y if USE_ARCH_STRLEN
241	depends on RISCV_ISA_ZBB
242	depends on SPL
243	help
244	  Enable the generation of an optimized version of strlen using
245	  Zbb extension.
246
247config TPL_USE_ARCH_STRLEN
248	bool "Use an assembly optimized implementation of strlen for TPL"
249	default y if USE_ARCH_STRLEN
250	depends on RISCV_ISA_ZBB
251	depends on TPL
252	help
253	  Enable the generation of an optimized version of strlen using
254	  Zbb extension.
255
256config USE_ARCH_STRCMP
257	bool "Use an assembly optimized implementation of strcmp"
258	default y
259	depends on RISCV_ISA_ZBB
260	help
261	  Enable the generation of an optimized version of strcmp using
262	  Zbb extension.
263
264config SPL_USE_ARCH_STRCMP
265	bool "Use an assembly optimized implementation of strcmp for SPL"
266	default y if USE_ARCH_STRCMP
267	depends on RISCV_ISA_ZBB
268	depends on SPL
269	help
270	  Enable the generation of an optimized version of strcmp using
271	  Zbb extension.
272
273config TPL_USE_ARCH_STRCMP
274	bool "Use an assembly optimized implementation of strcmp for TPL"
275	default y if USE_ARCH_STRCMP
276	depends on RISCV_ISA_ZBB
277	depends on TPL
278	help
279	  Enable the generation of an optimized version of strcmp using
280	  Zbb extension.
281
282config USE_ARCH_STRNCMP
283	bool "Use an assembly optimized implementation of strncmp"
284	default y
285	depends on RISCV_ISA_ZBB
286	help
287	  Enable the generation of an optimized version of strncmp using
288	  Zbb extension.
289
290config SPL_USE_ARCH_STRNCMP
291	bool "Use an assembly optimized implementation of strncmp for SPL"
292	default y if USE_ARCH_STRNCMP
293	depends on RISCV_ISA_ZBB
294	depends on SPL
295	help
296	  Enable the generation of an optimized version of strncmp using
297	  Zbb extension.
298
299config TPL_USE_ARCH_STRNCMP
300	bool "Use an assembly optimized implementation of strncmp for TPL"
301	default y if USE_ARCH_STRNCMP
302	depends on RISCV_ISA_ZBB
303	depends on TPL
304	help
305	  Enable the generation of an optimized version of strncmp using
306	  Zbb extension.
307
308endmenu
309
310config RISCV_ISA_A
311	def_bool y
312
313config DMA_ADDR_T_64BIT
314	bool
315	default y if 64BIT
316
317config RISCV_ACLINT
318	bool
319	depends on RISCV_MMODE
320	select REGMAP
321	select SYSCON
322	help
323	  The RISC-V ACLINT block holds memory-mapped control and status registers
324	  associated with software and timer interrupts.
325
326config SPL_RISCV_ACLINT
327	bool
328	depends on SPL_RISCV_MMODE
329	select SPL_REGMAP
330	select SPL_SYSCON
331	help
332	  The RISC-V ACLINT block holds memory-mapped control and status registers
333	  associated with software and timer interrupts.
334
335config SIFIVE_CACHE
336	bool
337	help
338	  This enables the operations to configure SiFive cache
339
340config ANDES_PLICSW
341	bool
342	depends on RISCV_MMODE || SPL_RISCV_MMODE
343	select REGMAP
344	select SYSCON
345	select SPL_REGMAP if SPL
346	select SPL_SYSCON if SPL
347	help
348	  The Andes PLICSW block holds memory-mapped claim and pending
349	  registers associated with software interrupt.
350
351config SMP
352	bool "Symmetric Multi-Processing"
353	depends on SBI_V01 || !RISCV_SMODE
354	help
355	  This enables support for systems with more than one CPU. If
356	  you say N here, U-Boot will run on single and multiprocessor
357	  machines, but will use only one CPU of a multiprocessor
358	  machine. If you say Y here, U-Boot will run on many, but not
359	  all, single processor machines.
360
361config SPL_SMP
362	bool "Symmetric Multi-Processing in SPL"
363	depends on SPL && SPL_RISCV_MMODE
364	default y
365	help
366	  This enables support for systems with more than one CPU in SPL.
367	  If you say N here, U-Boot SPL will run on single and multiprocessor
368	  machines, but will use only one CPU of a multiprocessor
369	  machine. If you say Y here, U-Boot SPL will run on many, but not
370	  all, single processor machines.
371
372config NR_CPUS
373	int "Maximum number of CPUs (2-32)"
374	range 2 32
375	depends on SMP || SPL_SMP
376	default 8
377	help
378	  On multiprocessor machines, U-Boot sets up a stack for each CPU.
379	  Stack memory is pre-allocated. U-Boot must therefore know the
380	  maximum number of CPUs that may be present.
381
382config SBI
383	bool
384	default y if RISCV_SMODE || SPL_RISCV_SMODE
385
386choice
387	prompt "SBI support"
388	default SBI_V02
389
390config SBI_V01
391	bool "SBI v0.1 support"
392	depends on SBI
393	help
394	  This config allows kernel to use SBI v0.1 APIs. This will be
395	  deprecated in future once legacy M-mode software are no longer in use.
396
397config SBI_V02
398	bool "SBI v0.2 or later support"
399	depends on SBI
400	help
401	  The SBI specification introduced the concept of extensions in version
402	  v0.2. With this configuration option U-Boot can detect and use SBI
403	  extensions. With the HSM extension introduced in SBI 0.2, only a
404	  single hart needs to boot and enter the operating system. The booting
405	  hart can bring up secondary harts one by one afterwards.
406
407	  Choose this option if OpenSBI release v0.7 or above is used together
408	  with U-Boot.
409
410endchoice
411
412config SBI_IPI
413	bool
414	depends on SBI
415	default y if RISCV_SMODE || SPL_RISCV_SMODE
416	depends on SMP
417
418config XIP
419	bool "XIP mode"
420	help
421	  XIP (eXecute In Place) is a method for executing code directly
422	  from a NOR flash memory without copying the code to ram.
423	  Say yes here if U-Boot boots from flash directly.
424
425config SPL_XIP
426	bool "Enable XIP mode for SPL"
427	help
428	  If SPL starts in read-only memory (XIP for example) then we shouldn't
429	  rely on lock variables (for example hart_lottery and available_harts_lock),
430	  this affects only SPL, other stages should proceed as non-XIP.
431
432config AVAILABLE_HARTS
433	bool "Send IPI by available harts"
434	default y
435	help
436	  By default, IPI sending mechanism will depend on available_harts.
437	  If disable this, it will send IPI by CPUs node numbers of device tree.
438
439config SHOW_REGS
440	bool "Show registers on unhandled exception"
441
442config RISCV_PRIV_1_9
443	bool "Use version 1.9 of the RISC-V priviledged specification"
444	help
445	  Older versions of the RISC-V priviledged specification had
446	  separate counter enable CSRs for each privilege mode. Writing
447	  to the unified mcounteren CSR on a processor implementing the
448	  old specification will result in an illegal instruction
449	  exception. In addition to counter CSR changes, the way virtual
450	  memory is configured was also changed.
451
452config STACK_SIZE_SHIFT
453	int
454	default 14
455
456config OF_BOARD_FIXUP
457	default y if OF_SEPARATE && RISCV_SMODE
458
459menu "Use assembly optimized implementation of memory routines"
460
461config USE_ARCH_MEMCPY
462	bool "Use an assembly optimized implementation of memcpy"
463	default y
464	help
465	  Enable the generation of an optimized version of memcpy.
466	  Such an implementation may be faster under some conditions
467	  but may increase the binary size.
468
469config SPL_USE_ARCH_MEMCPY
470	bool "Use an assembly optimized implementation of memcpy for SPL"
471	default y if USE_ARCH_MEMCPY
472	depends on SPL
473	help
474	  Enable the generation of an optimized version of memcpy.
475	  Such an implementation may be faster under some conditions
476	  but may increase the binary size.
477
478config TPL_USE_ARCH_MEMCPY
479	bool "Use an assembly optimized implementation of memcpy for TPL"
480	default y if USE_ARCH_MEMCPY
481	depends on TPL
482	help
483	  Enable the generation of an optimized version of memcpy.
484	  Such an implementation may be faster under some conditions
485	  but may increase the binary size.
486
487config USE_ARCH_MEMMOVE
488	bool "Use an assembly optimized implementation of memmove"
489	default y
490	help
491	  Enable the generation of an optimized version of memmove.
492	  Such an implementation may be faster under some conditions
493	  but may increase the binary size.
494
495config SPL_USE_ARCH_MEMMOVE
496	bool "Use an assembly optimized implementation of memmove for SPL"
497	default y if USE_ARCH_MEMCPY
498	depends on SPL
499	help
500	  Enable the generation of an optimized version of memmove.
501	  Such an implementation may be faster under some conditions
502	  but may increase the binary size.
503
504config TPL_USE_ARCH_MEMMOVE
505	bool "Use an assembly optimized implementation of memmove for TPL"
506	default y if USE_ARCH_MEMCPY
507	depends on TPL
508	help
509	  Enable the generation of an optimized version of memmove.
510	  Such an implementation may be faster under some conditions
511	  but may increase the binary size.
512
513config USE_ARCH_MEMSET
514	bool "Use an assembly optimized implementation of memset"
515	default y
516	help
517	  Enable the generation of an optimized version of memset.
518	  Such an implementation may be faster under some conditions
519	  but may increase the binary size.
520
521config SPL_USE_ARCH_MEMSET
522	bool "Use an assembly optimized implementation of memset for SPL"
523	default y if USE_ARCH_MEMSET
524	depends on SPL
525	help
526	  Enable the generation of an optimized version of memset.
527	  Such an implementation may be faster under some conditions
528	  but may increase the binary size.
529
530config TPL_USE_ARCH_MEMSET
531	bool "Use an assembly optimized implementation of memset for TPL"
532	default y if USE_ARCH_MEMSET
533	depends on TPL
534	help
535	  Enable the generation of an optimized version of memset.
536	  Such an implementation may be faster under some conditions
537	  but may increase the binary size.
538
539endmenu
540
541config SPL_LOAD_FIT_OPENSBI_OS_BOOT
542	bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT"
543	depends on SPL_LOAD_FIT
544	help
545	  Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly.
546	  This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper
547	  -> linux to u-boot SPL -> OpenSBI -> linux.
548
549endmenu
550