1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2002-2010 4 * Copyright 2020 NXP 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 */ 7 8#ifndef __ASM_GBL_DATA_H 9#define __ASM_GBL_DATA_H 10 11#include <linux/types.h> 12 13/* Architecture-specific global data */ 14struct arch_global_data { 15#if defined(CONFIG_FSL_ESDHC) 16 u32 sdhc_clk; 17 u32 sdhc_per_clk; 18#endif 19#if defined(CONFIG_MPC8xx) 20 unsigned long brg_clk; 21#endif 22 /* TODO: sjg@chromium.org: Should these be unslgned long? */ 23#if defined(CONFIG_MPC83xx) 24#ifdef CONFIG_CLK_MPC83XX 25 u32 core_clk; 26#else 27 /* There are other clocks in the MPC83XX */ 28 u32 csb_clk; 29# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ 30 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) 31 u32 tsec1_clk; 32 u32 tsec2_clk; 33 u32 usbdr_clk; 34# endif 35# if defined(CONFIG_ARCH_MPC834X) 36 u32 usbmph_clk; 37# endif /* CONFIG_ARCH_MPC834X */ 38 u32 core_clk; 39 u32 enc_clk; 40 u32 lbiu_clk; 41 u32 lclk_clk; 42# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ 43 defined(CONFIG_ARCH_MPC837X) 44 u32 pciexp1_clk; 45 u32 pciexp2_clk; 46# endif 47# if defined(CONFIG_ARCH_MPC837X) 48 u32 sata_clk; 49# endif 50# if defined(CONFIG_ARCH_MPC8360) 51 u32 mem_sec_clk; 52# endif /* CONFIG_ARCH_MPC8360 */ 53#endif 54#endif 55#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) 56 u32 lbc_clk; 57 void *cpu; 58#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */ 59#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ 60 defined(CONFIG_MPC86xx) 61 u32 i2c1_clk; 62 u32 i2c2_clk; 63#endif 64#if defined(CONFIG_QE) 65 u32 qe_clk; 66 u32 brg_clk; 67 uint mp_alloc_base; 68 uint mp_alloc_top; 69#endif /* CONFIG_QE */ 70#if defined(CONFIG_FSL_LAW) 71 u32 used_laws; 72#endif 73#if defined(CONFIG_E500) 74 u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32]; 75#endif 76 unsigned long reset_status; /* reset status register at boot */ 77#if defined(CONFIG_MPC83xx) 78 unsigned long arbiter_event_attributes; 79 unsigned long arbiter_event_address; 80#endif 81#ifdef CONFIG_SYS_FPGA_COUNT 82 unsigned fpga_state[CONFIG_SYS_FPGA_COUNT]; 83#endif 84#if defined(CONFIG_WD_MAX_RATE) 85 unsigned long long wdt_last; /* trace watch-dog triggering rate */ 86#endif 87#if defined(CONFIG_LWMON5) 88 unsigned long kbd_status; 89#endif 90}; 91 92#include <asm-generic/global_data.h> 93 94#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") 95 96#endif /* __ASM_GBL_DATA_H */ 97