1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2012-2016 Freescale Semiconductor, Inc.
4 */
5
6#ifndef __PAMU_H
7#define __PAMU_H
8
9#define CFG_NUM_PAMU		16
10#define NUM_PPAACT_ENTRIES	512
11#define NUM_SPAACT_ENTRIES	256
12
13/* PAMU_OFFSET to the next pamu space in ccsr */
14#define PAMU_OFFSET 0x1000
15
16#define PAMU_TABLE_ALIGNMENT 0x00001000
17
18#define PAMU_PAGE_SHIFT 12
19#define PAMU_PAGE_SIZE  4096U
20
21#define PAACE_M_COHERENCE_REQ   0x01
22
23#define PAACE_DA_HOST_CR                0x80
24#define PAACE_DA_HOST_CR_SHIFT          7
25
26#define PAACE_AF_PT                     0x00000002
27#define PAACE_AF_PT_SHIFT               1
28
29#define PAACE_PT_PRIMARY       0x0
30#define PAACE_PT_SECONDARY     0x1
31
32#define PPAACE_AF_WBAL			0xfffff000
33#define PPAACE_AF_WBAL_SHIFT		12
34
35#define	OME_NUMBER_ENTRIES      16   /* based on P4080 2.0 silicon plan */
36
37#define PAACE_IA_CID			0x00FF0000
38#define PAACE_IA_CID_SHIFT		16
39#define PAACE_IA_WCE			0x000000F0
40#define PAACE_IA_WCE_SHIFT		4
41#define PAACE_IA_ATM			0x0000000C
42#define PAACE_IA_ATM_SHIFT		2
43#define PAACE_IA_OTM			0x00000003
44#define PAACE_IA_OTM_SHIFT		0
45
46#define PAACE_OTM_NO_XLATE      0x00
47#define PAACE_OTM_IMMEDIATE     0x01
48#define PAACE_OTM_INDEXED       0x02
49#define PAACE_OTM_RESERVED      0x03
50#define PAACE_ATM_NO_XLATE      0x00
51#define PAACE_ATM_WINDOW_XLATE  0x01
52#define PAACE_ATM_PAGE_XLATE    0x02
53#define PAACE_ATM_WIN_PG_XLATE  \
54	(PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
55#define PAACE_WIN_TWBAL			0xfffff000
56#define PAACE_WIN_TWBAL_SHIFT		12
57#define PAACE_WIN_SWSE			0x00000fc0
58#define PAACE_WIN_SWSE_SHIFT		6
59
60#define PAACE_AF_AP			0x00000018
61#define PAACE_AF_AP_SHIFT		3
62#define PAACE_AF_DD			0x00000004
63#define PAACE_AF_DD_SHIFT		2
64#define PAACE_AF_PT			0x00000002
65#define PAACE_AF_PT_SHIFT		1
66#define PAACE_AF_V			0x00000001
67#define PAACE_AF_V_SHIFT		0
68#define PPAACE_AF_WSE			0x00000fc0
69#define PPAACE_AF_WSE_SHIFT		6
70#define PPAACE_AF_MW			0x00000020
71#define PPAACE_AF_MW_SHIFT		5
72
73#define PAACE_AP_PERMS_DENIED  0x0
74#define PAACE_AP_PERMS_QUERY   0x1
75#define PAACE_AP_PERMS_UPDATE  0x2
76#define PAACE_AP_PERMS_ALL     0x3
77
78#define SPAACE_AF_LIODN			0xffff0000
79#define SPAACE_AF_LIODN_SHIFT		16
80#define PAACE_V_VALID          0x1
81
82#define set_bf(v, m, x)             (v = ((v) & ~(m)) | (((x) << \
83					(m##_SHIFT)) & (m)))
84#define get_bf(v, m)            (((v) & (m)) >> (m##_SHIFT))
85
86#define DEFAULT_NUM_SUBWINDOWS		128
87#define PAMU_PCR_OFFSET 0xc10
88#define PAMU_PCR_PE	0x40000000
89
90struct pamu_addr_tbl {
91	phys_addr_t start_addr[10];
92	phys_addr_t end_addr[10];
93	phys_size_t size[10];
94};
95
96struct paace {
97	/* PAACE Offset 0x00 */
98	uint32_t wbah;			/* only valid for Primary PAACE */
99	uint32_t addr_bitfields;	/* See P/S PAACE_AF_* */
100
101	/* PAACE Offset 0x08 */
102	/* Interpretation of first 32 bits dependent on DD above */
103	union {
104		struct {
105			/* Destination ID, see PAACE_DID_* defines */
106			uint8_t did;
107			/* Partition ID */
108			uint8_t pid;
109			/* Snoop ID */
110			uint8_t snpid;
111			/* coherency_required : 1 reserved : 7 */
112			uint8_t coherency_required; /* See PAACE_DA_* */
113		} to_host;
114		struct {
115			/* Destination ID, see PAACE_DID_* defines */
116			uint8_t  did;
117			uint8_t  reserved1;
118			uint16_t reserved2;
119		} to_io;
120	} domain_attr;
121
122	/* Implementation attributes + window count + address & operation
123	 * translation modes
124	 */
125	uint32_t impl_attr;			/* See PAACE_IA_* */
126
127	/* PAACE Offset 0x10 */
128	/* Translated window base address */
129	uint32_t twbah;
130	uint32_t win_bitfields;			/* See PAACE_WIN_* */
131
132	/* PAACE Offset 0x18 */
133	/* first secondary paace entry */
134	uint32_t fspi;			/* only valid for Primary PAACE */
135	union {
136		struct {
137			uint8_t ioea;
138			uint8_t moea;
139			uint8_t ioeb;
140			uint8_t moeb;
141		} immed_ot;
142		struct {
143			uint16_t reserved;
144			uint16_t omi;
145		} index_ot;
146	} op_encode;
147
148	/* PAACE Offset 0x20 */
149	uint32_t reserved1[2];			/* not currently implemented */
150
151	/* PAACE Offset 0x28 */
152	uint32_t reserved2[2];			/* not currently implemented */
153
154	/* PAACE Offset 0x30 */
155	uint32_t reserved3[2];			/* not currently implemented */
156
157	/* PAACE Offset 0x38 */
158	uint32_t reserved4[2];			/* not currently implemented */
159
160};
161
162int pamu_init(void);
163void pamu_enable(void);
164void pamu_disable(void);
165int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn);
166int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s);
167
168#endif
169