1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6#ifndef _ASM_MPC85xx_CONFIG_H_ 7#define _ASM_MPC85xx_CONFIG_H_ 8 9/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 10 11#include <fsl_ddrc_version.h> 12 13#if defined(CONFIG_ARCH_MPC8548) 14#define CFG_SYS_FSL_SRIO_MAX_PORTS 1 15#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 16#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 17#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 18 19#elif defined(CONFIG_ARCH_P1021) 20#define QE_MURAM_SIZE 0x6000UL 21#define MAX_QE_RISC 1 22#define QE_NUM_OF_SNUM 28 23 24#elif defined(CONFIG_ARCH_P1023) 25#define CFG_SYS_NUM_FMAN 1 26#define CFG_SYS_NUM_FM1_DTSEC 2 27#define CFG_SYS_QMAN_NUM_PORTALS 3 28#define CFG_SYS_BMAN_NUM_PORTALS 3 29#define CFG_SYS_FM_MURAM_SIZE 0x10000 30 31/* P1025 is lower end variant of P1021 */ 32#elif defined(CONFIG_ARCH_P1025) 33#define QE_MURAM_SIZE 0x6000UL 34#define MAX_QE_RISC 1 35#define QE_NUM_OF_SNUM 28 36 37#elif defined(CONFIG_ARCH_P2020) 38#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 39#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 40#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 41#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 42 43#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ 44#define CFG_SYS_NUM_FMAN 1 45#define CFG_SYS_NUM_FM1_DTSEC 5 46#define CFG_SYS_NUM_FM1_10GEC 1 47#define CFG_SYS_FM_MURAM_SIZE 0x28000 48#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 49#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 50#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 51#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 52 53#elif defined(CONFIG_ARCH_P3041) 54#define CFG_SYS_NUM_FMAN 1 55#define CFG_SYS_NUM_FM1_DTSEC 5 56#define CFG_SYS_NUM_FM1_10GEC 1 57#define CFG_SYS_FM_MURAM_SIZE 0x28000 58#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 59#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 60#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 61#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 62 63#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ 64#define CFG_SYS_NUM_FMAN 2 65#define CFG_SYS_NUM_FM1_DTSEC 4 66#define CFG_SYS_NUM_FM2_DTSEC 4 67#define CFG_SYS_NUM_FM1_10GEC 1 68#define CFG_SYS_NUM_FM2_10GEC 1 69#define CFG_SYS_FM_MURAM_SIZE 0x28000 70#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 71#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 72#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 73#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 74#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 75 76#elif defined(CONFIG_ARCH_P5040) 77#define CFG_SYS_NUM_FMAN 2 78#define CFG_SYS_NUM_FM1_DTSEC 5 79#define CFG_SYS_NUM_FM1_10GEC 1 80#define CFG_SYS_NUM_FM2_DTSEC 5 81#define CFG_SYS_NUM_FM2_10GEC 1 82#define CFG_SYS_FM_MURAM_SIZE 0x28000 83#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 84 85 86#elif defined(CONFIG_ARCH_T4240) 87#ifdef CONFIG_ARCH_T4240 88#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 89#define CFG_SYS_NUM_FM1_DTSEC 8 90#define CFG_SYS_NUM_FM1_10GEC 2 91#define CFG_SYS_NUM_FM2_DTSEC 8 92#define CFG_SYS_NUM_FM2_10GEC 2 93#else 94#define CFG_SYS_NUM_FM1_DTSEC 6 95#define CFG_SYS_NUM_FM1_10GEC 1 96#define CFG_SYS_NUM_FM2_DTSEC 8 97#define CFG_SYS_NUM_FM2_10GEC 1 98#endif 99#define CFG_SYS_FSL_SRDS_3 100#define CFG_SYS_FSL_SRDS_4 101#define CFG_SYS_NUM_FMAN 2 102#define CFG_SYS_PME_CLK 0 103#define CFG_SYS_FM1_CLK 3 104#define CFG_SYS_FM2_CLK 3 105#define CFG_SYS_FM_MURAM_SIZE 0x60000 106#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 107#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 108#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 109 110#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) 111#define CFG_SYS_NUM_FMAN 1 112#define CFG_SYS_FM1_CLK 0 113#define CFG_SYS_FM_MURAM_SIZE 0x60000 114 115#ifdef CONFIG_ARCH_B4860 116#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 117#define CFG_SYS_NUM_FM1_DTSEC 6 118#define CFG_SYS_NUM_FM1_10GEC 2 119#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 120#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 121#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 122#else 123#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 124#define CFG_SYS_NUM_FM1_DTSEC 4 125#define CFG_SYS_NUM_FM1_10GEC 0 126#endif 127 128#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) 129#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 130#define CFG_SYS_NUM_FMAN 1 131#define CFG_SYS_NUM_FM1_DTSEC 5 132#define CFG_PME_PLAT_CLK_DIV 2 133#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV 134#define CFG_FM_PLAT_CLK_DIV 1 135#define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV 136#define CFG_SYS_FM_MURAM_SIZE 0x30000 137#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 138#define QE_MURAM_SIZE 0x6000UL 139#define MAX_QE_RISC 1 140#define QE_NUM_OF_SNUM 28 141 142#elif defined(CONFIG_ARCH_T1024) 143#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 144#define CFG_SYS_NUM_FMAN 1 145#define CFG_SYS_NUM_FM1_DTSEC 4 146#define CFG_SYS_NUM_FM1_10GEC 1 147#define CFG_SYS_FM1_CLK 0 148#define CFG_QBMAN_CLK_DIV 1 149#define CFG_SYS_FM_MURAM_SIZE 0x30000 150#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 151#define QE_MURAM_SIZE 0x6000UL 152#define MAX_QE_RISC 1 153#define QE_NUM_OF_SNUM 28 154 155#elif defined(CONFIG_ARCH_T2080) 156#define CFG_SYS_NUM_FMAN 1 157#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 158#if defined(CONFIG_ARCH_T2080) 159#define CFG_SYS_NUM_FM1_DTSEC 8 160#define CFG_SYS_NUM_FM1_10GEC 4 161#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 162#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 163#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 164#endif 165#define CFG_PME_PLAT_CLK_DIV 1 166#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV 167#define CFG_SYS_FM1_CLK 0 168#define CFG_SYS_FM_MURAM_SIZE 0x28000 169#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 170 171 172#elif defined(CONFIG_ARCH_C29X) 173#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000 174 175#endif 176 177#endif /* _ASM_MPC85xx_CONFIG_H_ */ 178