1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P2020 Silicon/SoC Device Tree Source (post include)
4 *
5 * Copyright 2013 Freescale Semiconductor Inc.
6 * Copyright 2019 NXP
7 */
8
9&soc {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	device_type = "soc";
13	compatible = "fsl,p2020-immr", "simple-bus";
14	bus-frequency = <0x0>;
15
16	ecm-law@0 {
17		compatible = "fsl,ecm-law";
18		reg = <0x0 0x1000>;
19		fsl,num-laws = <12>;
20	};
21
22	ecm@1000 {
23		compatible = "fsl,p2020-ecm", "fsl,ecm";
24		reg = <0x1000 0x1000>;
25		interrupts = <17 2 0 0>;
26	};
27
28	memory-controller@2000 {
29		compatible = "fsl,p2020-memory-controller";
30		reg = <0x2000 0x1000>;
31		interrupts = <18 2 0 0>;
32	};
33
34/include/ "pq3-i2c-0.dtsi"
35/include/ "pq3-i2c-1.dtsi"
36/include/ "pq3-duart-0.dtsi"
37
38	espi0: spi@7000 {
39		compatible = "fsl,mpc8536-espi";
40		#address-cells = <1>;
41		#size-cells = <0>;
42		reg = <0x7000 0x1000>;
43		interrupts = < 0x3b 0x02 0x00 0x00 >;
44		fsl,espi-num-chipselects = <4>;
45	};
46
47/include/ "pq3-dma-1.dtsi"
48/include/ "pq3-gpio-0.dtsi"
49
50	L2: l2-cache-controller@20000 {
51		compatible = "fsl,p2020-l2-cache-controller";
52		reg = <0x20000 0x1000>;
53		cache-line-size = <32>; /* 32 bytes */
54		cache-size = <0x80000>; /* L2,512K */
55		interrupts = <16 2 0 0>;
56	};
57
58/include/ "pq3-dma-0.dtsi"
59
60	usb@22000 {
61		compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
62		reg = <0x22000 0x1000>;
63		#address-cells = <1>;
64		#size-cells = <0>;
65		interrupts = <28 0x2 0 0>;
66		phy_type = "ulpi";
67	};
68
69/include/ "pq3-etsec1-0.dtsi"
70/include/ "pq3-etsec1-timer-0.dtsi"
71
72	ptp_clock@24e00 {
73		interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
74	};
75
76/include/ "pq3-etsec1-1.dtsi"
77/include/ "pq3-etsec1-2.dtsi"
78
79	esdhc: sdhc@2e000 {
80		compatible = "fsl,p2020-esdhc", "fsl,esdhc";
81		reg = <0x2e000 0x1000>;
82		interrupts = <72 0x2 0 0>;
83		/* Filled in by U-Boot */
84		clock-frequency = <0>;
85	};
86
87/include/ "pq3-sec3.1-0.dtsi"
88/include/ "pq3-mpic.dtsi"
89/include/ "pq3-mpic-timer-B.dtsi"
90
91	global-utilities@e0000 {
92		compatible = "fsl,p2020-guts";
93		reg = <0xe0000 0x1000>;
94		fsl,has-rstcr;
95	};
96
97	pmc: power@e0070 {
98		compatible = "fsl,mpc8548-pmc";
99		reg = <0xe0070 0x20>;
100	};
101};
102
103/* PCIe controller base address 0x8000 */
104&pci2 {
105	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
106	law_trgt_if = <0>;
107	#address-cells = <3>;
108	#size-cells = <2>;
109	device_type = "pci";
110	bus-range = <0x0 0xff>;
111	clock-frequency = <33333333>;
112	interrupts = <24 2 0 0>;
113
114	pcie@0 {
115		reg = <0 0 0 0 0>;
116		#interrupt-cells = <1>;
117		#size-cells = <2>;
118		#address-cells = <3>;
119		device_type = "pci";
120		interrupts = <24 2 0 0>;
121		interrupt-map-mask = <0xf800 0 0 7>;
122
123		interrupt-map = <
124			/* IDSEL 0x0 */
125			0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
126			0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
127			0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
128			0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
129			>;
130	};
131};
132
133/* PCIe controller base address 0x9000 */
134&pci1 {
135	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
136	law_trgt_if = <1>;
137	#address-cells = <3>;
138	#size-cells = <2>;
139	device_type = "pci";
140	bus-range = <0x0 0xff>;
141	clock-frequency = <33333333>;
142	interrupts = <25 2 0 0>;
143
144	pcie@0 {
145		reg = <0 0 0 0 0>;
146		#interrupt-cells = <1>;
147		#size-cells = <2>;
148		#address-cells = <3>;
149		device_type = "pci";
150		interrupts = <25 2 0 0>;
151		interrupt-map-mask = <0xf800 0 0 7>;
152
153		interrupt-map = <
154			/* IDSEL 0x0 */
155			0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
156			0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
157			0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
158			0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
159			>;
160	};
161};
162
163/* PCIe controller base address 0xa000 */
164&pci0 {
165	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
166	law_trgt_if = <2>;
167	#address-cells = <3>;
168	#size-cells = <2>;
169	device_type = "pci";
170	bus-range = <0x0 0xff>;
171	clock-frequency = <33333333>;
172	interrupts = <26 2 0 0>;
173
174	pcie@0 {
175		reg = <0 0 0 0 0>;
176		#interrupt-cells = <1>;
177		#size-cells = <2>;
178		#address-cells = <3>;
179		device_type = "pci";
180		interrupts = <26 2 0 0>;
181		interrupt-map-mask = <0xf800 0 0 7>;
182		interrupt-map = <
183			/* IDSEL 0x0 */
184			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
185			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
186			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
187			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
188			>;
189	};
190};
191
192&lbc {
193	#address-cells = <2>;
194	#size-cells = <1>;
195	compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
196	interrupts = <19 2 0 0>;
197};
198