1menu "mpc8xx CPU"
2	depends on MPC8xx
3
4config SYS_CPU
5	default "mpc8xx"
6
7choice
8	prompt "Target select"
9	optional
10
11config TARGET_MCR3000
12	bool "Support MCR3000 board from CSSI"
13
14config TARGET_CMPC885
15	bool "Support CMPC885 board from CSSI"
16
17endchoice
18
19choice
20	prompt "CPU select"
21	default MPC866
22
23config MPC866
24	bool "MPC866"
25	select SYS_CACHE_SHIFT_4
26
27config MPC885
28	bool "MPC885"
29	select SYS_CACHE_SHIFT_4
30
31endchoice
32
33choice
34	prompt "Microcode patch selection"
35	default NO_UCODE_PATCH
36	help
37	  This allows loading of CPM microcode.
38
39	  Only one microcode can be loaded at a time.
40
41config NO_UCODE_PATCH
42	bool "None"
43
44config USB_SOF_UCODE_PATCH
45	bool "USB SOF patch"
46	depends on MPC885
47	help
48	  This microcode fixes CPM15 errata:
49
50	  When the USB controller is configured in Host mode, and the
51	  SOF generation (SFTE=1 in USMOD register) is being used,
52	  there may be false CRC error indication in other SCCs.
53	  Although the data is received correctly, the CRC result
54	  will be corrupted.
55
56config SMC_UCODE_PATCH
57	bool "SMC relocation patch"
58	help
59	  This microcode relocates SMC1 and SMC2 parameter RAMs to allow
60	  extended parameter RAM for SCC3 and SCC4 (ex: for QMC mode)
61
62config SMC1_RPBASE
63	hex "SMC1 relocation offset"
64	depends on SMC_UCODE_PATCH
65	default 0x1e80
66	help
67	  Offset of SMC1 parameter RAM to be written to RPBASE register.
68
69config SMC2_RPBASE
70	hex "SMC2 relocation offset"
71	depends on SMC_UCODE_PATCH
72	default 0x1f80
73	help
74	  Offset of SMC2 parameter RAM to be written to RPBASE register.
75
76endchoice
77
78comment "Specific commands"
79
80config CMD_IMMAP
81	bool "Enable various commands to dump IMMR information"
82	help
83	  This enables various commands such as:
84
85	    siuinfo - print System Interface Unit (SIU) registers
86	    memcinfo - print Memory Controller registers
87
88comment "Configuration Registers"
89
90config SYS_SIUMCR
91	hex "SIUMCR register"
92	help
93	  SIU Module Configuration (11-6)
94
95config SYS_SYPCR
96	hex "SYPCR register" if !WDT_MPC8xxx
97	default 0x0
98	help
99	  System Protection Control (11-9)
100
101config SYS_TBSCR
102	hex "TBSCR register"
103	help
104	  Time Base Status and Control (11-26)
105
106config SYS_PISCR
107	hex "PISCR register"
108	help
109	  Periodic Interrupt Status and Control (11-31)
110
111config SYS_PLPRCR_BOOL
112	bool "Customise PLPRCR"
113
114config SYS_PLPRCR
115	hex "PLPRCR register"
116	depends on SYS_PLPRCR_BOOL
117	help
118	  PLL, Low-Power, and Reset Control Register (15-30)
119
120config SYS_SCCR
121	hex "SCCR register"
122	help
123	  System Clock and reset Control Register (15-27)
124
125config SYS_SCCR_MASK
126	hex "MASK for setting SCCR register"
127
128config SYS_DER
129	hex "DER register"
130	help
131	  Debug Event Register (37-47)
132
133source "board/cssi/mcr3000/Kconfig"
134
135source "board/cssi/cmpc885/Kconfig"
136endmenu
137