1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon pow. 7 */ 8 9#ifndef __CVMX_POW_DEFS_H__ 10#define __CVMX_POW_DEFS_H__ 11 12#define CVMX_POW_BIST_STAT (0x00016700000003F8ull) 13#define CVMX_POW_DS_PC (0x0001670000000398ull) 14#define CVMX_POW_ECC_ERR (0x0001670000000218ull) 15#define CVMX_POW_IQ_CNTX(offset) (0x0001670000000340ull + ((offset) & 7) * 8) 16#define CVMX_POW_IQ_COM_CNT (0x0001670000000388ull) 17#define CVMX_POW_IQ_INT (0x0001670000000238ull) 18#define CVMX_POW_IQ_INT_EN (0x0001670000000240ull) 19#define CVMX_POW_IQ_THRX(offset) (0x00016700000003A0ull + ((offset) & 7) * 8) 20#define CVMX_POW_NOS_CNT (0x0001670000000228ull) 21#define CVMX_POW_NW_TIM (0x0001670000000210ull) 22#define CVMX_POW_PF_RST_MSK (0x0001670000000230ull) 23#define CVMX_POW_PP_GRP_MSKX(offset) (0x0001670000000000ull + ((offset) & 15) * 8) 24#define CVMX_POW_QOS_RNDX(offset) (0x00016700000001C0ull + ((offset) & 7) * 8) 25#define CVMX_POW_QOS_THRX(offset) (0x0001670000000180ull + ((offset) & 7) * 8) 26#define CVMX_POW_TS_PC (0x0001670000000390ull) 27#define CVMX_POW_WA_COM_PC (0x0001670000000380ull) 28#define CVMX_POW_WA_PCX(offset) (0x0001670000000300ull + ((offset) & 7) * 8) 29#define CVMX_POW_WQ_INT (0x0001670000000200ull) 30#define CVMX_POW_WQ_INT_CNTX(offset) (0x0001670000000100ull + ((offset) & 15) * 8) 31#define CVMX_POW_WQ_INT_PC (0x0001670000000208ull) 32#define CVMX_POW_WQ_INT_THRX(offset) (0x0001670000000080ull + ((offset) & 15) * 8) 33#define CVMX_POW_WS_PCX(offset) (0x0001670000000280ull + ((offset) & 15) * 8) 34 35/** 36 * cvmx_pow_bist_stat 37 * 38 * Contains the BIST status for the POW memories ('0' = pass, '1' = fail). 39 * 40 */ 41union cvmx_pow_bist_stat { 42 u64 u64; 43 struct cvmx_pow_bist_stat_s { 44 u64 reserved_32_63 : 32; 45 u64 pp : 16; 46 u64 reserved_0_15 : 16; 47 } s; 48 struct cvmx_pow_bist_stat_cn30xx { 49 u64 reserved_17_63 : 47; 50 u64 pp : 1; 51 u64 reserved_9_15 : 7; 52 u64 cam : 1; 53 u64 nbt1 : 1; 54 u64 nbt0 : 1; 55 u64 index : 1; 56 u64 fidx : 1; 57 u64 nbr1 : 1; 58 u64 nbr0 : 1; 59 u64 pend : 1; 60 u64 adr : 1; 61 } cn30xx; 62 struct cvmx_pow_bist_stat_cn31xx { 63 u64 reserved_18_63 : 46; 64 u64 pp : 2; 65 u64 reserved_9_15 : 7; 66 u64 cam : 1; 67 u64 nbt1 : 1; 68 u64 nbt0 : 1; 69 u64 index : 1; 70 u64 fidx : 1; 71 u64 nbr1 : 1; 72 u64 nbr0 : 1; 73 u64 pend : 1; 74 u64 adr : 1; 75 } cn31xx; 76 struct cvmx_pow_bist_stat_cn38xx { 77 u64 reserved_32_63 : 32; 78 u64 pp : 16; 79 u64 reserved_10_15 : 6; 80 u64 cam : 1; 81 u64 nbt : 1; 82 u64 index : 1; 83 u64 fidx : 1; 84 u64 nbr1 : 1; 85 u64 nbr0 : 1; 86 u64 pend1 : 1; 87 u64 pend0 : 1; 88 u64 adr1 : 1; 89 u64 adr0 : 1; 90 } cn38xx; 91 struct cvmx_pow_bist_stat_cn38xx cn38xxp2; 92 struct cvmx_pow_bist_stat_cn31xx cn50xx; 93 struct cvmx_pow_bist_stat_cn52xx { 94 u64 reserved_20_63 : 44; 95 u64 pp : 4; 96 u64 reserved_9_15 : 7; 97 u64 cam : 1; 98 u64 nbt1 : 1; 99 u64 nbt0 : 1; 100 u64 index : 1; 101 u64 fidx : 1; 102 u64 nbr1 : 1; 103 u64 nbr0 : 1; 104 u64 pend : 1; 105 u64 adr : 1; 106 } cn52xx; 107 struct cvmx_pow_bist_stat_cn52xx cn52xxp1; 108 struct cvmx_pow_bist_stat_cn56xx { 109 u64 reserved_28_63 : 36; 110 u64 pp : 12; 111 u64 reserved_10_15 : 6; 112 u64 cam : 1; 113 u64 nbt : 1; 114 u64 index : 1; 115 u64 fidx : 1; 116 u64 nbr1 : 1; 117 u64 nbr0 : 1; 118 u64 pend1 : 1; 119 u64 pend0 : 1; 120 u64 adr1 : 1; 121 u64 adr0 : 1; 122 } cn56xx; 123 struct cvmx_pow_bist_stat_cn56xx cn56xxp1; 124 struct cvmx_pow_bist_stat_cn38xx cn58xx; 125 struct cvmx_pow_bist_stat_cn38xx cn58xxp1; 126 struct cvmx_pow_bist_stat_cn61xx { 127 u64 reserved_20_63 : 44; 128 u64 pp : 4; 129 u64 reserved_12_15 : 4; 130 u64 cam : 1; 131 u64 nbr : 3; 132 u64 nbt : 4; 133 u64 index : 1; 134 u64 fidx : 1; 135 u64 pend : 1; 136 u64 adr : 1; 137 } cn61xx; 138 struct cvmx_pow_bist_stat_cn63xx { 139 u64 reserved_22_63 : 42; 140 u64 pp : 6; 141 u64 reserved_12_15 : 4; 142 u64 cam : 1; 143 u64 nbr : 3; 144 u64 nbt : 4; 145 u64 index : 1; 146 u64 fidx : 1; 147 u64 pend : 1; 148 u64 adr : 1; 149 } cn63xx; 150 struct cvmx_pow_bist_stat_cn63xx cn63xxp1; 151 struct cvmx_pow_bist_stat_cn66xx { 152 u64 reserved_26_63 : 38; 153 u64 pp : 10; 154 u64 reserved_12_15 : 4; 155 u64 cam : 1; 156 u64 nbr : 3; 157 u64 nbt : 4; 158 u64 index : 1; 159 u64 fidx : 1; 160 u64 pend : 1; 161 u64 adr : 1; 162 } cn66xx; 163 struct cvmx_pow_bist_stat_cn70xx { 164 u64 reserved_12_63 : 52; 165 u64 cam : 1; 166 u64 reserved_10_10 : 1; 167 u64 nbr : 2; 168 u64 reserved_6_7 : 2; 169 u64 nbt : 2; 170 u64 index : 1; 171 u64 fidx : 1; 172 u64 pend : 1; 173 u64 adr : 1; 174 } cn70xx; 175 struct cvmx_pow_bist_stat_cn70xx cn70xxp1; 176 struct cvmx_pow_bist_stat_cn61xx cnf71xx; 177}; 178 179typedef union cvmx_pow_bist_stat cvmx_pow_bist_stat_t; 180 181/** 182 * cvmx_pow_ds_pc 183 * 184 * Counts the number of de-schedule requests. Write to clear. 185 * 186 */ 187union cvmx_pow_ds_pc { 188 u64 u64; 189 struct cvmx_pow_ds_pc_s { 190 u64 reserved_32_63 : 32; 191 u64 ds_pc : 32; 192 } s; 193 struct cvmx_pow_ds_pc_s cn30xx; 194 struct cvmx_pow_ds_pc_s cn31xx; 195 struct cvmx_pow_ds_pc_s cn38xx; 196 struct cvmx_pow_ds_pc_s cn38xxp2; 197 struct cvmx_pow_ds_pc_s cn50xx; 198 struct cvmx_pow_ds_pc_s cn52xx; 199 struct cvmx_pow_ds_pc_s cn52xxp1; 200 struct cvmx_pow_ds_pc_s cn56xx; 201 struct cvmx_pow_ds_pc_s cn56xxp1; 202 struct cvmx_pow_ds_pc_s cn58xx; 203 struct cvmx_pow_ds_pc_s cn58xxp1; 204 struct cvmx_pow_ds_pc_s cn61xx; 205 struct cvmx_pow_ds_pc_s cn63xx; 206 struct cvmx_pow_ds_pc_s cn63xxp1; 207 struct cvmx_pow_ds_pc_s cn66xx; 208 struct cvmx_pow_ds_pc_s cn70xx; 209 struct cvmx_pow_ds_pc_s cn70xxp1; 210 struct cvmx_pow_ds_pc_s cnf71xx; 211}; 212 213typedef union cvmx_pow_ds_pc cvmx_pow_ds_pc_t; 214 215/** 216 * cvmx_pow_ecc_err 217 * 218 * Contains the single and double error bits and the corresponding interrupt enables for the ECC- 219 * protected POW index memory. Also contains the syndrome value in the event of an ECC error. 220 * Also contains the remote pointer error bit and interrupt enable. RPE is set when the POW 221 * detected 222 * corruption on one or more of the input queue lists in L2/DRAM (POW's local copy of the tail 223 * pointer 224 * for the L2/DRAM input queue did not match the last entry on the the list). This is caused by 225 * L2/DRAM corruption, and is generally a fatal error because it likely caused POW to load bad 226 * work 227 * queue entries. 228 * This register also contains the illegal operation error bits and the corresponding interrupt 229 * enables as follows: 230 * <0> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state 231 * <1> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state 232 * <2> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED 233 * or ATOMIC 234 * <3> Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL 235 * <4> Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL 236 * <5> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with 237 * GET_WORK pending 238 * <6> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD 239 * pending 240 * <7> Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending 241 * <8> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with 242 * CLR_NSCHED pending 243 * <9> Received illegal opcode 244 * <10> Received ADD_WORK with tag specified as NULL_NULL 245 * <11> Received DBG load from PP with DBG load pending 246 * <12> Received CSR load from PP with CSR load pending 247 */ 248union cvmx_pow_ecc_err { 249 u64 u64; 250 struct cvmx_pow_ecc_err_s { 251 u64 reserved_45_63 : 19; 252 u64 iop_ie : 13; 253 u64 reserved_29_31 : 3; 254 u64 iop : 13; 255 u64 reserved_14_15 : 2; 256 u64 rpe_ie : 1; 257 u64 rpe : 1; 258 u64 reserved_9_11 : 3; 259 u64 syn : 5; 260 u64 dbe_ie : 1; 261 u64 sbe_ie : 1; 262 u64 dbe : 1; 263 u64 sbe : 1; 264 } s; 265 struct cvmx_pow_ecc_err_s cn30xx; 266 struct cvmx_pow_ecc_err_cn31xx { 267 u64 reserved_14_63 : 50; 268 u64 rpe_ie : 1; 269 u64 rpe : 1; 270 u64 reserved_9_11 : 3; 271 u64 syn : 5; 272 u64 dbe_ie : 1; 273 u64 sbe_ie : 1; 274 u64 dbe : 1; 275 u64 sbe : 1; 276 } cn31xx; 277 struct cvmx_pow_ecc_err_s cn38xx; 278 struct cvmx_pow_ecc_err_cn31xx cn38xxp2; 279 struct cvmx_pow_ecc_err_s cn50xx; 280 struct cvmx_pow_ecc_err_s cn52xx; 281 struct cvmx_pow_ecc_err_s cn52xxp1; 282 struct cvmx_pow_ecc_err_s cn56xx; 283 struct cvmx_pow_ecc_err_s cn56xxp1; 284 struct cvmx_pow_ecc_err_s cn58xx; 285 struct cvmx_pow_ecc_err_s cn58xxp1; 286 struct cvmx_pow_ecc_err_s cn61xx; 287 struct cvmx_pow_ecc_err_s cn63xx; 288 struct cvmx_pow_ecc_err_s cn63xxp1; 289 struct cvmx_pow_ecc_err_s cn66xx; 290 struct cvmx_pow_ecc_err_s cn70xx; 291 struct cvmx_pow_ecc_err_s cn70xxp1; 292 struct cvmx_pow_ecc_err_s cnf71xx; 293}; 294 295typedef union cvmx_pow_ecc_err cvmx_pow_ecc_err_t; 296 297/** 298 * cvmx_pow_iq_cnt# 299 * 300 * Contains a read-only count of the number of work queue entries for each QOS level. 301 * 302 */ 303union cvmx_pow_iq_cntx { 304 u64 u64; 305 struct cvmx_pow_iq_cntx_s { 306 u64 reserved_32_63 : 32; 307 u64 iq_cnt : 32; 308 } s; 309 struct cvmx_pow_iq_cntx_s cn30xx; 310 struct cvmx_pow_iq_cntx_s cn31xx; 311 struct cvmx_pow_iq_cntx_s cn38xx; 312 struct cvmx_pow_iq_cntx_s cn38xxp2; 313 struct cvmx_pow_iq_cntx_s cn50xx; 314 struct cvmx_pow_iq_cntx_s cn52xx; 315 struct cvmx_pow_iq_cntx_s cn52xxp1; 316 struct cvmx_pow_iq_cntx_s cn56xx; 317 struct cvmx_pow_iq_cntx_s cn56xxp1; 318 struct cvmx_pow_iq_cntx_s cn58xx; 319 struct cvmx_pow_iq_cntx_s cn58xxp1; 320 struct cvmx_pow_iq_cntx_s cn61xx; 321 struct cvmx_pow_iq_cntx_s cn63xx; 322 struct cvmx_pow_iq_cntx_s cn63xxp1; 323 struct cvmx_pow_iq_cntx_s cn66xx; 324 struct cvmx_pow_iq_cntx_s cn70xx; 325 struct cvmx_pow_iq_cntx_s cn70xxp1; 326 struct cvmx_pow_iq_cntx_s cnf71xx; 327}; 328 329typedef union cvmx_pow_iq_cntx cvmx_pow_iq_cntx_t; 330 331/** 332 * cvmx_pow_iq_com_cnt 333 * 334 * Contains a read-only count of the total number of work queue entries in all QOS levels. 335 * 336 */ 337union cvmx_pow_iq_com_cnt { 338 u64 u64; 339 struct cvmx_pow_iq_com_cnt_s { 340 u64 reserved_32_63 : 32; 341 u64 iq_cnt : 32; 342 } s; 343 struct cvmx_pow_iq_com_cnt_s cn30xx; 344 struct cvmx_pow_iq_com_cnt_s cn31xx; 345 struct cvmx_pow_iq_com_cnt_s cn38xx; 346 struct cvmx_pow_iq_com_cnt_s cn38xxp2; 347 struct cvmx_pow_iq_com_cnt_s cn50xx; 348 struct cvmx_pow_iq_com_cnt_s cn52xx; 349 struct cvmx_pow_iq_com_cnt_s cn52xxp1; 350 struct cvmx_pow_iq_com_cnt_s cn56xx; 351 struct cvmx_pow_iq_com_cnt_s cn56xxp1; 352 struct cvmx_pow_iq_com_cnt_s cn58xx; 353 struct cvmx_pow_iq_com_cnt_s cn58xxp1; 354 struct cvmx_pow_iq_com_cnt_s cn61xx; 355 struct cvmx_pow_iq_com_cnt_s cn63xx; 356 struct cvmx_pow_iq_com_cnt_s cn63xxp1; 357 struct cvmx_pow_iq_com_cnt_s cn66xx; 358 struct cvmx_pow_iq_com_cnt_s cn70xx; 359 struct cvmx_pow_iq_com_cnt_s cn70xxp1; 360 struct cvmx_pow_iq_com_cnt_s cnf71xx; 361}; 362 363typedef union cvmx_pow_iq_com_cnt cvmx_pow_iq_com_cnt_t; 364 365/** 366 * cvmx_pow_iq_int 367 * 368 * "Contains the bits (1 per QOS level) that can trigger the input queue interrupt. An IQ_INT 369 * bit 370 * will be set if POW_IQ_CNT#QOS# changes and the resulting value is equal to POW_IQ_THR#QOS#." 371 */ 372union cvmx_pow_iq_int { 373 u64 u64; 374 struct cvmx_pow_iq_int_s { 375 u64 reserved_8_63 : 56; 376 u64 iq_int : 8; 377 } s; 378 struct cvmx_pow_iq_int_s cn52xx; 379 struct cvmx_pow_iq_int_s cn52xxp1; 380 struct cvmx_pow_iq_int_s cn56xx; 381 struct cvmx_pow_iq_int_s cn56xxp1; 382 struct cvmx_pow_iq_int_s cn61xx; 383 struct cvmx_pow_iq_int_s cn63xx; 384 struct cvmx_pow_iq_int_s cn63xxp1; 385 struct cvmx_pow_iq_int_s cn66xx; 386 struct cvmx_pow_iq_int_s cn70xx; 387 struct cvmx_pow_iq_int_s cn70xxp1; 388 struct cvmx_pow_iq_int_s cnf71xx; 389}; 390 391typedef union cvmx_pow_iq_int cvmx_pow_iq_int_t; 392 393/** 394 * cvmx_pow_iq_int_en 395 * 396 * Contains the bits (1 per QOS level) that enable the input queue interrupt. 397 * 398 */ 399union cvmx_pow_iq_int_en { 400 u64 u64; 401 struct cvmx_pow_iq_int_en_s { 402 u64 reserved_8_63 : 56; 403 u64 int_en : 8; 404 } s; 405 struct cvmx_pow_iq_int_en_s cn52xx; 406 struct cvmx_pow_iq_int_en_s cn52xxp1; 407 struct cvmx_pow_iq_int_en_s cn56xx; 408 struct cvmx_pow_iq_int_en_s cn56xxp1; 409 struct cvmx_pow_iq_int_en_s cn61xx; 410 struct cvmx_pow_iq_int_en_s cn63xx; 411 struct cvmx_pow_iq_int_en_s cn63xxp1; 412 struct cvmx_pow_iq_int_en_s cn66xx; 413 struct cvmx_pow_iq_int_en_s cn70xx; 414 struct cvmx_pow_iq_int_en_s cn70xxp1; 415 struct cvmx_pow_iq_int_en_s cnf71xx; 416}; 417 418typedef union cvmx_pow_iq_int_en cvmx_pow_iq_int_en_t; 419 420/** 421 * cvmx_pow_iq_thr# 422 * 423 * Threshold value for triggering input queue interrupts. 424 * 425 */ 426union cvmx_pow_iq_thrx { 427 u64 u64; 428 struct cvmx_pow_iq_thrx_s { 429 u64 reserved_32_63 : 32; 430 u64 iq_thr : 32; 431 } s; 432 struct cvmx_pow_iq_thrx_s cn52xx; 433 struct cvmx_pow_iq_thrx_s cn52xxp1; 434 struct cvmx_pow_iq_thrx_s cn56xx; 435 struct cvmx_pow_iq_thrx_s cn56xxp1; 436 struct cvmx_pow_iq_thrx_s cn61xx; 437 struct cvmx_pow_iq_thrx_s cn63xx; 438 struct cvmx_pow_iq_thrx_s cn63xxp1; 439 struct cvmx_pow_iq_thrx_s cn66xx; 440 struct cvmx_pow_iq_thrx_s cn70xx; 441 struct cvmx_pow_iq_thrx_s cn70xxp1; 442 struct cvmx_pow_iq_thrx_s cnf71xx; 443}; 444 445typedef union cvmx_pow_iq_thrx cvmx_pow_iq_thrx_t; 446 447/** 448 * cvmx_pow_nos_cnt 449 * 450 * Contains the number of work queue entries on the no-schedule list. 451 * 452 */ 453union cvmx_pow_nos_cnt { 454 u64 u64; 455 struct cvmx_pow_nos_cnt_s { 456 u64 reserved_12_63 : 52; 457 u64 nos_cnt : 12; 458 } s; 459 struct cvmx_pow_nos_cnt_cn30xx { 460 u64 reserved_7_63 : 57; 461 u64 nos_cnt : 7; 462 } cn30xx; 463 struct cvmx_pow_nos_cnt_cn31xx { 464 u64 reserved_9_63 : 55; 465 u64 nos_cnt : 9; 466 } cn31xx; 467 struct cvmx_pow_nos_cnt_s cn38xx; 468 struct cvmx_pow_nos_cnt_s cn38xxp2; 469 struct cvmx_pow_nos_cnt_cn31xx cn50xx; 470 struct cvmx_pow_nos_cnt_cn52xx { 471 u64 reserved_10_63 : 54; 472 u64 nos_cnt : 10; 473 } cn52xx; 474 struct cvmx_pow_nos_cnt_cn52xx cn52xxp1; 475 struct cvmx_pow_nos_cnt_s cn56xx; 476 struct cvmx_pow_nos_cnt_s cn56xxp1; 477 struct cvmx_pow_nos_cnt_s cn58xx; 478 struct cvmx_pow_nos_cnt_s cn58xxp1; 479 struct cvmx_pow_nos_cnt_cn52xx cn61xx; 480 struct cvmx_pow_nos_cnt_cn63xx { 481 u64 reserved_11_63 : 53; 482 u64 nos_cnt : 11; 483 } cn63xx; 484 struct cvmx_pow_nos_cnt_cn63xx cn63xxp1; 485 struct cvmx_pow_nos_cnt_cn63xx cn66xx; 486 struct cvmx_pow_nos_cnt_cn52xx cn70xx; 487 struct cvmx_pow_nos_cnt_cn52xx cn70xxp1; 488 struct cvmx_pow_nos_cnt_cn52xx cnf71xx; 489}; 490 491typedef union cvmx_pow_nos_cnt cvmx_pow_nos_cnt_t; 492 493/** 494 * cvmx_pow_nw_tim 495 * 496 * Sets the minimum period for a new work request timeout. Period is specified in n-1 notation 497 * where the increment value is 1024 clock cycles. Thus, a value of 0x0 in this register 498 * translates 499 * to 1024 cycles, 0x1 translates to 2048 cycles, 0x2 translates to 3072 cycles, etc... Note: 500 * the 501 * maximum period for a new work request timeout is 2 times the minimum period. Note: the new 502 * work 503 * request timeout counter is reset when this register is written. 504 * There are two new work request timeout cases: 505 * - WAIT bit clear. The new work request can timeout if the timer expires before the pre-fetch 506 * engine has reached the end of all work queues. This can occur if the executable work queue 507 * entry is deep in the queue and the pre-fetch engine is subject to many resets (i.e. high 508 * switch, 509 * de-schedule, or new work load from other PP's). Thus, it is possible for a PP to receive a 510 * work 511 * response with the NO_WORK bit set even though there was at least one executable entry in the 512 * work queues. The other (and typical) scenario for receiving a NO_WORK response with the 513 * WAIT 514 * bit clear is that the pre-fetch engine has reached the end of all work queues without 515 * finding 516 * executable work. 517 * - WAIT bit set. The new work request can timeout if the timer expires before the pre-fetch 518 * engine has found executable work. In this case, the only scenario where the PP will receive 519 * a 520 * work response with the NO_WORK bit set is if the timer expires. Note: it is still possible 521 * for 522 * a PP to receive a NO_WORK response even though there was at least one executable entry in 523 * the 524 * work queues. 525 * In either case, it's important to note that switches and de-schedules are higher priority 526 * operations that can cause the pre-fetch engine to reset. Thus in a system with many switches 527 * or 528 * de-schedules occurring, it's possible for the new work timer to expire (resulting in NO_WORK 529 * responses) before the pre-fetch engine is able to get very deep into the work queues. 530 */ 531union cvmx_pow_nw_tim { 532 u64 u64; 533 struct cvmx_pow_nw_tim_s { 534 u64 reserved_10_63 : 54; 535 u64 nw_tim : 10; 536 } s; 537 struct cvmx_pow_nw_tim_s cn30xx; 538 struct cvmx_pow_nw_tim_s cn31xx; 539 struct cvmx_pow_nw_tim_s cn38xx; 540 struct cvmx_pow_nw_tim_s cn38xxp2; 541 struct cvmx_pow_nw_tim_s cn50xx; 542 struct cvmx_pow_nw_tim_s cn52xx; 543 struct cvmx_pow_nw_tim_s cn52xxp1; 544 struct cvmx_pow_nw_tim_s cn56xx; 545 struct cvmx_pow_nw_tim_s cn56xxp1; 546 struct cvmx_pow_nw_tim_s cn58xx; 547 struct cvmx_pow_nw_tim_s cn58xxp1; 548 struct cvmx_pow_nw_tim_s cn61xx; 549 struct cvmx_pow_nw_tim_s cn63xx; 550 struct cvmx_pow_nw_tim_s cn63xxp1; 551 struct cvmx_pow_nw_tim_s cn66xx; 552 struct cvmx_pow_nw_tim_s cn70xx; 553 struct cvmx_pow_nw_tim_s cn70xxp1; 554 struct cvmx_pow_nw_tim_s cnf71xx; 555}; 556 557typedef union cvmx_pow_nw_tim cvmx_pow_nw_tim_t; 558 559/** 560 * cvmx_pow_pf_rst_msk 561 * 562 * Resets the work prefetch engine when work is stored in an internal buffer (either when the add 563 * work arrives or when the work is reloaded from an external buffer) for an enabled QOS level 564 * (1 bit per QOS level). 565 */ 566union cvmx_pow_pf_rst_msk { 567 u64 u64; 568 struct cvmx_pow_pf_rst_msk_s { 569 u64 reserved_8_63 : 56; 570 u64 rst_msk : 8; 571 } s; 572 struct cvmx_pow_pf_rst_msk_s cn50xx; 573 struct cvmx_pow_pf_rst_msk_s cn52xx; 574 struct cvmx_pow_pf_rst_msk_s cn52xxp1; 575 struct cvmx_pow_pf_rst_msk_s cn56xx; 576 struct cvmx_pow_pf_rst_msk_s cn56xxp1; 577 struct cvmx_pow_pf_rst_msk_s cn58xx; 578 struct cvmx_pow_pf_rst_msk_s cn58xxp1; 579 struct cvmx_pow_pf_rst_msk_s cn61xx; 580 struct cvmx_pow_pf_rst_msk_s cn63xx; 581 struct cvmx_pow_pf_rst_msk_s cn63xxp1; 582 struct cvmx_pow_pf_rst_msk_s cn66xx; 583 struct cvmx_pow_pf_rst_msk_s cn70xx; 584 struct cvmx_pow_pf_rst_msk_s cn70xxp1; 585 struct cvmx_pow_pf_rst_msk_s cnf71xx; 586}; 587 588typedef union cvmx_pow_pf_rst_msk cvmx_pow_pf_rst_msk_t; 589 590/** 591 * cvmx_pow_pp_grp_msk# 592 * 593 * Selects which group(s) a PP belongs to. A '1' in any bit position sets the PP's membership in 594 * the corresponding group. A value of 0x0 will prevent the PP from receiving new work. Note: 595 * disabled or non-existent PP's should have this field set to 0xffff (the reset value) in order 596 * to 597 * maximize POW performance. 598 * Also contains the QOS level priorities for each PP. 0x0 is highest priority, and 0x7 the 599 * lowest. 600 * Setting the priority to 0xf will prevent that PP from receiving work from that QOS level. 601 * Priority values 0x8 through 0xe are reserved and should not be used. For a given PP, 602 * priorities 603 * should begin at 0x0 and remain contiguous throughout the range. 604 */ 605union cvmx_pow_pp_grp_mskx { 606 u64 u64; 607 struct cvmx_pow_pp_grp_mskx_s { 608 u64 reserved_48_63 : 16; 609 u64 qos7_pri : 4; 610 u64 qos6_pri : 4; 611 u64 qos5_pri : 4; 612 u64 qos4_pri : 4; 613 u64 qos3_pri : 4; 614 u64 qos2_pri : 4; 615 u64 qos1_pri : 4; 616 u64 qos0_pri : 4; 617 u64 grp_msk : 16; 618 } s; 619 struct cvmx_pow_pp_grp_mskx_cn30xx { 620 u64 reserved_16_63 : 48; 621 u64 grp_msk : 16; 622 } cn30xx; 623 struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx; 624 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx; 625 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2; 626 struct cvmx_pow_pp_grp_mskx_s cn50xx; 627 struct cvmx_pow_pp_grp_mskx_s cn52xx; 628 struct cvmx_pow_pp_grp_mskx_s cn52xxp1; 629 struct cvmx_pow_pp_grp_mskx_s cn56xx; 630 struct cvmx_pow_pp_grp_mskx_s cn56xxp1; 631 struct cvmx_pow_pp_grp_mskx_s cn58xx; 632 struct cvmx_pow_pp_grp_mskx_s cn58xxp1; 633 struct cvmx_pow_pp_grp_mskx_s cn61xx; 634 struct cvmx_pow_pp_grp_mskx_s cn63xx; 635 struct cvmx_pow_pp_grp_mskx_s cn63xxp1; 636 struct cvmx_pow_pp_grp_mskx_s cn66xx; 637 struct cvmx_pow_pp_grp_mskx_s cn70xx; 638 struct cvmx_pow_pp_grp_mskx_s cn70xxp1; 639 struct cvmx_pow_pp_grp_mskx_s cnf71xx; 640}; 641 642typedef union cvmx_pow_pp_grp_mskx cvmx_pow_pp_grp_mskx_t; 643 644/** 645 * cvmx_pow_qos_rnd# 646 * 647 * Contains the round definitions for issuing new work. Each round consists of 8 bits with each 648 * bit 649 * corresponding to a QOS level. There are 4 rounds contained in each register for a total of 32 650 * rounds. The issue logic traverses through the rounds sequentially (lowest round to highest 651 * round) 652 * in an attempt to find new work for each PP. Within each round, the issue logic traverses 653 * through 654 * the QOS levels sequentially (highest QOS to lowest QOS) skipping over each QOS level with a 655 * clear 656 * bit in the round mask. Note: setting a QOS level to all zeroes in all issue round registers 657 * will 658 * prevent work from being issued from that QOS level. 659 */ 660union cvmx_pow_qos_rndx { 661 u64 u64; 662 struct cvmx_pow_qos_rndx_s { 663 u64 reserved_32_63 : 32; 664 u64 rnd_p3 : 8; 665 u64 rnd_p2 : 8; 666 u64 rnd_p1 : 8; 667 u64 rnd : 8; 668 } s; 669 struct cvmx_pow_qos_rndx_s cn30xx; 670 struct cvmx_pow_qos_rndx_s cn31xx; 671 struct cvmx_pow_qos_rndx_s cn38xx; 672 struct cvmx_pow_qos_rndx_s cn38xxp2; 673 struct cvmx_pow_qos_rndx_s cn50xx; 674 struct cvmx_pow_qos_rndx_s cn52xx; 675 struct cvmx_pow_qos_rndx_s cn52xxp1; 676 struct cvmx_pow_qos_rndx_s cn56xx; 677 struct cvmx_pow_qos_rndx_s cn56xxp1; 678 struct cvmx_pow_qos_rndx_s cn58xx; 679 struct cvmx_pow_qos_rndx_s cn58xxp1; 680 struct cvmx_pow_qos_rndx_s cn61xx; 681 struct cvmx_pow_qos_rndx_s cn63xx; 682 struct cvmx_pow_qos_rndx_s cn63xxp1; 683 struct cvmx_pow_qos_rndx_s cn66xx; 684 struct cvmx_pow_qos_rndx_s cn70xx; 685 struct cvmx_pow_qos_rndx_s cn70xxp1; 686 struct cvmx_pow_qos_rndx_s cnf71xx; 687}; 688 689typedef union cvmx_pow_qos_rndx cvmx_pow_qos_rndx_t; 690 691/** 692 * cvmx_pow_qos_thr# 693 * 694 * Contains the thresholds for allocating POW internal storage buffers. If the number of 695 * remaining 696 * free buffers drops below the minimum threshold (MIN_THR) or the number of allocated buffers 697 * for 698 * this QOS level rises above the maximum threshold (MAX_THR), future incoming work queue entries 699 * will be buffered externally rather than internally. This register also contains a read-only 700 * count 701 * of the current number of free buffers (FREE_CNT), the number of internal buffers currently 702 * allocated to this QOS level (BUF_CNT), and the total number of buffers on the de-schedule list 703 * (DES_CNT) (which is not the same as the total number of de-scheduled buffers). 704 */ 705union cvmx_pow_qos_thrx { 706 u64 u64; 707 struct cvmx_pow_qos_thrx_s { 708 u64 reserved_60_63 : 4; 709 u64 des_cnt : 12; 710 u64 buf_cnt : 12; 711 u64 free_cnt : 12; 712 u64 reserved_23_23 : 1; 713 u64 max_thr : 11; 714 u64 reserved_11_11 : 1; 715 u64 min_thr : 11; 716 } s; 717 struct cvmx_pow_qos_thrx_cn30xx { 718 u64 reserved_55_63 : 9; 719 u64 des_cnt : 7; 720 u64 reserved_43_47 : 5; 721 u64 buf_cnt : 7; 722 u64 reserved_31_35 : 5; 723 u64 free_cnt : 7; 724 u64 reserved_18_23 : 6; 725 u64 max_thr : 6; 726 u64 reserved_6_11 : 6; 727 u64 min_thr : 6; 728 } cn30xx; 729 struct cvmx_pow_qos_thrx_cn31xx { 730 u64 reserved_57_63 : 7; 731 u64 des_cnt : 9; 732 u64 reserved_45_47 : 3; 733 u64 buf_cnt : 9; 734 u64 reserved_33_35 : 3; 735 u64 free_cnt : 9; 736 u64 reserved_20_23 : 4; 737 u64 max_thr : 8; 738 u64 reserved_8_11 : 4; 739 u64 min_thr : 8; 740 } cn31xx; 741 struct cvmx_pow_qos_thrx_s cn38xx; 742 struct cvmx_pow_qos_thrx_s cn38xxp2; 743 struct cvmx_pow_qos_thrx_cn31xx cn50xx; 744 struct cvmx_pow_qos_thrx_cn52xx { 745 u64 reserved_58_63 : 6; 746 u64 des_cnt : 10; 747 u64 reserved_46_47 : 2; 748 u64 buf_cnt : 10; 749 u64 reserved_34_35 : 2; 750 u64 free_cnt : 10; 751 u64 reserved_21_23 : 3; 752 u64 max_thr : 9; 753 u64 reserved_9_11 : 3; 754 u64 min_thr : 9; 755 } cn52xx; 756 struct cvmx_pow_qos_thrx_cn52xx cn52xxp1; 757 struct cvmx_pow_qos_thrx_s cn56xx; 758 struct cvmx_pow_qos_thrx_s cn56xxp1; 759 struct cvmx_pow_qos_thrx_s cn58xx; 760 struct cvmx_pow_qos_thrx_s cn58xxp1; 761 struct cvmx_pow_qos_thrx_cn52xx cn61xx; 762 struct cvmx_pow_qos_thrx_cn63xx { 763 u64 reserved_59_63 : 5; 764 u64 des_cnt : 11; 765 u64 reserved_47_47 : 1; 766 u64 buf_cnt : 11; 767 u64 reserved_35_35 : 1; 768 u64 free_cnt : 11; 769 u64 reserved_22_23 : 2; 770 u64 max_thr : 10; 771 u64 reserved_10_11 : 2; 772 u64 min_thr : 10; 773 } cn63xx; 774 struct cvmx_pow_qos_thrx_cn63xx cn63xxp1; 775 struct cvmx_pow_qos_thrx_cn63xx cn66xx; 776 struct cvmx_pow_qos_thrx_cn52xx cn70xx; 777 struct cvmx_pow_qos_thrx_cn52xx cn70xxp1; 778 struct cvmx_pow_qos_thrx_cn52xx cnf71xx; 779}; 780 781typedef union cvmx_pow_qos_thrx cvmx_pow_qos_thrx_t; 782 783/** 784 * cvmx_pow_ts_pc 785 * 786 * Counts the number of tag switch requests. Write to clear. 787 * 788 */ 789union cvmx_pow_ts_pc { 790 u64 u64; 791 struct cvmx_pow_ts_pc_s { 792 u64 reserved_32_63 : 32; 793 u64 ts_pc : 32; 794 } s; 795 struct cvmx_pow_ts_pc_s cn30xx; 796 struct cvmx_pow_ts_pc_s cn31xx; 797 struct cvmx_pow_ts_pc_s cn38xx; 798 struct cvmx_pow_ts_pc_s cn38xxp2; 799 struct cvmx_pow_ts_pc_s cn50xx; 800 struct cvmx_pow_ts_pc_s cn52xx; 801 struct cvmx_pow_ts_pc_s cn52xxp1; 802 struct cvmx_pow_ts_pc_s cn56xx; 803 struct cvmx_pow_ts_pc_s cn56xxp1; 804 struct cvmx_pow_ts_pc_s cn58xx; 805 struct cvmx_pow_ts_pc_s cn58xxp1; 806 struct cvmx_pow_ts_pc_s cn61xx; 807 struct cvmx_pow_ts_pc_s cn63xx; 808 struct cvmx_pow_ts_pc_s cn63xxp1; 809 struct cvmx_pow_ts_pc_s cn66xx; 810 struct cvmx_pow_ts_pc_s cn70xx; 811 struct cvmx_pow_ts_pc_s cn70xxp1; 812 struct cvmx_pow_ts_pc_s cnf71xx; 813}; 814 815typedef union cvmx_pow_ts_pc cvmx_pow_ts_pc_t; 816 817/** 818 * cvmx_pow_wa_com_pc 819 * 820 * Counts the number of add new work requests for all QOS levels. Write to clear. 821 * 822 */ 823union cvmx_pow_wa_com_pc { 824 u64 u64; 825 struct cvmx_pow_wa_com_pc_s { 826 u64 reserved_32_63 : 32; 827 u64 wa_pc : 32; 828 } s; 829 struct cvmx_pow_wa_com_pc_s cn30xx; 830 struct cvmx_pow_wa_com_pc_s cn31xx; 831 struct cvmx_pow_wa_com_pc_s cn38xx; 832 struct cvmx_pow_wa_com_pc_s cn38xxp2; 833 struct cvmx_pow_wa_com_pc_s cn50xx; 834 struct cvmx_pow_wa_com_pc_s cn52xx; 835 struct cvmx_pow_wa_com_pc_s cn52xxp1; 836 struct cvmx_pow_wa_com_pc_s cn56xx; 837 struct cvmx_pow_wa_com_pc_s cn56xxp1; 838 struct cvmx_pow_wa_com_pc_s cn58xx; 839 struct cvmx_pow_wa_com_pc_s cn58xxp1; 840 struct cvmx_pow_wa_com_pc_s cn61xx; 841 struct cvmx_pow_wa_com_pc_s cn63xx; 842 struct cvmx_pow_wa_com_pc_s cn63xxp1; 843 struct cvmx_pow_wa_com_pc_s cn66xx; 844 struct cvmx_pow_wa_com_pc_s cn70xx; 845 struct cvmx_pow_wa_com_pc_s cn70xxp1; 846 struct cvmx_pow_wa_com_pc_s cnf71xx; 847}; 848 849typedef union cvmx_pow_wa_com_pc cvmx_pow_wa_com_pc_t; 850 851/** 852 * cvmx_pow_wa_pc# 853 * 854 * Counts the number of add new work requests for each QOS level. Write to clear. 855 * 856 */ 857union cvmx_pow_wa_pcx { 858 u64 u64; 859 struct cvmx_pow_wa_pcx_s { 860 u64 reserved_32_63 : 32; 861 u64 wa_pc : 32; 862 } s; 863 struct cvmx_pow_wa_pcx_s cn30xx; 864 struct cvmx_pow_wa_pcx_s cn31xx; 865 struct cvmx_pow_wa_pcx_s cn38xx; 866 struct cvmx_pow_wa_pcx_s cn38xxp2; 867 struct cvmx_pow_wa_pcx_s cn50xx; 868 struct cvmx_pow_wa_pcx_s cn52xx; 869 struct cvmx_pow_wa_pcx_s cn52xxp1; 870 struct cvmx_pow_wa_pcx_s cn56xx; 871 struct cvmx_pow_wa_pcx_s cn56xxp1; 872 struct cvmx_pow_wa_pcx_s cn58xx; 873 struct cvmx_pow_wa_pcx_s cn58xxp1; 874 struct cvmx_pow_wa_pcx_s cn61xx; 875 struct cvmx_pow_wa_pcx_s cn63xx; 876 struct cvmx_pow_wa_pcx_s cn63xxp1; 877 struct cvmx_pow_wa_pcx_s cn66xx; 878 struct cvmx_pow_wa_pcx_s cn70xx; 879 struct cvmx_pow_wa_pcx_s cn70xxp1; 880 struct cvmx_pow_wa_pcx_s cnf71xx; 881}; 882 883typedef union cvmx_pow_wa_pcx cvmx_pow_wa_pcx_t; 884 885/** 886 * cvmx_pow_wq_int 887 * 888 * Contains the bits (1 per group) that set work queue interrupts and are used to clear these 889 * interrupts. Also contains the input queue interrupt temporary disable bits (1 per group). For 890 * more information regarding this register, see the interrupt section. 891 */ 892union cvmx_pow_wq_int { 893 u64 u64; 894 struct cvmx_pow_wq_int_s { 895 u64 reserved_32_63 : 32; 896 u64 iq_dis : 16; 897 u64 wq_int : 16; 898 } s; 899 struct cvmx_pow_wq_int_s cn30xx; 900 struct cvmx_pow_wq_int_s cn31xx; 901 struct cvmx_pow_wq_int_s cn38xx; 902 struct cvmx_pow_wq_int_s cn38xxp2; 903 struct cvmx_pow_wq_int_s cn50xx; 904 struct cvmx_pow_wq_int_s cn52xx; 905 struct cvmx_pow_wq_int_s cn52xxp1; 906 struct cvmx_pow_wq_int_s cn56xx; 907 struct cvmx_pow_wq_int_s cn56xxp1; 908 struct cvmx_pow_wq_int_s cn58xx; 909 struct cvmx_pow_wq_int_s cn58xxp1; 910 struct cvmx_pow_wq_int_s cn61xx; 911 struct cvmx_pow_wq_int_s cn63xx; 912 struct cvmx_pow_wq_int_s cn63xxp1; 913 struct cvmx_pow_wq_int_s cn66xx; 914 struct cvmx_pow_wq_int_s cn70xx; 915 struct cvmx_pow_wq_int_s cn70xxp1; 916 struct cvmx_pow_wq_int_s cnf71xx; 917}; 918 919typedef union cvmx_pow_wq_int cvmx_pow_wq_int_t; 920 921/** 922 * cvmx_pow_wq_int_cnt# 923 * 924 * Contains a read-only copy of the counts used to trigger work queue interrupts. For more 925 * information regarding this register, see the interrupt section. 926 */ 927union cvmx_pow_wq_int_cntx { 928 u64 u64; 929 struct cvmx_pow_wq_int_cntx_s { 930 u64 reserved_28_63 : 36; 931 u64 tc_cnt : 4; 932 u64 ds_cnt : 12; 933 u64 iq_cnt : 12; 934 } s; 935 struct cvmx_pow_wq_int_cntx_cn30xx { 936 u64 reserved_28_63 : 36; 937 u64 tc_cnt : 4; 938 u64 reserved_19_23 : 5; 939 u64 ds_cnt : 7; 940 u64 reserved_7_11 : 5; 941 u64 iq_cnt : 7; 942 } cn30xx; 943 struct cvmx_pow_wq_int_cntx_cn31xx { 944 u64 reserved_28_63 : 36; 945 u64 tc_cnt : 4; 946 u64 reserved_21_23 : 3; 947 u64 ds_cnt : 9; 948 u64 reserved_9_11 : 3; 949 u64 iq_cnt : 9; 950 } cn31xx; 951 struct cvmx_pow_wq_int_cntx_s cn38xx; 952 struct cvmx_pow_wq_int_cntx_s cn38xxp2; 953 struct cvmx_pow_wq_int_cntx_cn31xx cn50xx; 954 struct cvmx_pow_wq_int_cntx_cn52xx { 955 u64 reserved_28_63 : 36; 956 u64 tc_cnt : 4; 957 u64 reserved_22_23 : 2; 958 u64 ds_cnt : 10; 959 u64 reserved_10_11 : 2; 960 u64 iq_cnt : 10; 961 } cn52xx; 962 struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1; 963 struct cvmx_pow_wq_int_cntx_s cn56xx; 964 struct cvmx_pow_wq_int_cntx_s cn56xxp1; 965 struct cvmx_pow_wq_int_cntx_s cn58xx; 966 struct cvmx_pow_wq_int_cntx_s cn58xxp1; 967 struct cvmx_pow_wq_int_cntx_cn52xx cn61xx; 968 struct cvmx_pow_wq_int_cntx_cn63xx { 969 u64 reserved_28_63 : 36; 970 u64 tc_cnt : 4; 971 u64 reserved_23_23 : 1; 972 u64 ds_cnt : 11; 973 u64 reserved_11_11 : 1; 974 u64 iq_cnt : 11; 975 } cn63xx; 976 struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1; 977 struct cvmx_pow_wq_int_cntx_cn63xx cn66xx; 978 struct cvmx_pow_wq_int_cntx_cn52xx cn70xx; 979 struct cvmx_pow_wq_int_cntx_cn52xx cn70xxp1; 980 struct cvmx_pow_wq_int_cntx_cn52xx cnf71xx; 981}; 982 983typedef union cvmx_pow_wq_int_cntx cvmx_pow_wq_int_cntx_t; 984 985/** 986 * cvmx_pow_wq_int_pc 987 * 988 * Contains the threshold value for the work queue interrupt periodic counter and also a read- 989 * only 990 * copy of the periodic counter. For more information regarding this register, see the interrupt 991 * section. 992 */ 993union cvmx_pow_wq_int_pc { 994 u64 u64; 995 struct cvmx_pow_wq_int_pc_s { 996 u64 reserved_60_63 : 4; 997 u64 pc : 28; 998 u64 reserved_28_31 : 4; 999 u64 pc_thr : 20; 1000 u64 reserved_0_7 : 8; 1001 } s; 1002 struct cvmx_pow_wq_int_pc_s cn30xx; 1003 struct cvmx_pow_wq_int_pc_s cn31xx; 1004 struct cvmx_pow_wq_int_pc_s cn38xx; 1005 struct cvmx_pow_wq_int_pc_s cn38xxp2; 1006 struct cvmx_pow_wq_int_pc_s cn50xx; 1007 struct cvmx_pow_wq_int_pc_s cn52xx; 1008 struct cvmx_pow_wq_int_pc_s cn52xxp1; 1009 struct cvmx_pow_wq_int_pc_s cn56xx; 1010 struct cvmx_pow_wq_int_pc_s cn56xxp1; 1011 struct cvmx_pow_wq_int_pc_s cn58xx; 1012 struct cvmx_pow_wq_int_pc_s cn58xxp1; 1013 struct cvmx_pow_wq_int_pc_s cn61xx; 1014 struct cvmx_pow_wq_int_pc_s cn63xx; 1015 struct cvmx_pow_wq_int_pc_s cn63xxp1; 1016 struct cvmx_pow_wq_int_pc_s cn66xx; 1017 struct cvmx_pow_wq_int_pc_s cn70xx; 1018 struct cvmx_pow_wq_int_pc_s cn70xxp1; 1019 struct cvmx_pow_wq_int_pc_s cnf71xx; 1020}; 1021 1022typedef union cvmx_pow_wq_int_pc cvmx_pow_wq_int_pc_t; 1023 1024/** 1025 * cvmx_pow_wq_int_thr# 1026 * 1027 * Contains the thresholds for enabling and setting work queue interrupts. For more information 1028 * regarding this register, see the interrupt section. 1029 * Note: Up to 4 of the POW's internal storage buffers can be allocated for hardware use and are 1030 * therefore not available for incoming work queue entries. Additionally, any PP that is not in 1031 * the 1032 * NULL_NULL state consumes a buffer. Thus in a 4 PP system, it is not advisable to set either 1033 * IQ_THR or DS_THR to greater than 512 - 4 - 4 = 504. Doing so may prevent the interrupt from 1034 * ever triggering. 1035 */ 1036union cvmx_pow_wq_int_thrx { 1037 u64 u64; 1038 struct cvmx_pow_wq_int_thrx_s { 1039 u64 reserved_29_63 : 35; 1040 u64 tc_en : 1; 1041 u64 tc_thr : 4; 1042 u64 reserved_23_23 : 1; 1043 u64 ds_thr : 11; 1044 u64 reserved_11_11 : 1; 1045 u64 iq_thr : 11; 1046 } s; 1047 struct cvmx_pow_wq_int_thrx_cn30xx { 1048 u64 reserved_29_63 : 35; 1049 u64 tc_en : 1; 1050 u64 tc_thr : 4; 1051 u64 reserved_18_23 : 6; 1052 u64 ds_thr : 6; 1053 u64 reserved_6_11 : 6; 1054 u64 iq_thr : 6; 1055 } cn30xx; 1056 struct cvmx_pow_wq_int_thrx_cn31xx { 1057 u64 reserved_29_63 : 35; 1058 u64 tc_en : 1; 1059 u64 tc_thr : 4; 1060 u64 reserved_20_23 : 4; 1061 u64 ds_thr : 8; 1062 u64 reserved_8_11 : 4; 1063 u64 iq_thr : 8; 1064 } cn31xx; 1065 struct cvmx_pow_wq_int_thrx_s cn38xx; 1066 struct cvmx_pow_wq_int_thrx_s cn38xxp2; 1067 struct cvmx_pow_wq_int_thrx_cn31xx cn50xx; 1068 struct cvmx_pow_wq_int_thrx_cn52xx { 1069 u64 reserved_29_63 : 35; 1070 u64 tc_en : 1; 1071 u64 tc_thr : 4; 1072 u64 reserved_21_23 : 3; 1073 u64 ds_thr : 9; 1074 u64 reserved_9_11 : 3; 1075 u64 iq_thr : 9; 1076 } cn52xx; 1077 struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1; 1078 struct cvmx_pow_wq_int_thrx_s cn56xx; 1079 struct cvmx_pow_wq_int_thrx_s cn56xxp1; 1080 struct cvmx_pow_wq_int_thrx_s cn58xx; 1081 struct cvmx_pow_wq_int_thrx_s cn58xxp1; 1082 struct cvmx_pow_wq_int_thrx_cn52xx cn61xx; 1083 struct cvmx_pow_wq_int_thrx_cn63xx { 1084 u64 reserved_29_63 : 35; 1085 u64 tc_en : 1; 1086 u64 tc_thr : 4; 1087 u64 reserved_22_23 : 2; 1088 u64 ds_thr : 10; 1089 u64 reserved_10_11 : 2; 1090 u64 iq_thr : 10; 1091 } cn63xx; 1092 struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1; 1093 struct cvmx_pow_wq_int_thrx_cn63xx cn66xx; 1094 struct cvmx_pow_wq_int_thrx_cn52xx cn70xx; 1095 struct cvmx_pow_wq_int_thrx_cn52xx cn70xxp1; 1096 struct cvmx_pow_wq_int_thrx_cn52xx cnf71xx; 1097}; 1098 1099typedef union cvmx_pow_wq_int_thrx cvmx_pow_wq_int_thrx_t; 1100 1101/** 1102 * cvmx_pow_ws_pc# 1103 * 1104 * Counts the number of work schedules for each group. Write to clear. 1105 * 1106 */ 1107union cvmx_pow_ws_pcx { 1108 u64 u64; 1109 struct cvmx_pow_ws_pcx_s { 1110 u64 reserved_32_63 : 32; 1111 u64 ws_pc : 32; 1112 } s; 1113 struct cvmx_pow_ws_pcx_s cn30xx; 1114 struct cvmx_pow_ws_pcx_s cn31xx; 1115 struct cvmx_pow_ws_pcx_s cn38xx; 1116 struct cvmx_pow_ws_pcx_s cn38xxp2; 1117 struct cvmx_pow_ws_pcx_s cn50xx; 1118 struct cvmx_pow_ws_pcx_s cn52xx; 1119 struct cvmx_pow_ws_pcx_s cn52xxp1; 1120 struct cvmx_pow_ws_pcx_s cn56xx; 1121 struct cvmx_pow_ws_pcx_s cn56xxp1; 1122 struct cvmx_pow_ws_pcx_s cn58xx; 1123 struct cvmx_pow_ws_pcx_s cn58xxp1; 1124 struct cvmx_pow_ws_pcx_s cn61xx; 1125 struct cvmx_pow_ws_pcx_s cn63xx; 1126 struct cvmx_pow_ws_pcx_s cn63xxp1; 1127 struct cvmx_pow_ws_pcx_s cn66xx; 1128 struct cvmx_pow_ws_pcx_s cn70xx; 1129 struct cvmx_pow_ws_pcx_s cn70xxp1; 1130 struct cvmx_pow_ws_pcx_s cnf71xx; 1131}; 1132 1133typedef union cvmx_pow_ws_pcx cvmx_pow_ws_pcx_t; 1134 1135#endif 1136