1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2018-2022 Marvell International Ltd. 4 * 5 * Functions for RGMII (MGMT) initialization, configuration, 6 * and monitoring. 7 */ 8 9#include <log.h> 10#include <time.h> 11#include <linux/delay.h> 12 13#include <mach/cvmx-regs.h> 14#include <mach/cvmx-csr.h> 15#include <mach/cvmx-bootmem.h> 16#include <mach/octeon-model.h> 17#include <mach/cvmx-fuse.h> 18#include <mach/octeon-feature.h> 19#include <mach/cvmx-qlm.h> 20#include <mach/octeon_qlm.h> 21#include <mach/cvmx-pcie.h> 22#include <mach/cvmx-coremask.h> 23 24#include <mach/cvmx-pki.h> 25#include <mach/cvmx-helper.h> 26#include <mach/cvmx-helper-board.h> 27#include <mach/cvmx-helper-cfg.h> 28 29#include <mach/cvmx-agl.h> 30#include <mach/cvmx-agl-defs.h> 31 32/* 33 * @param port to enable 34 * 35 * @return Zero on success, negative on failure 36 */ 37int cvmx_agl_enable(int port) 38{ 39 cvmx_agl_gmx_rxx_frm_ctl_t rxx_frm_ctl; 40 41 rxx_frm_ctl.u64 = 0; 42 rxx_frm_ctl.s.pre_align = 1; 43 /* When set, disables the length check for non-min sized pkts with 44 * padding in the client data 45 */ 46 rxx_frm_ctl.s.pad_len = 1; 47 /* When set, disables the length check for VLAN pkts */ 48 rxx_frm_ctl.s.vlan_len = 1; 49 /* When set, PREAMBLE checking is less strict */ 50 rxx_frm_ctl.s.pre_free = 1; 51 /* Control Pause Frames can match station SMAC */ 52 rxx_frm_ctl.s.ctl_smac = 0; 53 /* Control Pause Frames can match globally assign Multicast address */ 54 rxx_frm_ctl.s.ctl_mcst = 1; 55 rxx_frm_ctl.s.ctl_bck = 1; /* Forward pause information to TX block */ 56 rxx_frm_ctl.s.ctl_drp = 1; /* Drop Control Pause Frames */ 57 rxx_frm_ctl.s.pre_strp = 1; /* Strip off the preamble */ 58 /* This port is configured to send PREAMBLE+SFD to begin every frame. 59 * GMX checks that the PREAMBLE is sent correctly 60 */ 61 rxx_frm_ctl.s.pre_chk = 1; 62 csr_wr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64); 63 64 return 0; 65} 66 67cvmx_helper_link_info_t cvmx_agl_link_get(int port) 68{ 69 cvmx_helper_link_info_t result; 70 int interface, port_index; 71 72 /* Fake IPD port is used on some older models. */ 73 if (port < 0) 74 return __cvmx_helper_board_link_get(port); 75 76 /* Simulator does not have PHY, use some defaults. */ 77 interface = cvmx_helper_get_interface_num(port); 78 port_index = cvmx_helper_get_interface_index_num(port); 79 if (cvmx_helper_get_port_force_link_up(interface, port_index)) { 80 result.u64 = 0; 81 result.s.full_duplex = 1; 82 result.s.link_up = 1; 83 result.s.speed = 1000; 84 return result; 85 } 86 87 return __cvmx_helper_board_link_get(port); 88} 89 90/* 91 * Set MII/RGMII link based on mode. 92 * 93 * @param port interface port to set the link. 94 * @param link_info Link status 95 * 96 * @return 0 on success and 1 on failure 97 */ 98int cvmx_agl_link_set(int port, cvmx_helper_link_info_t link_info) 99{ 100 cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx; 101 102 /* Disable GMX before we make any changes. */ 103 agl_gmx_prtx.u64 = csr_rd(CVMX_AGL_GMX_PRTX_CFG(port)); 104 agl_gmx_prtx.s.en = 0; 105 agl_gmx_prtx.s.tx_en = 0; 106 agl_gmx_prtx.s.rx_en = 0; 107 csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 108 109 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) { 110 u64 one_second = 0x1000000; /* todo: this needs checking */ 111 112 /* Wait for GMX to be idle */ 113 if (CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port), 114 cvmx_agl_gmx_prtx_cfg_t, rx_idle, ==, 115 1, one_second) || 116 CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port), 117 cvmx_agl_gmx_prtx_cfg_t, tx_idle, ==, 118 1, one_second)) { 119 debug("AGL%d: Timeout waiting for GMX to be idle\n", 120 port); 121 return -1; 122 } 123 } 124 125 agl_gmx_prtx.u64 = csr_rd(CVMX_AGL_GMX_PRTX_CFG(port)); 126 127 /* Set duplex mode */ 128 if (!link_info.s.link_up) 129 agl_gmx_prtx.s.duplex = 1; /* Force full duplex on down links */ 130 else 131 agl_gmx_prtx.s.duplex = link_info.s.full_duplex; 132 133 switch (link_info.s.speed) { 134 case 10: 135 agl_gmx_prtx.s.speed = 0; 136 agl_gmx_prtx.s.slottime = 0; 137 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) { 138 agl_gmx_prtx.s.speed_msb = 1; 139 agl_gmx_prtx.s.burst = 1; 140 } 141 break; 142 143 case 100: 144 agl_gmx_prtx.s.speed = 0; 145 agl_gmx_prtx.s.slottime = 0; 146 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) { 147 agl_gmx_prtx.s.speed_msb = 0; 148 agl_gmx_prtx.s.burst = 1; 149 } 150 break; 151 152 case 1000: 153 /* 1000 MBits is only supported on 6XXX chips */ 154 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) { 155 agl_gmx_prtx.s.speed_msb = 0; 156 agl_gmx_prtx.s.speed = 1; 157 agl_gmx_prtx.s.slottime = 158 1; /* Only matters for half-duplex */ 159 agl_gmx_prtx.s.burst = agl_gmx_prtx.s.duplex; 160 } 161 break; 162 163 /* No link */ 164 case 0: 165 default: 166 break; 167 } 168 169 /* Write the new GMX setting with the port still disabled. */ 170 csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 171 172 /* Read GMX CFG again to make sure the config is completed. */ 173 agl_gmx_prtx.u64 = csr_rd(CVMX_AGL_GMX_PRTX_CFG(port)); 174 175 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) { 176 cvmx_agl_gmx_txx_clk_t agl_clk; 177 cvmx_agl_prtx_ctl_t prt_ctl; 178 179 prt_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(port)); 180 agl_clk.u64 = csr_rd(CVMX_AGL_GMX_TXX_CLK(port)); 181 /* MII (both speeds) and RGMII 1000 setting */ 182 agl_clk.s.clk_cnt = 1; 183 /* Check other speeds for RGMII mode */ 184 if (prt_ctl.s.mode == 0 || OCTEON_IS_OCTEON3()) { 185 if (link_info.s.speed == 10) 186 agl_clk.s.clk_cnt = 50; 187 else if (link_info.s.speed == 100) 188 agl_clk.s.clk_cnt = 5; 189 } 190 csr_wr(CVMX_AGL_GMX_TXX_CLK(port), agl_clk.u64); 191 } 192 193 /* Enable transmit and receive ports */ 194 agl_gmx_prtx.s.tx_en = 1; 195 agl_gmx_prtx.s.rx_en = 1; 196 csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 197 198 /* Enable the link. */ 199 agl_gmx_prtx.s.en = 1; 200 csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 201 202 if (OCTEON_IS_OCTEON3()) { 203 union cvmx_agl_prtx_ctl agl_prtx_ctl; 204 /* Enable the interface, set clkrst */ 205 agl_prtx_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(port)); 206 agl_prtx_ctl.s.clkrst = 1; 207 csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); 208 csr_rd(CVMX_AGL_PRTX_CTL(port)); 209 agl_prtx_ctl.s.enable = 1; 210 csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); 211 /* Read the value back to force the previous write */ 212 csr_rd(CVMX_AGL_PRTX_CTL(port)); 213 } 214 215 return 0; 216} 217