1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 MediaTek Inc. All rights reserved. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 */ 7 8#include <init.h> 9#include <image.h> 10#include <vsprintf.h> 11#include <malloc.h> 12#include <asm/io.h> 13#include <asm/sections.h> 14#include <asm/addrspace.h> 15#include <asm/byteorder.h> 16#include <asm/global_data.h> 17#include <linux/sizes.h> 18#include <linux/types.h> 19#include <mach/serial.h> 20#include "../mt7621.h" 21#include "dram.h" 22#include <spl.h> 23 24DECLARE_GLOBAL_DATA_PTR; 25 26struct tpl_info { 27 u32 magic; 28 u32 size; 29}; 30 31void set_timer_freq_simple(void) 32{ 33 u32 div = get_xtal_mhz(); 34 35 /* Round down cpu freq */ 36 gd->arch.timer_freq = rounddown(CONFIG_MT7621_CPU_FREQ, div) * 500000; 37} 38 39void __noreturn board_init_f(ulong dummy) 40{ 41 spl_init(); 42 43#ifdef CONFIG_SPL_SERIAL 44 /* 45 * mtmips_spl_serial_init() is useful if debug uart is enabled, 46 * or DM based serial is not enabled. 47 */ 48 mtmips_spl_serial_init(); 49 preloader_console_init(); 50#endif 51 52 board_init_r(NULL, 0); 53} 54 55void board_boot_order(u32 *spl_boot_list) 56{ 57#ifdef CONFIG_MT7621_BOOT_FROM_NAND 58 spl_boot_list[0] = BOOT_DEVICE_NAND; 59#else 60 spl_boot_list[0] = BOOT_DEVICE_NOR; 61#endif 62} 63 64unsigned long spl_nor_get_uboot_base(void) 65{ 66 const struct tpl_info *tpli; 67 const struct legacy_img_hdr *hdr; 68 u32 addr; 69 70 addr = FLASH_MMAP_BASE + TPL_INFO_OFFSET; 71 tpli = (const struct tpl_info *)KSEG1ADDR(addr); 72 73 if (tpli->magic == TPL_INFO_MAGIC) { 74 addr = FLASH_MMAP_BASE + tpli->size; 75 hdr = (const struct legacy_img_hdr *)KSEG1ADDR(addr); 76 77 if (image_get_magic(hdr) == IH_MAGIC) { 78 addr += sizeof(*hdr) + image_get_size(hdr); 79 return KSEG1ADDR(addr); 80 } 81 } 82 83 panic("Unable to locate SPL payload\n"); 84 return 0; 85} 86 87uint32_t spl_nand_get_uboot_raw_page(void) 88{ 89 const struct stage_header *sh = (const struct stage_header *)_start; 90 u32 addr; 91 92 addr = image_get_header_size() + be32_to_cpu(sh->stage_size); 93 addr = ALIGN(addr, SZ_4K); 94 95 return addr; 96} 97