1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/dts-v1/;
7#include "mscc,serval.dtsi"
8#include <dt-bindings/mscc/serval_data.h>
9
10/ {
11	model = "Serval PCB105 Reference Board";
12	compatible = "mscc,serval-pcb105", "mscc,serval";
13
14	aliases {
15		spi0 = &spi0;
16		serial0 = &uart0;
17	};
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	gpio-leds {
24		compatible = "gpio-leds";
25
26		status_green {
27			label = "pcb105:green:status";
28			gpios = <&sgpio 43 1>; /* p11.1 */
29			default-state = "on";
30		};
31
32		status_red {
33			label = "pcb105:red:status";
34			gpios = <&sgpio 11 1>; /* p11.0 */
35			default-state = "off";
36		};
37	};
38};
39
40&uart0 {
41	status = "okay";
42};
43
44&spi0 {
45	status = "okay";
46	spi-flash@0 {
47		compatible = "jedec,spi-nor";
48		spi-max-frequency = <18000000>; /* input clock */
49		reg = <0>; /* CS0 */
50		spi-cs-high;
51	};
52};
53
54&sgpio {
55	status = "okay";
56	sgpio-ports = <0x00FFFFFF>;
57};
58
59&mdio1 {
60	status = "okay";
61
62	phy16: ethernet-phy@16 {
63		reg = <16>;
64	};
65	phy17: ethernet-phy@17 {
66		reg = <17>;
67	};
68	phy18: ethernet-phy@18 {
69		reg = <18>;
70	};
71	phy19: ethernet-phy@19 {
72		reg = <19>;
73	};
74};
75
76&switch {
77	ethernet-ports {
78
79		port0: port@0 {
80			reg = <7>;
81			phy-handle = <&phy16>;
82			phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>;
83		};
84		port1: port@1 {
85			reg = <6>;
86			phy-handle = <&phy17>;
87			phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>;
88		};
89		port2: port@2 {
90			reg = <5>;
91			phy-handle = <&phy18>;
92			phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>;
93		};
94		port3: port@3 {
95			reg = <4>;
96			phy-handle = <&phy19>;
97			phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>;
98		};
99	};
100};
101