1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11	compatible = "mscc,luton";
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			compatible = "mips,mips24KEc";
19			device_type = "cpu";
20			reg = <0>;
21		};
22	};
23
24	aliases {
25		serial0 = &uart0;
26	};
27
28	sys_clk: sys-clk {
29		compatible = "fixed-clock";
30		#clock-cells = <0>;
31		clock-frequency = <250000000>;
32	};
33	ahb_clk: ahb-clk {
34		compatible = "fixed-clock";
35		#clock-cells = <0>;
36		clock-frequency = <208333333>;
37	};
38
39	ahb {
40		compatible = "simple-bus";
41		#address-cells = <1>;
42		#size-cells = <1>;
43		ranges = <0 0x60000000 0x10200000>;
44
45		uart0: serial@10100000 {
46			pinctrl-0 = <&uart_pins>;
47			pinctrl-names = "default";
48
49			compatible = "ns16550a";
50			reg = <0x10100000 0x20>;
51			clocks = <&ahb_clk>;
52			reg-io-width = <4>;
53			reg-shift = <2>;
54
55			status = "disabled";
56		};
57
58		gpio: pinctrl@70068 {
59			compatible = "mscc,luton-pinctrl";
60			reg = <0x70068 0x68>;
61			gpio-controller;
62			#gpio-cells = <2>;
63			gpio-ranges = <&gpio 0 0 32>;
64
65			sgpio_pins: sgpio-pins {
66				pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
67				function = "sio";
68			};
69			uart_pins: uart-pins {
70				pins = "GPIO_30", "GPIO_31";
71				function = "uart";
72			};
73		};
74
75		sgpio: gpio@70130 {
76			compatible = "mscc,luton-sgpio";
77			status = "disabled";
78			clocks = <&sys_clk>;
79			pinctrl-0 = <&sgpio_pins>;
80			pinctrl-names = "default";
81			reg = <0x0070130 0x100>;
82			gpio-controller;
83			#gpio-cells = <2>;
84			gpio-ranges = <&sgpio 0 0 64>;
85		};
86
87		spi0: spi-bitbang {
88			compatible = "mscc,luton-bb-spi";
89			status = "okay";
90			reg = <0x10000064 0x4>;
91			num-chipselects = <1>;
92			#address-cells = <1>;
93			#size-cells = <0>;
94		};
95
96		switch: switch@1010000 {
97			compatible = "mscc,vsc7527-switch";
98			reg = <0x1e0000 0x0100>, // VTSS_TO_DEV_0
99			      <0x1f0000 0x0100>, // VTSS_TO_DEV_1
100			      <0x200000 0x0100>, // VTSS_TO_DEV_2
101			      <0x210000 0x0100>, // VTSS_TO_DEV_3
102			      <0x220000 0x0100>, // VTSS_TO_DEV_4
103			      <0x230000 0x0100>, // VTSS_TO_DEV_5
104			      <0x240000 0x0100>, // VTSS_TO_DEV_6
105			      <0x250000 0x0100>, // VTSS_TO_DEV_7
106			      <0x260000 0x0100>, // VTSS_TO_DEV_8
107			      <0x270000 0x0100>, // VTSS_TO_DEV_9
108			      <0x280000 0x0100>, // VTSS_TO_DEV_10
109			      <0x290000 0x0100>, // VTSS_TO_DEV_11
110			      <0x2a0000 0x0100>, // VTSS_TO_DEV_12
111			      <0x2b0000 0x0100>, // VTSS_TO_DEV_13
112			      <0x2c0000 0x0100>, // VTSS_TO_DEV_14
113			      <0x2d0000 0x0100>, // VTSS_TO_DEV_15
114			      <0x2e0000 0x0100>, // VTSS_TO_DEV_16
115			      <0x2f0000 0x0100>, // VTSS_TO_DEV_17
116			      <0x300000 0x0100>, // VTSS_TO_DEV_18
117			      <0x310000 0x0100>, // VTSS_TO_DEV_19
118			      <0x320000 0x0100>, // VTSS_TO_DEV_20
119			      <0x330000 0x0100>, // VTSS_TO_DEV_21
120			      <0x340000 0x0100>, // VTSS_TO_DEV_22
121			      <0x350000 0x0100>, // VTSS_TO_DEV_23
122			      <0x010000 0x1000>, // VTSS_TO_SYS
123			      <0x020000 0x1000>, // VTSS_TO_ANA
124			      <0x030000 0x1000>, // VTSS_TO_REW
125			      <0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB
126			      <0x080000 0x0100>, // VTSS_TO_DEVCPU_QS
127			      <0x0a0000 0x10000>; // VTSS_TO_HSIO
128			reg-names = "port0", "port1", "port2", "port3",
129				    "port4", "port5", "port6", "port7",
130				    "port8", "port9", "port10", "port11",
131				    "port12", "port13", "port14", "port15",
132				    "port16", "port17", "port18", "port19",
133				    "port20", "port21", "port22", "port23",
134				    "sys", "ana", "rew", "gcb", "qs", "hsio";
135			status = "okay";
136
137			ethernet-ports {
138				#address-cells = <1>;
139				#size-cells = <0>;
140			};
141		};
142
143		mdio0: mdio@700a0 {
144			#address-cells = <1>;
145			#size-cells = <0>;
146			compatible = "mscc,luton-miim";
147			reg = <0x700a0 0x24>;
148			status = "disabled";
149		};
150
151		mdio1: mdio@700c4 {
152			#address-cells = <1>;
153			#size-cells = <0>;
154			compatible = "mscc,luton-miim";
155			reg = <0x700c4 0x24>;
156			status = "disabled";
157		};
158
159		hsio: syscon@10d0000 {
160			compatible = "mscc,luton-hsio", "syscon", "simple-mfd";
161			reg = <0xa0000 0x10000>;
162
163			serdes_hsio: serdes_hsio {
164				compatible = "mscc,vsc7527-serdes";
165				#phy-cells = <3>;
166			};
167		};
168	};
169};
170