1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/dts-v1/;
7#include "mscc,luton.dtsi"
8
9/ {
10	model = "Luton10 PCB091 Reference Board";
11	compatible = "mscc,luton-pcb091", "mscc,luton";
12
13	aliases {
14		serial0 = &uart0;
15		spi0 = &spi0;
16	};
17
18	chosen {
19		stdout-path = "serial0:115200n8";
20	};
21
22	gpio-leds {
23		compatible = "gpio-leds";
24
25		top_dimmer {
26			label = "pcb091:top:dimmer";
27			gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
28			default-state = "on";
29		};
30
31		status_green {
32			label = "pcb091:green:status";
33			gpios = <&sgpio 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
34			default-state = "on";
35		};
36
37		status_red {
38			label = "pcb091:red:status";
39			gpios = <&sgpio 58 GPIO_ACTIVE_HIGH>; /* p26.1 */
40			default-state = "off";
41		};
42	};
43};
44
45&sgpio {
46	status = "okay";
47	mscc,sgpio-ports = <0xFFF000FF>;
48};
49
50&uart0 {
51	status = "okay";
52};
53
54&spi0 {
55	status = "okay";
56	spi-flash@0 {
57		compatible = "jedec,spi-nor";
58		spi-max-frequency = <18000000>; /* input clock */
59		reg = <0>; /* CS0 */
60		spi-cs-high;
61	};
62};
63
64&mdio0 {
65	status = "okay";
66
67	phy0: ethernet-phy@0 {
68		reg = <0>;
69	};
70	phy1: ethernet-phy@1 {
71		reg = <1>;
72	};
73	phy2: ethernet-phy@2 {
74		reg = <2>;
75	};
76	phy3: ethernet-phy@3 {
77		reg = <3>;
78	};
79	phy4: ethernet-phy@4 {
80		reg = <4>;
81	};
82	phy5: ethernet-phy@5 {
83		reg = <5>;
84	};
85	phy6: ethernet-phy@6 {
86		reg = <6>;
87	};
88	phy7: ethernet-phy@7 {
89		reg = <7>;
90	};
91	phy8: ethernet-phy@8 {
92		reg = <8>;
93	};
94	phy9: ethernet-phy@9 {
95		reg = <9>;
96	};
97	phy10: ethernet-phy@10 {
98		reg = <10>;
99	};
100	phy11: ethernet-phy@11 {
101		reg = <11>;
102	};
103};
104
105&switch {
106	ethernet-ports {
107		port0: port@0 {
108			reg = <0>;
109			phy-handle = <&phy0>;
110		};
111		port1: port@1 {
112			reg = <1>;
113			phy-handle = <&phy1>;
114		};
115		port2: port@2 {
116			reg = <2>;
117			phy-handle = <&phy2>;
118		};
119		port3: port@3 {
120			reg = <3>;
121			phy-handle = <&phy3>;
122		};
123		port4: port@4 {
124			reg = <4>;
125			phy-handle = <&phy4>;
126		};
127		port5: port@5 {
128			reg = <5>;
129			phy-handle = <&phy5>;
130		};
131		port6: port@6 {
132			reg = <6>;
133			phy-handle = <&phy6>;
134		};
135		port7: port@7 {
136			reg = <7>;
137			phy-handle = <&phy7>;
138		};
139		port8: port@8 {
140			reg = <8>;
141			phy-handle = <&phy8>;
142		};
143		port9: port@9 {
144			reg = <9>;
145			phy-handle = <&phy9>;
146		};
147		port10: port@10 {
148			reg = <10>;
149			phy-handle = <&phy10>;
150		};
151		port11: port@11 {
152			reg = <11>;
153			phy-handle = <&phy11>;
154		};
155	};
156};
157