1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6/dts-v1/;
7#include "mscc,jr2.dtsi"
8#include <dt-bindings/mscc/jr2_data.h>
9
10/ {
11	model = "Jaguar2 Cu48 PCB111 Reference Board";
12	compatible = "mscc,jr2-pcb111", "mscc,jr2";
13
14	aliases {
15		spi0 = &spi0;
16		serial0 = &uart0;
17	};
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	gpio-leds {
24		compatible = "gpio-leds";
25
26		status_green {
27			label = "pcb111:green:status";
28			gpios = <&gpio 12 0>;
29			default-state = "on";
30		};
31
32		status_red {
33			label = "pcb111:red:status";
34			gpios = <&gpio 13 0>;
35			default-state = "off";
36		};
37	};
38};
39
40&uart0 {
41	status = "okay";
42};
43
44&spi0 {
45	status = "okay";
46	spi-flash@0 {
47		compatible = "jedec,spi-nor";
48		spi-max-frequency = <18000000>; /* input clock */
49		reg = <0>; /* CS0 */
50	};
51};
52
53&gpio {
54	/* SPIO only use DO, CLK, no inputs */
55	sgpio1_pins: sgpio1-pins {
56		pins = "GPIO_4", "GPIO_5";
57		function = "sg1";
58	};
59};
60
61&sgpio {
62	status = "okay";
63	sgpio-ports = <0xffffffff>;
64};
65
66&sgpio1 {
67	status = "okay";
68	sgpio-ports = <0x001effff>;
69};
70
71&sgpio2 {
72	status = "okay";
73	sgpio-ports = <0xff000000>;
74	gpio-ranges = <&sgpio2 0 0 96>;
75};
76
77&mdio1 {
78	status = "okay";
79
80	phy0: ethernet-phy@0 {
81		reg = <0>;
82	};
83	phy1: ethernet-phy@1 {
84		reg = <1>;
85	};
86	phy2: ethernet-phy@2 {
87		reg = <2>;
88	};
89	phy3: ethernet-phy@3 {
90		reg = <3>;
91	};
92	phy4: ethernet-phy@4 {
93		reg = <4>;
94	};
95	phy5: ethernet-phy@5 {
96		reg = <5>;
97	};
98	phy6: ethernet-phy@6 {
99		reg = <6>;
100	};
101	phy7: ethernet-phy@7 {
102		reg = <7>;
103	};
104	phy8: ethernet-phy@8 {
105		reg = <8>;
106	};
107	phy9: ethernet-phy@9 {
108		reg = <9>;
109	};
110	phy10: ethernet-phy@10 {
111		reg = <10>;
112	};
113	phy11: ethernet-phy@11 {
114		reg = <11>;
115	};
116	phy12: ethernet-phy@12 {
117		reg = <12>;
118	};
119	phy13: ethernet-phy@13 {
120		reg = <13>;
121	};
122	phy14: ethernet-phy@14 {
123		reg = <14>;
124	};
125	phy15: ethernet-phy@15 {
126		reg = <15>;
127	};
128	phy16: ethernet-phy@16 {
129		reg = <16>;
130	};
131	phy17: ethernet-phy@17 {
132		reg = <17>;
133	};
134	phy18: ethernet-phy@18 {
135		reg = <18>;
136	};
137	phy19: ethernet-phy@19 {
138		reg = <19>;
139	};
140	phy20: ethernet-phy@20 {
141		reg = <20>;
142	};
143	phy21: ethernet-phy@21 {
144		reg = <21>;
145	};
146	phy22: ethernet-phy@22 {
147		reg = <22>;
148	};
149	phy23: ethernet-phy@23 {
150		reg = <23>;
151	};
152};
153
154&mdio2 {
155	status = "okay";
156
157	phy24: ethernet-phy@24 {
158		reg = <0>;
159	};
160	phy25: ethernet-phy@25 {
161		reg = <1>;
162	};
163	phy26: ethernet-phy@26 {
164		reg = <2>;
165	};
166	phy27: ethernet-phy@27 {
167		reg = <3>;
168	};
169	phy28: ethernet-phy@28 {
170		reg = <4>;
171	};
172	phy29: ethernet-phy@29 {
173		reg = <5>;
174	};
175	phy30: ethernet-phy@30 {
176		reg = <6>;
177	};
178	phy31: ethernet-phy@31 {
179		reg = <7>;
180	};
181	phy32: ethernet-phy@32 {
182		reg = <8>;
183	};
184	phy33: ethernet-phy@33 {
185		reg = <9>;
186	};
187	phy34: ethernet-phy@34 {
188		reg = <10>;
189	};
190	phy35: ethernet-phy@35 {
191		reg = <11>;
192	};
193	phy36: ethernet-phy@36 {
194		reg = <12>;
195	};
196	phy37: ethernet-phy@37 {
197		reg = <13>;
198	};
199	phy38: ethernet-phy@38 {
200		reg = <14>;
201	};
202	phy39: ethernet-phy@39 {
203		reg = <15>;
204	};
205	phy40: ethernet-phy@40 {
206		reg = <16>;
207	};
208	phy41: ethernet-phy@41 {
209		reg = <17>;
210	};
211	phy42: ethernet-phy@42 {
212		reg = <18>;
213	};
214	phy43: ethernet-phy@43 {
215		reg = <19>;
216	};
217	phy44: ethernet-phy@44 {
218		reg = <20>;
219	};
220	phy45: ethernet-phy@45 {
221		reg = <21>;
222	};
223	phy46: ethernet-phy@46 {
224		reg = <22>;
225	};
226	phy47: ethernet-phy@47 {
227		reg = <23>;
228	};
229};
230
231&switch {
232	ethernet-ports {
233		port0: port@0 {
234			reg = <0>;
235			phy-handle = <&phy0>;
236			phys = <&serdes_hsio 0 SERDES6G(4) PHY_MODE_QSGMII>;
237		};
238		port1: port@1 {
239			reg = <1>;
240			phy-handle = <&phy1>;
241			phys = <&serdes_hsio 1 0xff PHY_MODE_QSGMII>;
242		};
243		port2: port@2 {
244			reg = <2>;
245			phy-handle = <&phy2>;
246			phys = <&serdes_hsio 2 0xff PHY_MODE_QSGMII>;
247		};
248		port3: port@3 {
249			reg = <3>;
250			phy-handle = <&phy3>;
251			phys = <&serdes_hsio 3 0xff PHY_MODE_QSGMII>;
252		};
253		port4: port@4 {
254			reg = <4>;
255			phy-handle = <&phy4>;
256			phys = <&serdes_hsio 4 SERDES6G(5) PHY_MODE_QSGMII>;
257		};
258		port5: port@5 {
259			reg = <5>;
260			phy-handle = <&phy5>;
261			phys = <&serdes_hsio 5 0xff PHY_MODE_QSGMII>;
262		};
263		port6: port@6 {
264			reg = <6>;
265			phy-handle = <&phy6>;
266			phys = <&serdes_hsio 6 0xff PHY_MODE_QSGMII>;
267		};
268		port7: port@7 {
269			reg = <7>;
270			phy-handle = <&phy7>;
271			phys = <&serdes_hsio 7 0xff PHY_MODE_QSGMII>;
272		};
273		port8: port@8 {
274			reg = <8>;
275			phy-handle = <&phy8>;
276			phys = <&serdes_hsio 8 SERDES6G(6) PHY_MODE_QSGMII>;
277		};
278		port9: port@9 {
279			reg = <9>;
280			phy-handle = <&phy9>;
281			phys = <&serdes_hsio 9 0xff PHY_MODE_QSGMII>;
282		};
283		port10: port@10 {
284			reg = <10>;
285			phy-handle = <&phy10>;
286			phys = <&serdes_hsio 10 0xff PHY_MODE_QSGMII>;
287		};
288		port11: port@11 {
289			reg = <11>;
290			phy-handle = <&phy11>;
291			phys = <&serdes_hsio 11 0xff PHY_MODE_QSGMII>;
292		};
293		port12: port@12 {
294			reg = <12>;
295			phy-handle = <&phy12>;
296			phys = <&serdes_hsio 12 SERDES6G(7) PHY_MODE_QSGMII>;
297		};
298		port13: port@13 {
299			reg = <13>;
300			phy-handle = <&phy13>;
301			phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
302		};
303		port14: port@14 {
304			reg = <14>;
305			phy-handle = <&phy14>;
306			phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
307		};
308		port15: port@15 {
309			reg = <15>;
310			phy-handle = <&phy15>;
311			phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
312		};
313		port16: port@16 {
314			reg = <16>;
315			phy-handle = <&phy16>;
316			phys = <&serdes_hsio 16 SERDES6G(8) PHY_MODE_QSGMII>;
317		};
318		port17: port@17 {
319			reg = <17>;
320			phy-handle = <&phy17>;
321			phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
322		};
323		port18: port@18 {
324			reg = <18>;
325			phy-handle = <&phy18>;
326			phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
327		};
328		port19: port@19 {
329			reg = <19>;
330			phy-handle = <&phy19>;
331			phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
332		};
333		port20: port@20 {
334			reg = <20>;
335			phy-handle = <&phy20>;
336			phys = <&serdes_hsio 20 SERDES6G(9) PHY_MODE_QSGMII>;
337		};
338		port21: port@21 {
339			reg = <21>;
340			phy-handle = <&phy21>;
341			phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
342		};
343		port22: port@22 {
344			reg = <22>;
345			phy-handle = <&phy22>;
346			phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
347		};
348		port23: port@23 {
349			reg = <23>;
350			phy-handle = <&phy23>;
351			phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
352		};
353		port24: port@24 {
354			reg = <24>;
355			phy-handle = <&phy24>;
356			phys = <&serdes_hsio 24 SERDES6G(10) PHY_MODE_QSGMII>;
357		};
358		port25: port@25 {
359			reg = <25>;
360			phy-handle = <&phy25>;
361			phys = <&serdes_hsio 25 0xff PHY_MODE_QSGMII>;
362		};
363		port26: port@26 {
364			reg = <26>;
365			phy-handle = <&phy26>;
366			phys = <&serdes_hsio 26 0xff PHY_MODE_QSGMII>;
367		};
368		port27: port@27 {
369			reg = <27>;
370			phy-handle = <&phy27>;
371			phys = <&serdes_hsio 27 0xff PHY_MODE_QSGMII>;
372		};
373		port28: port@28 {
374			reg = <28>;
375			phy-handle = <&phy28>;
376			phys = <&serdes_hsio 28 SERDES6G(11) PHY_MODE_QSGMII>;
377		};
378		port29: port@29 {
379			reg = <29>;
380			phy-handle = <&phy29>;
381			phys = <&serdes_hsio 29 0xff PHY_MODE_QSGMII>;
382		};
383		port30: port@30 {
384			reg = <30>;
385			phy-handle = <&phy30>;
386			phys = <&serdes_hsio 30 0xff PHY_MODE_QSGMII>;
387		};
388		port31: port@31 {
389			reg = <31>;
390			phy-handle = <&phy31>;
391			phys = <&serdes_hsio 31 0xff PHY_MODE_QSGMII>;
392		};
393		port32: port@32 {
394			reg = <32>;
395			phy-handle = <&phy32>;
396			phys = <&serdes_hsio 32 SERDES6G(12) PHY_MODE_QSGMII>;
397		};
398		port33: port@33 {
399			reg = <33>;
400			phy-handle = <&phy33>;
401			phys = <&serdes_hsio 33 0xff PHY_MODE_QSGMII>;
402		};
403		port34: port@34 {
404			reg = <34>;
405			phy-handle = <&phy34>;
406			phys = <&serdes_hsio 34 0xff PHY_MODE_QSGMII>;
407		};
408		port35: port@35 {
409			reg = <35>;
410			phy-handle = <&phy35>;
411			phys = <&serdes_hsio 35 0xff PHY_MODE_QSGMII>;
412		};
413		port36: port@36 {
414			reg = <36>;
415			phy-handle = <&phy36>;
416			phys = <&serdes_hsio 36 SERDES6G(13) PHY_MODE_QSGMII>;
417		};
418		port37: port@37 {
419			reg = <37>;
420			phy-handle = <&phy37>;
421			phys = <&serdes_hsio 37 0xff PHY_MODE_QSGMII>;
422		};
423		port38: port@38 {
424			reg = <38>;
425			phy-handle = <&phy38>;
426			phys = <&serdes_hsio 38 0xff PHY_MODE_QSGMII>;
427		};
428		port39: port@39 {
429			reg = <39>;
430			phy-handle = <&phy39>;
431			phys = <&serdes_hsio 39 0xff PHY_MODE_QSGMII>;
432		};
433		port40: port@40 {
434			reg = <40>;
435			phy-handle = <&phy40>;
436			phys = <&serdes_hsio 40 SERDES6G(14) PHY_MODE_QSGMII>;
437		};
438		port41: port@41 {
439			reg = <41>;
440			phy-handle = <&phy41>;
441			phys = <&serdes_hsio 41 0xff PHY_MODE_QSGMII>;
442		};
443		port42: port@42 {
444			reg = <42>;
445			phy-handle = <&phy42>;
446			phys = <&serdes_hsio 42 0xff PHY_MODE_QSGMII>;
447		};
448		port43: port@43 {
449			reg = <43>;
450			phy-handle = <&phy43>;
451			phys = <&serdes_hsio 43 0xff PHY_MODE_QSGMII>;
452		};
453		port44: port@44 {
454			reg = <44>;
455			phy-handle = <&phy44>;
456			phys = <&serdes_hsio 44 SERDES6G(15) PHY_MODE_QSGMII>;
457		};
458		port45: port@45 {
459			reg = <45>;
460			phy-handle = <&phy45>;
461			phys = <&serdes_hsio 45 0xff PHY_MODE_QSGMII>;
462		};
463		port46: port@46 {
464			reg = <46>;
465			phy-handle = <&phy46>;
466			phys = <&serdes_hsio 46 0xff PHY_MODE_QSGMII>;
467		};
468		port47: port@47 {
469			reg = <47>;
470			phy-handle = <&phy47>;
471			phys = <&serdes_hsio 47 0xff PHY_MODE_QSGMII>;
472		};
473	};
474};
475