1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Interrupt Controller Memory Map
4 *
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 */
8
9#ifndef __INTCTRL_H__
10#define __INTCTRL_H__
11
12#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
13    defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
14    defined(CONFIG_M547x)
15#	define	CFG_SYS_CF_INTC_REG1
16#endif
17
18typedef struct int0_ctrl {
19	/* Interrupt Controller 0 */
20	u32 iprh0;		/* 0x00 Pending High */
21	u32 iprl0;		/* 0x04 Pending Low */
22	u32 imrh0;		/* 0x08 Mask High */
23	u32 imrl0;		/* 0x0C Mask Low */
24	u32 frch0;		/* 0x10 Force High */
25	u32 frcl0;		/* 0x14 Force Low */
26#if defined(CFG_SYS_CF_INTC_REG1)
27	u8 irlr;		/* 0x18 */
28	u8 iacklpr;		/* 0x19 */
29	u16 res1[19];		/* 0x1a - 0x3c */
30#else
31	u16 res1;		/* 0x18 - 0x19 */
32	u16 icfg0;		/* 0x1A Configuration */
33	u8 simr0;		/* 0x1C Set Interrupt Mask */
34	u8 cimr0;		/* 0x1D Clear Interrupt Mask */
35	u8 clmask0;		/* 0x1E Current Level Mask */
36	u8 slmask;		/* 0x1F Saved Level Mask */
37	u32 res2[8];		/* 0x20 - 0x3F */
38#endif
39	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
40	u32 res3[24];		/* 0x80 - 0xDF */
41	u8 swiack0;		/* 0xE0 Software Interrupt ack */
42	u8 res4[3];		/* 0xE1 - 0xE3 */
43	u8 L1iack0;		/* 0xE4 Level n interrupt ack */
44	u8 res5[3];		/* 0xE5 - 0xE7 */
45	u8 L2iack0;		/* 0xE8 Level n interrupt ack */
46	u8 res6[3];		/* 0xE9 - 0xEB */
47	u8 L3iack0;		/* 0xEC Level n interrupt ack */
48	u8 res7[3];		/* 0xED - 0xEF */
49	u8 L4iack0;		/* 0xF0 Level n interrupt ack */
50	u8 res8[3];		/* 0xF1 - 0xF3 */
51	u8 L5iack0;		/* 0xF4 Level n interrupt ack */
52	u8 res9[3];		/* 0xF5 - 0xF7 */
53	u8 L6iack0;		/* 0xF8 Level n interrupt ack */
54	u8 resa[3];		/* 0xF9 - 0xFB */
55	u8 L7iack0;		/* 0xFC Level n interrupt ack */
56	u8 resb[3];		/* 0xFD - 0xFF */
57} int0_t;
58
59typedef struct int1_ctrl {
60	/* Interrupt Controller 1 */
61	u32 iprh1;		/* 0x00 Pending High */
62	u32 iprl1;		/* 0x04 Pending Low */
63	u32 imrh1;		/* 0x08 Mask High */
64	u32 imrl1;		/* 0x0C Mask Low */
65	u32 frch1;		/* 0x10 Force High */
66	u32 frcl1;		/* 0x14 Force Low */
67#if defined(CFG_SYS_CF_INTC_REG1)
68	u8 irlr;		/* 0x18 */
69	u8 iacklpr;		/* 0x19 */
70	u16 res1[19];		/* 0x1a - 0x3c */
71#else
72	u16 res1;		/* 0x18 */
73	u16 icfg1;		/* 0x1A Configuration */
74	u8 simr1;		/* 0x1C Set Interrupt Mask */
75	u8 cimr1;		/* 0x1D Clear Interrupt Mask */
76	u16 res2;		/* 0x1E - 0x1F */
77	u32 res3[8];		/* 0x20 - 0x3F */
78#endif
79	u8 icr1[64];		/* 0x40 - 0x7F */
80	u32 res4[24];		/* 0x80 - 0xDF */
81	u8 swiack1;		/* 0xE0 Software Interrupt ack */
82	u8 res5[3];		/* 0xE1 - 0xE3 */
83	u8 L1iack1;		/* 0xE4 Level n interrupt ack */
84	u8 res6[3];		/* 0xE5 - 0xE7 */
85	u8 L2iack1;		/* 0xE8 Level n interrupt ack */
86	u8 res7[3];		/* 0xE9 - 0xEB */
87	u8 L3iack1;		/* 0xEC Level n interrupt ack */
88	u8 res8[3];		/* 0xED - 0xEF */
89	u8 L4iack1;		/* 0xF0 Level n interrupt ack */
90	u8 res9[3];		/* 0xF1 - 0xF3 */
91	u8 L5iack1;		/* 0xF4 Level n interrupt ack */
92	u8 resa[3];		/* 0xF5 - 0xF7 */
93	u8 L6iack1;		/* 0xF8 Level n interrupt ack */
94	u8 resb[3];		/* 0xF9 - 0xFB */
95	u8 L7iack1;		/* 0xFC Level n interrupt ack */
96	u8 resc[3];		/* 0xFD - 0xFF */
97} int1_t;
98
99typedef struct intgack_ctrl1 {
100	/* Global IACK Registers */
101	u8 swiack;		/* 0x00 Global Software Interrupt ack */
102	u8 res0[0x3];
103	u8 gl1iack;		/* 0x04 */
104	u8 resv1[0x3];
105	u8 gl2iack;		/* 0x08 */
106	u8 res2[0x3];
107	u8 gl3iack;		/* 0x0C */
108	u8 res3[0x3];
109	u8 gl4iack;		/* 0x10 */
110	u8 res4[0x3];
111	u8 gl5iack;		/* 0x14 */
112	u8 res5[0x3];
113	u8 gl6iack;		/* 0x18 */
114	u8 res6[0x3];
115	u8 gl7iack;		/* 0x1C */
116	u8 res7[0x3];
117} intgack_t;
118
119#define INTC_IPRH_INT63			(0x80000000)
120#define INTC_IPRH_INT62			(0x40000000)
121#define INTC_IPRH_INT61			(0x20000000)
122#define INTC_IPRH_INT60			(0x10000000)
123#define INTC_IPRH_INT59			(0x08000000)
124#define INTC_IPRH_INT58			(0x04000000)
125#define INTC_IPRH_INT57			(0x02000000)
126#define INTC_IPRH_INT56			(0x01000000)
127#define INTC_IPRH_INT55			(0x00800000)
128#define INTC_IPRH_INT54			(0x00400000)
129#define INTC_IPRH_INT53			(0x00200000)
130#define INTC_IPRH_INT52			(0x00100000)
131#define INTC_IPRH_INT51			(0x00080000)
132#define INTC_IPRH_INT50			(0x00040000)
133#define INTC_IPRH_INT49			(0x00020000)
134#define INTC_IPRH_INT48			(0x00010000)
135#define INTC_IPRH_INT47			(0x00008000)
136#define INTC_IPRH_INT46			(0x00004000)
137#define INTC_IPRH_INT45			(0x00002000)
138#define INTC_IPRH_INT44			(0x00001000)
139#define INTC_IPRH_INT43			(0x00000800)
140#define INTC_IPRH_INT42			(0x00000400)
141#define INTC_IPRH_INT41			(0x00000200)
142#define INTC_IPRH_INT40			(0x00000100)
143#define INTC_IPRH_INT39			(0x00000080)
144#define INTC_IPRH_INT38			(0x00000040)
145#define INTC_IPRH_INT37			(0x00000020)
146#define INTC_IPRH_INT36			(0x00000010)
147#define INTC_IPRH_INT35			(0x00000008)
148#define INTC_IPRH_INT34			(0x00000004)
149#define INTC_IPRH_INT33			(0x00000002)
150#define INTC_IPRH_INT32			(0x00000001)
151
152#define INTC_IPRL_INT31			(0x80000000)
153#define INTC_IPRL_INT30			(0x40000000)
154#define INTC_IPRL_INT29			(0x20000000)
155#define INTC_IPRL_INT28			(0x10000000)
156#define INTC_IPRL_INT27			(0x08000000)
157#define INTC_IPRL_INT26			(0x04000000)
158#define INTC_IPRL_INT25			(0x02000000)
159#define INTC_IPRL_INT24			(0x01000000)
160#define INTC_IPRL_INT23			(0x00800000)
161#define INTC_IPRL_INT22			(0x00400000)
162#define INTC_IPRL_INT21			(0x00200000)
163#define INTC_IPRL_INT20			(0x00100000)
164#define INTC_IPRL_INT19			(0x00080000)
165#define INTC_IPRL_INT18			(0x00040000)
166#define INTC_IPRL_INT17			(0x00020000)
167#define INTC_IPRL_INT16			(0x00010000)
168#define INTC_IPRL_INT15			(0x00008000)
169#define INTC_IPRL_INT14			(0x00004000)
170#define INTC_IPRL_INT13			(0x00002000)
171#define INTC_IPRL_INT12			(0x00001000)
172#define INTC_IPRL_INT11			(0x00000800)
173#define INTC_IPRL_INT10			(0x00000400)
174#define INTC_IPRL_INT9			(0x00000200)
175#define INTC_IPRL_INT8			(0x00000100)
176#define INTC_IPRL_INT7			(0x00000080)
177#define INTC_IPRL_INT6			(0x00000040)
178#define INTC_IPRL_INT5			(0x00000020)
179#define INTC_IPRL_INT4			(0x00000010)
180#define INTC_IPRL_INT3			(0x00000008)
181#define INTC_IPRL_INT2			(0x00000004)
182#define INTC_IPRL_INT1			(0x00000002)
183#define INTC_IPRL_INT0			(0x00000001)
184
185#define INTC_IMRLn_MASKALL		(0x00000001)
186
187#define INTC_IRLR(x)			(((x) & 0x7F) << 1)
188#define INTC_IRLR_MASK			(0x01)
189
190#define INTC_IACKLPR_LVL(x)		(((x) & 0x07) << 4)
191#define INTC_IACKLPR_LVL_MASK		(0x8F)
192#define INTC_IACKLPR_PRI(x)		((x) & 0x0F)
193#define INTC_IACKLPR_PRI_MASK		(0xF0)
194
195#if defined(CFG_SYS_CF_INTC_REG1)
196#define INTC_ICR_IL(x)			(((x) & 0x07) << 3)
197#define INTC_ICR_IL_MASK		(0xC7)
198#define INTC_ICR_IP(x)			((x) & 0x07)
199#define INTC_ICR_IP_MASK		(0xF8)
200#else
201#define INTC_ICR_IL(x)			((x) & 0x07)
202#define INTC_ICR_IL_MASK		(0xF8)
203#endif
204
205#define INTC_ICONFIG_ELVLPRI_MASK	(0x01FF)
206#define INTC_ICONFIG_ELVLPRI7		(0x8000)
207#define INTC_ICONFIG_ELVLPRI6		(0x4000)
208#define INTC_ICONFIG_ELVLPRI5		(0x2000)
209#define INTC_ICONFIG_ELVLPRI4		(0x1000)
210#define INTC_ICONFIG_ELVLPRI3		(0x0800)
211#define INTC_ICONFIG_ELVLPRI2		(0x0400)
212#define INTC_ICONFIG_ELVLPRI1		(0x0200)
213#define INTC_ICONFIG_EMASK		(0x0020)
214
215#define INTC_SIMR_ALL			(0x40)
216#define INTC_SIMR(x)			((x) & 0x3F)
217#define INTC_SIMR_MASK			(0x80)
218
219#define INTC_CIMR_ALL			(0x40)
220#define INTC_CIMR(x)			((x) & 0x3F)
221#define INTC_CIMR_MASK			(0x80)
222
223#define INTC_CLMASK(x)			((x) & 0x0F)
224#define INTC_CLMASK_MASK		(0xF0)
225
226#define INTC_SLMASK(x)			((x) & 0x0F)
227#define INTC_SLMASK_MASK		(0xF0)
228
229#endif				/* __INTCTRL_H__ */
230