1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2003
4 * Josef Baumgartner <josef.baumgartner@telex.de>
5 *
6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 * Hayden Fraser (Hayden.Fraser@freescale.com)
8 */
9
10#include <clock_legacy.h>
11#include <asm/global_data.h>
12#include <asm/processor.h>
13#include <asm/immap.h>
14#include <asm/io.h>
15#include <linux/delay.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
20int get_clocks(void)
21{
22#if defined(CONFIG_M5208)
23	pll_t *pll = (pll_t *) MMAP_PLL;
24
25	out_8(&pll->odr, CFG_SYS_PLL_ODR);
26	out_8(&pll->fdr, CFG_SYS_PLL_FDR);
27#endif
28
29#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
30	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
31	unsigned long pllcr;
32
33#ifndef CFG_SYS_PLL_BYPASS
34
35#ifdef CONFIG_M5249
36	/* Setup the PLL to run at the specified speed */
37#ifdef CFG_SYS_FAST_CLK
38	pllcr = 0x925a3100;	/* ~140MHz clock (PLL bypass = 0) */
39#else
40	pllcr = 0x135a4140;	/* ~72MHz clock (PLL bypass = 0) */
41#endif
42#endif				/* CONFIG_M5249 */
43
44#ifdef CONFIG_M5253
45	pllcr = CFG_SYS_PLLCR;
46#endif				/* CONFIG_M5253 */
47
48	cpll = cpll & 0xfffffffe;	/* Set PLL bypass mode = 0 (PSTCLK = crystal) */
49	mbar2_writeLong(MCFSIM_PLLCR, cpll);	/* Set the PLL to bypass mode (PSTCLK = crystal) */
50	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* set the clock speed */
51	pllcr ^= 0x00000001;	/* Set pll bypass to 1 */
52	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* Start locking (pll bypass = 1) */
53	udelay(0x20);		/* Wait for a lock ... */
54#endif				/* #ifndef CFG_SYS_PLL_BYPASS */
55
56#endif				/* CONFIG_M5249 || CONFIG_M5253 */
57
58#if defined(CONFIG_M5275)
59	pll_t *pll = (pll_t *)(MMAP_PLL);
60
61	/* Setup PLL */
62	out_be32(&pll->syncr, 0x01080000);
63	while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
64		;
65	out_be32(&pll->syncr, 0x01000000);
66	while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
67		;
68#endif
69
70	gd->cpu_clk = CFG_SYS_CLK;
71#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
72    defined(CONFIG_M5271) || defined(CONFIG_M5275)
73	gd->bus_clk = gd->cpu_clk / 2;
74#else
75	gd->bus_clk = gd->cpu_clk;
76#endif
77
78#ifdef CONFIG_SYS_I2C_FSL
79	gd->arch.i2c1_clk = gd->bus_clk;
80#ifdef CONFIG_SYS_I2C2_FSL_OFFSET
81	gd->arch.i2c2_clk = gd->bus_clk;
82#endif
83#endif
84
85	return (0);
86}
87