1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@amd.com>
5 */
6
7#ifndef _ASM_ARCH_HARDWARE_H
8#define _ASM_ARCH_HARDWARE_H
9
10#ifndef __ASSEMBLY__
11#include <linux/bitops.h>
12#endif
13
14#define ZYNQMP_TCM_BASE_ADDR	0xFFE00000
15#define ZYNQMP_TCM_SIZE		0x40000
16
17#define ZYNQMP_CRL_APB_BASEADDR	0xFF5E0000
18#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000
19#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT	0
20#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT	8
21
22#define ZYNQMP_AMS_PS_SYSMON_BASEADDR      0XFFA50800
23#define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \
24							    + 0x00000114)
25#define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210
26
27#define ADMA_CH0_BASEADDR	0xFFA80000
28
29#define PS_MODE0	BIT(0)
30#define PS_MODE1	BIT(1)
31#define PS_MODE2	BIT(2)
32#define PS_MODE3	BIT(3)
33
34#define RESET_REASON_DEBUG_SYS	BIT(6)
35#define RESET_REASON_SOFT	BIT(5)
36#define RESET_REASON_SRST	BIT(4)
37#define RESET_REASON_PSONLY	BIT(3)
38#define RESET_REASON_PMU	BIT(2)
39#define RESET_REASON_INTERNAL	BIT(1)
40#define RESET_REASON_EXTERNAL	BIT(0)
41
42#define CRLAPB_DBG_LPD_CTRL_SETUP_CLK	0x01002002
43#define CRLAPB_RST_LPD_DBG_RESET	0
44
45struct crlapb_regs {
46	u32 reserved0[36];
47	u32 cpu_r5_ctrl; /* 0x90 */
48	u32 reserved1[7];
49	u32 dbg_lpd_ctrl; /* 0xB0 */
50	u32 reserved2[29];
51	u32 timestamp_ref_ctrl; /* 0x128 */
52	u32 reserved3[53];
53	u32 boot_mode; /* 0x200 */
54	u32 reserved4_0[7];
55	u32 reset_reason; /* 0x220 */
56	u32 reserved4_1[6];
57	u32 rst_lpd_top; /* 0x23C */
58	u32 rst_lpd_dbg; /* 0x240 */
59	u32 reserved5[3];
60	u32 boot_pin_ctrl; /* 0x250 */
61	u32 reserved6[21];
62};
63
64#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
65
66#define ZYNQMP_IOU_SCNTR_SECURE	0xFF260000
67#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN	0x1
68#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG	0x2
69
70struct iou_scntr_secure {
71	u32 counter_control_register;
72	u32 reserved0[7];
73	u32 base_frequency_id_register;
74};
75
76#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
77
78#define ZYNQMP_PS_VERSION	0xFFCA0044
79#define ZYNQMP_PS_VER_MASK	GENMASK(1, 0)
80
81/* Bootmode setting values */
82#define BOOT_MODES_MASK	0x0000000F
83#define QSPI_MODE_24BIT	0x00000001
84#define QSPI_MODE_32BIT	0x00000002
85#define SD_MODE		0x00000003 /* sd 0 */
86#define SD_MODE1	0x00000005 /* sd 1 */
87#define NAND_MODE	0x00000004
88#define EMMC_MODE	0x00000006
89#define USB_MODE	0x00000007
90#define SD1_LSHFT_MODE	0x0000000E /* SD1 Level shifter */
91#define JTAG_MODE	0x00000000
92#define BOOT_MODE_USE_ALT	0x100
93#define BOOT_MODE_ALT_SHIFT	12
94/* SW secondary boot modes 0xa - 0xd */
95#define SW_USBHOST_MODE	0x0000000A
96#define SW_SATA_MODE	0x0000000B
97
98#define ZYNQMP_IOU_SLCR_BASEADDR	0xFF180000
99
100struct iou_slcr_regs {
101	u32 mio_pin[78];
102	u32 reserved[442];
103};
104
105#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
106
107#define ZYNQMP_RPU_BASEADDR	0xFF9A0000
108
109struct rpu_regs {
110	u32 rpu_glbl_ctrl;
111	u32 reserved0[63];
112	u32 rpu0_cfg; /* 0x100 */
113	u32 reserved1[63];
114	u32 rpu1_cfg; /* 0x200 */
115};
116
117#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
118
119#define ZYNQMP_CRF_APB_BASEADDR	0xFD1A0000
120
121struct crfapb_regs {
122	u32 reserved0[65];
123	u32 rst_fpd_apu; /* 0x104 */
124	u32 reserved1;
125};
126
127#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
128
129#define ZYNQMP_APU_BASEADDR	0xFD5C0000
130
131struct apu_regs {
132	u32 reserved0[16];
133	u32 rvbar_addr0_l; /* 0x40 */
134	u32 rvbar_addr0_h; /* 0x44 */
135	u32 reserved1[20];
136};
137
138#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
139
140/* Board version value */
141#define ZYNQMP_CSU_BASEADDR		0xFFCA0000
142#define ZYNQMP_CSU_VERSION_SILICON	0x0
143#define ZYNQMP_CSU_VERSION_QEMU		0x3
144
145#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT		20
146
147#define ZYNQMP_SILICON_VER_MASK		0xF
148#define ZYNQMP_SILICON_VER_SHIFT	0
149
150#define CSU_JTAG_SEC_GATE_DISABLE	GENMASK(7, 0)
151#define CSU_JTAG_DAP_ENABLE_DEBUG	GENMASK(7, 0)
152#define CSU_JTAG_CHAIN_WR_SETUP		GENMASK(1, 0)
153#define CSU_PCAP_PROG_RELEASE_PL	BIT(0)
154
155#define ZYNQMP_CSU_STATUS_AUTHENTICATED	BIT(0)
156#define ZYNQMP_CSU_STATUS_ENCRYPTED	BIT(1)
157
158struct csu_regs {
159	u32 status;
160	u32 reserved0[3];
161	u32 multi_boot;
162	u32 reserved1[7];
163	u32 jtag_chain_status_wr;
164	u32 jtag_chain_status;
165	u32 jtag_sec;
166	u32 jtag_dap_cfg;
167	u32 idcode;
168	u32 version;
169	u32 reserved2[3054];
170	u32 pcap_prog;
171};
172
173#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
174
175#define ZYNQMP_PMU_BASEADDR	0xFFD80000
176
177struct pmu_regs {
178	u32 reserved0[16];
179	u32 gen_storage4; /* 0x40 */
180	u32 reserved1[1];
181	u32 gen_storage6; /* 0x48 */
182};
183
184#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
185
186#endif /* _ASM_ARCH_HARDWARE_H */
187