1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7/* Tegra30 Clock control functions */
8
9#include <common.h>
10#include <errno.h>
11#include <init.h>
12#include <log.h>
13#include <asm/io.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/tegra.h>
16#include <asm/arch-tegra/clk_rst.h>
17#include <asm/arch-tegra/timer.h>
18#include <div64.h>
19#include <fdtdec.h>
20#include <linux/delay.h>
21#include <linux/printk.h>
22
23#include <dt-bindings/clock/tegra30-car.h>
24
25/*
26 * Clock types that we can use as a source. The Tegra30 has muxes for the
27 * peripheral clocks, and in most cases there are four options for the clock
28 * source. This gives us a clock 'type' and exploits what commonality exists
29 * in the device.
30 *
31 * Letters are obvious, except for T which means CLK_M, and S which means the
32 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
33 * datasheet) and PLL_M are different things. The former is the basic
34 * clock supplied to the SOC from an external oscillator. The latter is the
35 * memory clock PLL.
36 *
37 * See definitions in clock_id in the header file.
38 */
39enum clock_type_id {
40	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
41	CLOCK_TYPE_MCPA,	/* and so on */
42	CLOCK_TYPE_MCPT,
43	CLOCK_TYPE_PCM,
44	CLOCK_TYPE_PCMT,
45	CLOCK_TYPE_PCMT16,
46	CLOCK_TYPE_PDCT,
47	CLOCK_TYPE_ACPT,
48	CLOCK_TYPE_ASPTE,
49	CLOCK_TYPE_PMDACD2T,
50	CLOCK_TYPE_PCST,
51
52	CLOCK_TYPE_COUNT,
53	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
54};
55
56enum {
57	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
58};
59
60/*
61 * Clock source mux for each clock type. This just converts our enum into
62 * a list of mux sources for use by the code.
63 *
64 * Note:
65 *  The extra column in each clock source array is used to store the mask
66 *  bits in its register for the source.
67 */
68#define CLK(x) CLOCK_ID_ ## x
69static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
70	{ CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),
71		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
72		MASK_BITS_31_30},
73	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),
74		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
75		MASK_BITS_31_30},
76	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
77		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
78		MASK_BITS_31_30},
79	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE),
80		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
81		MASK_BITS_31_30},
82	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
83		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
84		MASK_BITS_31_30},
85	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
86		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
87		MASK_BITS_31_30},
88	{ CLK(PERIPH),  CLK(DISPLAY),   CLK(CGENERAL),  CLK(OSC),
89		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
90		MASK_BITS_31_30},
91	{ CLK(AUDIO),   CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
92		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
93		MASK_BITS_31_30},
94	{ CLK(AUDIO),   CLK(SFROM32KHZ),	CLK(PERIPH),   CLK(OSC),
95		CLK(EPCI),      CLK(NONE),      CLK(NONE),      CLK(NONE),
96		MASK_BITS_31_29},
97	{ CLK(PERIPH),  CLK(MEMORY),    CLK(DISPLAY),   CLK(AUDIO),
98		CLK(CGENERAL),  CLK(DISPLAY2),  CLK(OSC),       CLK(NONE),
99		MASK_BITS_31_29},
100	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ), CLK(OSC),
101		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
102		MASK_BITS_31_28}
103};
104
105/*
106 * Clock type for each peripheral clock source. We put the name in each
107 * record just so it is easy to match things up
108 */
109#define TYPE(name, type) type
110static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
111	/* 0x00 */
112	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
113	TYPE(PERIPHC_I2S2,      CLOCK_TYPE_AXPT),
114	TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
115	TYPE(PERIPHC_SPDIF_IN,  CLOCK_TYPE_PCM),
116	TYPE(PERIPHC_PWM,       CLOCK_TYPE_PCST),  /* only PWM uses b29:28 */
117	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
118	TYPE(PERIPHC_SBC2,      CLOCK_TYPE_PCMT),
119	TYPE(PERIPHC_SBC3,      CLOCK_TYPE_PCMT),
120
121	/* 0x08 */
122	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
123	TYPE(PERIPHC_I2C1,      CLOCK_TYPE_PCMT16),
124	TYPE(PERIPHC_DVC_I2C,   CLOCK_TYPE_PCMT16),
125	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
126	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
127	TYPE(PERIPHC_SBC1,      CLOCK_TYPE_PCMT),
128	TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PMDACD2T),
129	TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PMDACD2T),
130
131	/* 0x10 */
132	TYPE(PERIPHC_CVE,       CLOCK_TYPE_PDCT),
133	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
134	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
135	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
136	TYPE(PERIPHC_SDMMC1,    CLOCK_TYPE_PCMT),
137	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PCMT),
138	TYPE(PERIPHC_G3D,	CLOCK_TYPE_MCPA),
139	TYPE(PERIPHC_G2D,	CLOCK_TYPE_MCPA),
140
141	/* 0x18 */
142	TYPE(PERIPHC_NDFLASH,	CLOCK_TYPE_PCMT),
143	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PCMT),
144	TYPE(PERIPHC_VFIR,      CLOCK_TYPE_PCMT),
145	TYPE(PERIPHC_EPP,       CLOCK_TYPE_MCPA),
146	TYPE(PERIPHC_MPE,       CLOCK_TYPE_MCPA),
147	TYPE(PERIPHC_MIPI,      CLOCK_TYPE_PCMT),       /* MIPI base-band HSI */
148	TYPE(PERIPHC_UART1,     CLOCK_TYPE_PCMT),
149	TYPE(PERIPHC_UART2,     CLOCK_TYPE_PCMT),
150
151	/* 0x20 */
152	TYPE(PERIPHC_HOST1X,    CLOCK_TYPE_MCPA),
153	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
154	TYPE(PERIPHC_TVO,       CLOCK_TYPE_PDCT),
155	TYPE(PERIPHC_HDMI,      CLOCK_TYPE_PMDACD2T),
156	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
157	TYPE(PERIPHC_TVDAC,     CLOCK_TYPE_PDCT),
158	TYPE(PERIPHC_I2C2,      CLOCK_TYPE_PCMT16),
159	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),
160
161	/* 0x28 */
162	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PCMT),
163	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
164	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
165	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
166	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
167	TYPE(PERIPHC_SBC4,      CLOCK_TYPE_PCMT),
168	TYPE(PERIPHC_I2C3,      CLOCK_TYPE_PCMT16),
169	TYPE(PERIPHC_SDMMC3,    CLOCK_TYPE_PCMT),
170
171	/* 0x30 */
172	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PCMT),
173	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PCMT),
174	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PCMT),
175	TYPE(PERIPHC_OWR,       CLOCK_TYPE_PCMT),
176	TYPE(PERIPHC_NOR,       CLOCK_TYPE_PCMT),
177	TYPE(PERIPHC_CSITE,     CLOCK_TYPE_PCMT),
178	TYPE(PERIPHC_I2S0,      CLOCK_TYPE_AXPT),
179	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
180
181	/* 0x38h */	     /* Jumps to reg offset 0x3B0h - new for T30 */
182	TYPE(PERIPHC_G3D2,      CLOCK_TYPE_MCPA),
183	TYPE(PERIPHC_MSELECT,   CLOCK_TYPE_PCMT),
184	TYPE(PERIPHC_TSENSOR,   CLOCK_TYPE_PCST),       /* s/b PCTS */
185	TYPE(PERIPHC_I2S3,      CLOCK_TYPE_AXPT),
186	TYPE(PERIPHC_I2S4,      CLOCK_TYPE_AXPT),
187	TYPE(PERIPHC_I2C4,      CLOCK_TYPE_PCMT16),
188	TYPE(PERIPHC_SBC5,      CLOCK_TYPE_PCMT),
189	TYPE(PERIPHC_SBC6,      CLOCK_TYPE_PCMT),
190
191	/* 0x40 */
192	TYPE(PERIPHC_AUDIO,     CLOCK_TYPE_ACPT),
193	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
194	TYPE(PERIPHC_DAM0,      CLOCK_TYPE_ACPT),
195	TYPE(PERIPHC_DAM1,      CLOCK_TYPE_ACPT),
196	TYPE(PERIPHC_DAM2,      CLOCK_TYPE_ACPT),
197	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
198	TYPE(PERIPHC_ACTMON,    CLOCK_TYPE_PCST),       /* MASK 31:30 */
199	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
200
201	/* 0x48 */
202	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
203	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
204	TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
205	TYPE(PERIPHC_I2CSLOW,   CLOCK_TYPE_PCST),       /* MASK 31:30 */
206	TYPE(PERIPHC_SYS,       CLOCK_TYPE_NONE),
207	TYPE(PERIPHC_SPEEDO,    CLOCK_TYPE_PCMT),
208	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
209	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
210
211	/* 0x50 */
212	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
213	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
214	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
215	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
216	TYPE(PERIPHC_SATAOOB,   CLOCK_TYPE_PCMT),       /* offset 0x420h */
217	TYPE(PERIPHC_SATA,      CLOCK_TYPE_PCMT),
218	TYPE(PERIPHC_HDA,       CLOCK_TYPE_PCMT),
219};
220
221/*
222 * This array translates a periph_id to a periphc_internal_id
223 *
224 * Not present/matched up:
225 *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
226 *	SPDIF - which is both 0x08 and 0x0c
227 *
228 */
229#define NONE(name) (-1)
230#define OFFSET(name, value) PERIPHC_ ## name
231static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
232	/* Low word: 31:0 */
233	NONE(CPU),
234	NONE(COP),
235	NONE(TRIGSYS),
236	NONE(RESERVED3),
237	NONE(RESERVED4),
238	NONE(TMR),
239	PERIPHC_UART1,
240	PERIPHC_UART2,  /* and vfir 0x68 */
241
242	/* 8 */
243	NONE(GPIO),
244	PERIPHC_SDMMC2,
245	NONE(SPDIF),	    /* 0x08 and 0x0c, unclear which to use */
246	PERIPHC_I2S1,
247	PERIPHC_I2C1,
248	PERIPHC_NDFLASH,
249	PERIPHC_SDMMC1,
250	PERIPHC_SDMMC4,
251
252	/* 16 */
253	NONE(RESERVED16),
254	PERIPHC_PWM,
255	PERIPHC_I2S2,
256	PERIPHC_EPP,
257	PERIPHC_VI,
258	PERIPHC_G2D,
259	NONE(USBD),
260	NONE(ISP),
261
262	/* 24 */
263	PERIPHC_G3D,
264	NONE(RESERVED25),
265	PERIPHC_DISP2,
266	PERIPHC_DISP1,
267	PERIPHC_HOST1X,
268	NONE(VCP),
269	PERIPHC_I2S0,
270	NONE(CACHE2),
271
272	/* Middle word: 63:32 */
273	NONE(MEM),
274	NONE(AHBDMA),
275	NONE(APBDMA),
276	NONE(RESERVED35),
277	NONE(RESERVED36),
278	NONE(STAT_MON),
279	NONE(RESERVED38),
280	NONE(RESERVED39),
281
282	/* 40 */
283	NONE(KFUSE),
284	PERIPHC_SBC1,
285	PERIPHC_NOR,
286	NONE(RESERVED43),
287	PERIPHC_SBC2,
288	NONE(RESERVED45),
289	PERIPHC_SBC3,
290	PERIPHC_DVC_I2C,
291
292	/* 48 */
293	NONE(DSI),
294	PERIPHC_TVO,    /* also CVE 0x40 */
295	PERIPHC_MIPI,
296	PERIPHC_HDMI,
297	NONE(CSI),
298	PERIPHC_TVDAC,
299	PERIPHC_I2C2,
300	PERIPHC_UART3,
301
302	/* 56 */
303	NONE(RESERVED56),
304	PERIPHC_EMC,
305	NONE(USB2),
306	NONE(USB3),
307	PERIPHC_MPE,
308	PERIPHC_VDE,
309	NONE(BSEA),
310	NONE(BSEV),
311
312	/* Upper word 95:64 */
313	PERIPHC_SPEEDO,
314	PERIPHC_UART4,
315	PERIPHC_UART5,
316	PERIPHC_I2C3,
317	PERIPHC_SBC4,
318	PERIPHC_SDMMC3,
319	NONE(PCIE),
320	PERIPHC_OWR,
321
322	/* 72 */
323	NONE(AFI),
324	PERIPHC_CSITE,
325	NONE(PCIEXCLK),
326	NONE(AVPUCQ),
327	NONE(RESERVED76),
328	NONE(RESERVED77),
329	NONE(RESERVED78),
330	NONE(DTV),
331
332	/* 80 */
333	PERIPHC_NANDSPEED,
334	PERIPHC_I2CSLOW,
335	NONE(DSIB),
336	NONE(RESERVED83),
337	NONE(IRAMA),
338	NONE(IRAMB),
339	NONE(IRAMC),
340	NONE(IRAMD),
341
342	/* 88 */
343	NONE(CRAM2),
344	NONE(RESERVED89),
345	NONE(MDOUBLER),
346	NONE(RESERVED91),
347	NONE(SUSOUT),
348	NONE(RESERVED93),
349	NONE(RESERVED94),
350	NONE(RESERVED95),
351
352	/* V word: 31:0 */
353	NONE(CPUG),
354	NONE(CPULP),
355	PERIPHC_G3D2,
356	PERIPHC_MSELECT,
357	PERIPHC_TSENSOR,
358	PERIPHC_I2S3,
359	PERIPHC_I2S4,
360	PERIPHC_I2C4,
361
362	/* 08 */
363	PERIPHC_SBC5,
364	PERIPHC_SBC6,
365	PERIPHC_AUDIO,
366	NONE(APBIF),
367	PERIPHC_DAM0,
368	PERIPHC_DAM1,
369	PERIPHC_DAM2,
370	PERIPHC_HDA2CODEC2X,
371
372	/* 16 */
373	NONE(ATOMICS),
374	NONE(RESERVED17),
375	NONE(RESERVED18),
376	NONE(RESERVED19),
377	NONE(RESERVED20),
378	NONE(RESERVED21),
379	NONE(RESERVED22),
380	PERIPHC_ACTMON,
381
382	/* 24 */
383	PERIPHC_EXTPERIPH1,
384	PERIPHC_EXTPERIPH2,
385	PERIPHC_EXTPERIPH3,
386	NONE(RESERVED27),
387	PERIPHC_SATA,
388	PERIPHC_HDA,
389	NONE(RESERVED30),
390	NONE(RESERVED31),
391
392	/* W word: 31:0 */
393	NONE(HDA2HDMICODEC),
394	NONE(SATACOLD),
395	NONE(RESERVED0_PCIERX0),
396	NONE(RESERVED1_PCIERX1),
397	NONE(RESERVED2_PCIERX2),
398	NONE(RESERVED3_PCIERX3),
399	NONE(RESERVED4_PCIERX4),
400	NONE(RESERVED5_PCIERX5),
401
402	/* 40 */
403	NONE(CEC),
404	NONE(RESERVED6_PCIE2),
405	NONE(RESERVED7_EMC),
406	NONE(RESERVED8_HDMI),
407	NONE(RESERVED9_SATA),
408	NONE(RESERVED10_MIPI),
409	NONE(EX_RESERVED46),
410	NONE(EX_RESERVED47),
411};
412
413/*
414 * PLL divider shift/mask tables for all PLL IDs.
415 */
416struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
417	/*
418	 * T30: some deviations from T2x.
419	 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
420	 *       If lock_ena or lock_det are >31, they're not used in that PLL.
421	 */
422
423	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF,  .p_shift = 20, .p_mask = 0x0F,
424	  .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 },	/* PLLC */
425	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF,  .p_shift = 0,  .p_mask = 0,
426	  .lock_ena = 0,  .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },	/* PLLM */
427	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
428	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLP */
429	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
430	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLA */
431	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
432	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLU */
433	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
434	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLD */
435	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 20, .p_mask = 0x0F,
436	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 },	/* PLLX */
437	{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 0,  .p_mask = 0,
438	  .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },	/* PLLE */
439	{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
440	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLS (RESERVED) */
441	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
442	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF },	/* PLLD2 */
443};
444
445/*
446 * Get the oscillator frequency, from the corresponding hardware configuration
447 * field. Note that T30+ supports 3 new higher freqs.
448 */
449enum clock_osc_freq clock_get_osc_freq(void)
450{
451	struct clk_rst_ctlr *clkrst =
452			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
453	u32 reg;
454
455	reg = readl(&clkrst->crc_osc_ctrl);
456	return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
457}
458
459/* Returns a pointer to the clock source register for a peripheral */
460u32 *get_periph_source_reg(enum periph_id periph_id)
461{
462	struct clk_rst_ctlr *clkrst =
463		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
464	enum periphc_internal_id internal_id;
465
466	/* Coresight is a special case */
467	if (periph_id == PERIPH_ID_CSI)
468		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
469
470	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
471	internal_id = periph_id_to_internal_id[periph_id];
472	assert(internal_id != -1);
473	if (internal_id >= PERIPHC_VW_FIRST) {
474		internal_id -= PERIPHC_VW_FIRST;
475		return &clkrst->crc_clk_src_vw[internal_id];
476	} else
477		return &clkrst->crc_clk_src[internal_id];
478}
479
480int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
481			  int *divider_bits, int *type)
482{
483	enum periphc_internal_id internal_id;
484
485	if (!clock_periph_id_isvalid(periph_id))
486		return -1;
487
488	internal_id = periph_id_to_internal_id[periph_id];
489	if (!periphc_internal_id_isvalid(internal_id))
490		return -1;
491
492	*type = clock_periph_type[internal_id];
493	if (!clock_type_id_isvalid(*type))
494		return -1;
495
496	*mux_bits = clock_source[*type][CLOCK_MAX_MUX];
497
498	if (*type == CLOCK_TYPE_PCMT16)
499		*divider_bits = 16;
500	else
501		*divider_bits = 8;
502
503	return 0;
504}
505
506enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
507{
508	enum periphc_internal_id internal_id;
509	int type;
510
511	if (!clock_periph_id_isvalid(periph_id))
512		return CLOCK_ID_NONE;
513
514	internal_id = periph_id_to_internal_id[periph_id];
515	if (!periphc_internal_id_isvalid(internal_id))
516		return CLOCK_ID_NONE;
517
518	type = clock_periph_type[internal_id];
519	if (!clock_type_id_isvalid(type))
520		return CLOCK_ID_NONE;
521
522	return clock_source[type][source];
523}
524
525/**
526 * Given a peripheral ID and the required source clock, this returns which
527 * value should be programmed into the source mux for that peripheral.
528 *
529 * There is special code here to handle the one source type with 5 sources.
530 *
531 * @param periph_id	peripheral to start
532 * @param source	PLL id of required parent clock
533 * @param mux_bits	Set to number of bits in mux register: 2 or 4
534 * @param divider_bits  Set to number of divider bits (8 or 16)
535 * Return: mux value (0-4, or -1 if not found)
536 */
537int get_periph_clock_source(enum periph_id periph_id,
538	enum clock_id parent, int *mux_bits, int *divider_bits)
539{
540	enum clock_type_id type;
541	int mux, err;
542
543	err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
544	assert(!err);
545
546	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
547		if (clock_source[type][mux] == parent)
548			return mux;
549
550	/* if we get here, either us or the caller has made a mistake */
551	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
552		parent);
553	return -1;
554}
555
556void clock_set_enable(enum periph_id periph_id, int enable)
557{
558	struct clk_rst_ctlr *clkrst =
559			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
560	u32 *clk;
561	u32 reg;
562
563	/* Enable/disable the clock to this peripheral */
564	assert(clock_periph_id_isvalid(periph_id));
565	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
566		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
567	else
568		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
569	reg = readl(clk);
570	if (enable)
571		reg |= PERIPH_MASK(periph_id);
572	else
573		reg &= ~PERIPH_MASK(periph_id);
574	writel(reg, clk);
575}
576
577void reset_set_enable(enum periph_id periph_id, int enable)
578{
579	struct clk_rst_ctlr *clkrst =
580			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
581	u32 *reset;
582	u32 reg;
583
584	/* Enable/disable reset to the peripheral */
585	assert(clock_periph_id_isvalid(periph_id));
586	if (periph_id < PERIPH_ID_VW_FIRST)
587		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
588	else
589		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
590	reg = readl(reset);
591	if (enable)
592		reg |= PERIPH_MASK(periph_id);
593	else
594		reg &= ~PERIPH_MASK(periph_id);
595	writel(reg, reset);
596}
597
598#if CONFIG_IS_ENABLED(OF_CONTROL)
599/*
600 * Convert a device tree clock ID to our peripheral ID. They are mostly
601 * the same but we are very cautious so we check that a valid clock ID is
602 * provided.
603 *
604 * @param clk_id	Clock ID according to tegra30 device tree binding
605 * Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
606 */
607enum periph_id clk_id_to_periph_id(int clk_id)
608{
609	if (clk_id > PERIPH_ID_COUNT)
610		return PERIPH_ID_NONE;
611
612	switch (clk_id) {
613	case PERIPH_ID_RESERVED3:
614	case PERIPH_ID_RESERVED4:
615	case PERIPH_ID_RESERVED16:
616	case PERIPH_ID_RESERVED24:
617	case PERIPH_ID_RESERVED35:
618	case PERIPH_ID_RESERVED43:
619	case PERIPH_ID_RESERVED45:
620	case PERIPH_ID_RESERVED56:
621	case PERIPH_ID_PCIEXCLK:
622	case PERIPH_ID_RESERVED76:
623	case PERIPH_ID_RESERVED77:
624	case PERIPH_ID_RESERVED78:
625	case PERIPH_ID_RESERVED83:
626	case PERIPH_ID_RESERVED89:
627	case PERIPH_ID_RESERVED91:
628	case PERIPH_ID_RESERVED93:
629	case PERIPH_ID_RESERVED94:
630	case PERIPH_ID_RESERVED95:
631		return PERIPH_ID_NONE;
632	default:
633		return clk_id;
634	}
635}
636
637/*
638 * Convert a device tree clock ID to our PLL ID.
639 *
640 * @param clk_id	Clock ID according to tegra30 device tree binding
641 * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
642 */
643enum clock_id clk_id_to_pll_id(int clk_id)
644{
645	switch (clk_id) {
646	case TEGRA30_CLK_PLL_C:
647		return CLOCK_ID_CGENERAL;
648	case TEGRA30_CLK_PLL_M:
649		return CLOCK_ID_MEMORY;
650	case TEGRA30_CLK_PLL_P:
651		return CLOCK_ID_PERIPH;
652	case TEGRA30_CLK_PLL_A:
653		return CLOCK_ID_AUDIO;
654	case TEGRA30_CLK_PLL_U:
655		return CLOCK_ID_USB;
656	case TEGRA30_CLK_PLL_D:
657	case TEGRA30_CLK_PLL_D_OUT0:
658		return CLOCK_ID_DISPLAY;
659	case TEGRA30_CLK_PLL_D2:
660	case TEGRA30_CLK_PLL_D2_OUT0:
661		return CLOCK_ID_DISPLAY2;
662	case TEGRA30_CLK_PLL_X:
663		return CLOCK_ID_XCPU;
664	case TEGRA30_CLK_PLL_E:
665		return CLOCK_ID_EPCI;
666	case TEGRA30_CLK_CLK_32K:
667		return CLOCK_ID_32KHZ;
668	case TEGRA30_CLK_CLK_M:
669		return CLOCK_ID_CLK_M;
670	default:
671		return CLOCK_ID_NONE;
672	}
673}
674#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
675
676void clock_early_init(void)
677{
678	struct clk_rst_ctlr *clkrst =
679		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
680	struct clk_pll_info *pllinfo;
681	u32 data;
682
683	tegra30_set_up_pllp();
684
685	/*
686	 * PLLD output frequency set to 925Mhz
687	 */
688	switch (clock_get_osc_freq()) {
689	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
690	case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
691		clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
692		break;
693
694	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
695		clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
696		break;
697
698	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
699	case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
700		clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
701		break;
702
703	case CLOCK_OSC_FREQ_19_2:
704	case CLOCK_OSC_FREQ_38_4:
705	default:
706		/*
707		 * These are not supported. It is too early to print a
708		 * message and the UART likely won't work anyway due to the
709		 * oscillator being wrong.
710		 */
711		break;
712	}
713
714	/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
715	pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
716	data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
717	data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
718	writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
719	udelay(2);
720}
721
722void arch_timer_init(void)
723{
724}
725
726#define PMC_SATA_PWRGT 0x1ac
727#define  PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
728#define  PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
729
730#define PLLE_SS_CNTL 0x68
731#define  PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
732#define  PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
733#define  PLLE_SS_CNTL_SSCBYP (1 << 12)
734#define  PLLE_SS_CNTL_INTERP_RESET (1 << 11)
735#define  PLLE_SS_CNTL_BYPASS_SS (1 << 10)
736#define  PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
737
738#define PLLE_BASE 0x0e8
739#define  PLLE_BASE_ENABLE_CML (1 << 31)
740#define  PLLE_BASE_ENABLE (1 << 30)
741#define  PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
742#define  PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
743#define  PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
744#define  PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
745
746#define PLLE_MISC 0x0ec
747#define  PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
748#define  PLLE_MISC_PLL_READY (1 << 15)
749#define  PLLE_MISC_LOCK (1 << 11)
750#define  PLLE_MISC_LOCK_ENABLE (1 << 9)
751#define  PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
752
753static int tegra_plle_train(void)
754{
755	unsigned int timeout = 2000;
756	unsigned long value;
757
758	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
759	value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
760	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
761
762	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
763	value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
764	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
765
766	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
767	value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
768	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
769
770	do {
771		value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
772		if (value & PLLE_MISC_PLL_READY)
773			break;
774
775		udelay(100);
776	} while (--timeout);
777
778	if (timeout == 0) {
779		pr_err("timeout waiting for PLLE to become ready");
780		return -ETIMEDOUT;
781	}
782
783	return 0;
784}
785
786int tegra_plle_enable(void)
787{
788	unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
789	u32 value;
790	int err;
791
792	/* disable PLLE clock */
793	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
794	value &= ~PLLE_BASE_ENABLE_CML;
795	value &= ~PLLE_BASE_ENABLE;
796	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
797
798	/* clear lock enable and setup field */
799	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
800	value &= ~PLLE_MISC_LOCK_ENABLE;
801	value &= ~PLLE_MISC_SETUP_BASE(0xffff);
802	value &= ~PLLE_MISC_SETUP_EXT(0x3);
803	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
804
805	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
806	if ((value & PLLE_MISC_PLL_READY) == 0) {
807		err = tegra_plle_train();
808		if (err < 0) {
809			pr_err("failed to train PLLE: %d", err);
810			return err;
811		}
812	}
813
814	/* configure PLLE */
815	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
816
817	value &= ~PLLE_BASE_PLDIV_CML(0x0f);
818	value |= PLLE_BASE_PLDIV_CML(cpcon);
819
820	value &= ~PLLE_BASE_PLDIV(0x3f);
821	value |= PLLE_BASE_PLDIV(p);
822
823	value &= ~PLLE_BASE_NDIV(0xff);
824	value |= PLLE_BASE_NDIV(n);
825
826	value &= ~PLLE_BASE_MDIV(0xff);
827	value |= PLLE_BASE_MDIV(m);
828
829	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
830
831	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
832	value |= PLLE_MISC_SETUP_BASE(0x7);
833	value |= PLLE_MISC_LOCK_ENABLE;
834	value |= PLLE_MISC_SETUP_EXT(0);
835	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
836
837	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
838	value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
839		 PLLE_SS_CNTL_BYPASS_SS;
840	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
841
842	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
843	value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
844	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
845
846	do {
847		value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
848		if (value & PLLE_MISC_LOCK)
849			break;
850
851		udelay(2);
852	} while (--timeout);
853
854	if (timeout == 0) {
855		pr_err("timeout waiting for PLLE to lock");
856		return -ETIMEDOUT;
857	}
858
859	udelay(50);
860
861	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
862	value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
863	value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
864
865	value &= ~PLLE_SS_CNTL_SSCINC(0xff);
866	value |= PLLE_SS_CNTL_SSCINC(0x01);
867
868	value &= ~PLLE_SS_CNTL_SSCBYP;
869	value &= ~PLLE_SS_CNTL_INTERP_RESET;
870	value &= ~PLLE_SS_CNTL_BYPASS_SS;
871
872	value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
873	value |= PLLE_SS_CNTL_SSCMAX(0x24);
874	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
875
876	return 0;
877}
878
879struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
880{
881	struct clk_rst_ctlr *clkrst =
882			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
883
884	switch (clkid) {
885	case CLOCK_ID_XCPU:
886	case CLOCK_ID_EPCI:
887	case CLOCK_ID_SFROM32KHZ:
888		return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
889	case CLOCK_ID_DISPLAY2:
890		return &clkrst->plld2;
891	default:
892		return NULL;
893	}
894}
895
896struct periph_clk_init periph_clk_init_table[] = {
897	{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
898	{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
899	{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
900	{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
901	{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
902	{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
903	{ PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL },
904	{ PERIPH_ID_DISP1, CLOCK_ID_PERIPH },
905	{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
906	{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
907	{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
908	{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
909	{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
910	{ PERIPH_ID_PWM, CLOCK_ID_PERIPH },
911	{ PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
912	{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
913	{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
914	{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
915	{ PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
916	{ -1, },
917};
918