1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt 7 8#include <common.h> 9#include <errno.h> 10#include <log.h> 11#include <asm/global_data.h> 12#include <dm/of_access.h> 13#include <dm/ofnode.h> 14#include <linux/delay.h> 15#include <linux/printk.h> 16 17#include "../xusb-padctl-common.h" 18 19#include <asm/arch/clock.h> 20 21#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 22 23DECLARE_GLOBAL_DATA_PTR; 24 25enum tegra210_function { 26 TEGRA210_FUNC_SNPS, 27 TEGRA210_FUNC_XUSB, 28 TEGRA210_FUNC_UART, 29 TEGRA210_FUNC_PCIE_X1, 30 TEGRA210_FUNC_PCIE_X4, 31 TEGRA210_FUNC_USB3, 32 TEGRA210_FUNC_SATA, 33 TEGRA210_FUNC_RSVD, 34}; 35 36static const char *const tegra210_functions[] = { 37 "snps", 38 "xusb", 39 "uart", 40 "pcie-x1", 41 "pcie-x4", 42 "usb3", 43 "sata", 44 "rsvd", 45}; 46 47static const unsigned int tegra210_otg_functions[] = { 48 TEGRA210_FUNC_SNPS, 49 TEGRA210_FUNC_XUSB, 50 TEGRA210_FUNC_UART, 51 TEGRA210_FUNC_RSVD, 52}; 53 54static const unsigned int tegra210_usb_functions[] = { 55 TEGRA210_FUNC_SNPS, 56 TEGRA210_FUNC_XUSB, 57}; 58 59static const unsigned int tegra210_pci_functions[] = { 60 TEGRA210_FUNC_PCIE_X1, 61 TEGRA210_FUNC_USB3, 62 TEGRA210_FUNC_SATA, 63 TEGRA210_FUNC_PCIE_X4, 64}; 65 66#define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ 67 { \ 68 .name = _name, \ 69 .offset = _offset, \ 70 .shift = _shift, \ 71 .mask = _mask, \ 72 .iddq = _iddq, \ 73 .num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions), \ 74 .funcs = tegra210_##_funcs##_functions, \ 75 } 76 77static const struct tegra_xusb_padctl_lane tegra210_lanes[] = { 78 TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg), 79 TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg), 80 TEGRA210_LANE("otg-2", 0x004, 4, 0x3, 0, otg), 81 TEGRA210_LANE("otg-3", 0x004, 6, 0x3, 0, otg), 82 TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg), 83 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, 0, usb), 84 TEGRA210_LANE("hsic-1", 0x004, 15, 0x1, 0, usb), 85 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, 1, pci), 86 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, 2, pci), 87 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, 3, pci), 88 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, 4, pci), 89 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, 5, pci), 90 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, 6, pci), 91 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, 7, pci), 92 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, 8, pci), 93}; 94 95#define XUSB_PADCTL_ELPG_PROGRAM 0x024 96#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31) 97#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30) 98#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29) 99 100static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) 101{ 102 u32 value; 103 104 if (padctl->enable++ > 0) 105 return 0; 106 107 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 108 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 109 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 110 111 udelay(100); 112 113 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 114 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 115 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 116 117 udelay(100); 118 119 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 120 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 121 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 122 123 return 0; 124} 125 126static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) 127{ 128 u32 value; 129 130 if (padctl->enable == 0) { 131 pr_err("unbalanced enable/disable"); 132 return 0; 133 } 134 135 if (--padctl->enable > 0) 136 return 0; 137 138 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 139 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 140 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 141 142 udelay(100); 143 144 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 145 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 146 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 147 148 udelay(100); 149 150 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 151 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 152 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 153 154 return 0; 155} 156 157static int phy_prepare(struct tegra_xusb_phy *phy) 158{ 159 int err; 160 161 err = tegra_xusb_padctl_enable(phy->padctl); 162 if (err < 0) 163 return err; 164 165 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0); 166 167 return 0; 168} 169 170static int phy_unprepare(struct tegra_xusb_phy *phy) 171{ 172 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1); 173 174 return tegra_xusb_padctl_disable(phy->padctl); 175} 176 177#define XUSB_PADCTL_USB3_PAD_MUX 0x28 178#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0) 179#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1) 180#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2) 181#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3) 182#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4) 183#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5) 184#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6) 185#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7) 186#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8) 187 188#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 189#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20) 190#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20) 191#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16) 192#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15) 193#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4) 194#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3) 195#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1) 196#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1) 197#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0) 198 199#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364 200#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4) 201#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4) 202#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2) 203#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1) 204#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0) 205 206#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c 207#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15) 208#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12) 209#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12) 210#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8) 211#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4) 212 213#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370 214#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16) 215#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16) 216 217#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c 218#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31) 219#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15) 220#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13) 221#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12) 222 223#define CLK_RST_XUSBIO_PLL_CFG0 0x51c 224#define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24) 225#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13) 226#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6) 227#define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2) 228#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) 229 230static int pcie_phy_enable(struct tegra_xusb_phy *phy) 231{ 232 struct tegra_xusb_padctl *padctl = phy->padctl; 233 unsigned long start; 234 u32 value; 235 236 debug("> %s(phy=%p)\n", __func__, phy); 237 238 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 239 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK; 240 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136); 241 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 242 243 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); 244 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK; 245 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a); 246 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); 247 248 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 249 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; 250 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 251 252 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 253 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; 254 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 255 256 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 257 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; 258 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 259 260 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 261 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK; 262 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK; 263 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2); 264 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN; 265 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 266 267 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 268 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK; 269 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK; 270 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25); 271 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 272 273 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 274 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; 275 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 276 277 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 278 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; 279 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 280 281 udelay(1); 282 283 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 284 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN; 285 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 286 287 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 288 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN; 289 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 290 291 debug(" waiting for calibration\n"); 292 293 start = get_timer(0); 294 295 while (get_timer(start) < 250) { 296 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 297 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) 298 break; 299 } 300 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) { 301 debug(" timeout\n"); 302 return -ETIMEDOUT; 303 } 304 debug(" done\n"); 305 306 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 307 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN; 308 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 309 310 debug(" waiting for calibration to stop\n"); 311 312 start = get_timer(0); 313 314 while (get_timer(start) < 250) { 315 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 316 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0) 317 break; 318 } 319 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) { 320 debug(" timeout\n"); 321 return -ETIMEDOUT; 322 } 323 debug(" done\n"); 324 325 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 326 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; 327 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 328 329 debug(" waiting for PLL to lock...\n"); 330 start = get_timer(0); 331 332 while (get_timer(start) < 250) { 333 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 334 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS) 335 break; 336 } 337 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) { 338 debug(" timeout\n"); 339 return -ETIMEDOUT; 340 } 341 debug(" done\n"); 342 343 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 344 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; 345 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN; 346 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 347 348 debug(" waiting for register calibration...\n"); 349 start = get_timer(0); 350 351 while (get_timer(start) < 250) { 352 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 353 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) 354 break; 355 } 356 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) { 357 debug(" timeout\n"); 358 return -ETIMEDOUT; 359 } 360 debug(" done\n"); 361 362 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 363 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN; 364 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 365 366 debug(" waiting for register calibration to stop...\n"); 367 start = get_timer(0); 368 369 while (get_timer(start) < 250) { 370 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 371 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0) 372 break; 373 } 374 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) { 375 debug(" timeout\n"); 376 return -ETIMEDOUT; 377 } 378 debug(" done\n"); 379 380 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 381 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; 382 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 383 384 debug("< %s()\n", __func__); 385 return 0; 386} 387 388static int pcie_phy_disable(struct tegra_xusb_phy *phy) 389{ 390 return 0; 391} 392 393static const struct tegra_xusb_phy_ops pcie_phy_ops = { 394 .prepare = phy_prepare, 395 .enable = pcie_phy_enable, 396 .disable = pcie_phy_disable, 397 .unprepare = phy_unprepare, 398}; 399 400static struct tegra_xusb_phy tegra210_phys[] = { 401 { 402 .type = TEGRA_XUSB_PADCTL_PCIE, 403 .ops = &pcie_phy_ops, 404 .padctl = &padctl, 405 }, 406}; 407 408static const struct tegra_xusb_padctl_soc tegra210_socdata = { 409 .lanes = tegra210_lanes, 410 .num_lanes = ARRAY_SIZE(tegra210_lanes), 411 .functions = tegra210_functions, 412 .num_functions = ARRAY_SIZE(tegra210_functions), 413 .phys = tegra210_phys, 414 .num_phys = ARRAY_SIZE(tegra210_phys), 415}; 416 417void tegra_xusb_padctl_init(void) 418{ 419 ofnode nodes[1]; 420 int count = 0; 421 int ret; 422 423 debug("%s: start\n", __func__); 424 if (of_live_active()) { 425 struct device_node *np = of_find_compatible_node(NULL, NULL, 426 "nvidia,tegra210-xusb-padctl"); 427 428 debug("np=%p\n", np); 429 if (np) { 430 nodes[0] = np_to_ofnode(np); 431 count = 1; 432 } 433 } else { 434 int node_offsets[1]; 435 int i; 436 437 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl", 438 COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, 439 node_offsets, ARRAY_SIZE(node_offsets)); 440 for (i = 0; i < count; i++) 441 nodes[i] = offset_to_ofnode(node_offsets[i]); 442 } 443 444 ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata); 445 debug("%s: done, ret=%d\n", __func__, ret); 446} 447 448void tegra_xusb_padctl_exit(void) 449{ 450 u32 value; 451 452 debug("> %s\n", __func__); 453 454 value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX); 455 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE; 456 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0; 457 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1; 458 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2; 459 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3; 460 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4; 461 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5; 462 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6; 463 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0; 464 padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX); 465 466 value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 467 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; 468 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; 469 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3); 470 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; 471 padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 472 473 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1); 474 while (padctl.enable) 475 tegra_xusb_padctl_disable(&padctl); 476 477 debug("< %s()\n", __func__); 478} 479