126213Swpaul/* SPDX-License-Identifier: GPL-2.0+ */ 226213Swpaul/* 326213Swpaul * Specialty padding for the Altera SoCFPGA preloader image 426213Swpaul */ 526213Swpaul 626213Swpaul#ifndef __BOOT0_H 726213Swpaul#define __BOOT0_H 826213Swpaul 926213Swpaul_start: 1026213Swpaul ARM_VECTORS 1126213Swpaul 1226213Swpaul#ifdef CONFIG_SPL_BUILD 1326213Swpaul .balignl 64,0xf33db33f; 1426213Swpaul 1526213Swpaul .word 0x1337c0d3; /* SoCFPGA preloader validation word */ 1626213Swpaul .word 0xc01df00d; /* Version, flags, length */ 1726213Swpaul .word 0xcafec0d3; /* Checksum, zero-pad */ 1826213Swpaul nop; 1926213Swpaul 2026213Swpaul b reset; /* SoCFPGA Gen5 jumps here */ 2126213Swpaul b reset; /* SoCFPGA Gen10 trampoline */ 2226213Swpaul nop; 2326213Swpaul nop; 2426213Swpaul#endif 2526213Swpaul 2626213Swpaul#endif /* __BOOT0_H */ 2726213Swpaul