1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * board.c 4 * 5 * Common board functions for AM33XX based boards 6 * 7 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ 8 */ 9 10#include <common.h> 11#include <dm.h> 12#include <debug_uart.h> 13#include <errno.h> 14#include <event.h> 15#include <init.h> 16#include <net.h> 17#include <ns16550.h> 18#include <omap3_spi.h> 19#include <spl.h> 20#include <asm/arch/cpu.h> 21#include <asm/arch/hardware.h> 22#include <asm/arch/omap.h> 23#include <asm/arch/ddr_defs.h> 24#include <asm/arch/clock.h> 25#include <asm/arch/gpio.h> 26#include <asm/arch/i2c.h> 27#if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN) 28#include <asm/arch/mem-guardian.h> 29#else 30#include <asm/arch/mem.h> 31#endif 32#include <asm/arch/mmc_host_def.h> 33#include <asm/arch/sys_proto.h> 34#include <asm/global_data.h> 35#include <asm/io.h> 36#include <asm/emif.h> 37#include <asm/gpio.h> 38#include <asm/omap_common.h> 39#include <i2c.h> 40#include <miiphy.h> 41#include <cpsw.h> 42#include <linux/delay.h> 43#include <linux/errno.h> 44#include <linux/compiler.h> 45#include <linux/printk.h> 46#include <linux/usb/ch9.h> 47#include <linux/usb/gadget.h> 48#include <linux/usb/musb.h> 49#include <asm/omap_musb.h> 50#include <asm/davinci_rtc.h> 51 52#define AM43XX_EMIF_BASE 0x4C000000 53#define AM43XX_SDRAM_CONFIG_OFFSET 0x8 54#define AM43XX_SDRAM_TYPE_MASK 0xE0000000 55#define AM43XX_SDRAM_TYPE_SHIFT 29 56#define AM43XX_SDRAM_TYPE_DDR3 3 57#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC 58#define AM43XX_RDWRLVLFULL_START 0x80000000 59 60/* SPI flash. */ 61#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL) 62#define AM33XX_SPI0_BASE 0x48030000 63#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET) 64#endif 65 66DECLARE_GLOBAL_DATA_PTR; 67 68int dram_init(void) 69{ 70#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) 71 sdram_init(); 72#endif 73 74 /* dram_init must store complete ramsize in gd->ram_size */ 75 gd->ram_size = get_ram_size( 76 (void *)CFG_SYS_SDRAM_BASE, 77 CFG_MAX_RAM_BANK_SIZE); 78 return 0; 79} 80 81int dram_init_banksize(void) 82{ 83 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; 84 gd->bd->bi_dram[0].size = gd->ram_size; 85 86 return 0; 87} 88 89#if !CONFIG_IS_ENABLED(OF_CONTROL) 90static const struct ns16550_plat am33xx_serial[] = { 91 { .base = CFG_SYS_NS16550_COM1, .reg_shift = 2, 92 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 93# ifdef CFG_SYS_NS16550_COM2 94 { .base = CFG_SYS_NS16550_COM2, .reg_shift = 2, 95 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 96# ifdef CFG_SYS_NS16550_COM3 97 { .base = CFG_SYS_NS16550_COM3, .reg_shift = 2, 98 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 99 { .base = CFG_SYS_NS16550_COM4, .reg_shift = 2, 100 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 101 { .base = CFG_SYS_NS16550_COM5, .reg_shift = 2, 102 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 103 { .base = CFG_SYS_NS16550_COM6, .reg_shift = 2, 104 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 105# endif 106# endif 107}; 108 109U_BOOT_DRVINFOS(am33xx_uarts) = { 110 { "ns16550_serial", &am33xx_serial[0] }, 111# ifdef CFG_SYS_NS16550_COM2 112 { "ns16550_serial", &am33xx_serial[1] }, 113# ifdef CFG_SYS_NS16550_COM3 114 { "ns16550_serial", &am33xx_serial[2] }, 115 { "ns16550_serial", &am33xx_serial[3] }, 116 { "ns16550_serial", &am33xx_serial[4] }, 117 { "ns16550_serial", &am33xx_serial[5] }, 118# endif 119# endif 120}; 121 122#if CONFIG_IS_ENABLED(DM_I2C) 123static const struct omap_i2c_plat am33xx_i2c[] = { 124 { I2C_BASE1, 100000, OMAP_I2C_REV_V2}, 125 { I2C_BASE2, 100000, OMAP_I2C_REV_V2}, 126 { I2C_BASE3, 100000, OMAP_I2C_REV_V2}, 127}; 128 129U_BOOT_DRVINFOS(am33xx_i2c) = { 130 { "i2c_omap", &am33xx_i2c[0] }, 131 { "i2c_omap", &am33xx_i2c[1] }, 132 { "i2c_omap", &am33xx_i2c[2] }, 133}; 134#endif 135 136#if CONFIG_IS_ENABLED(DM_GPIO) 137static const struct omap_gpio_plat am33xx_gpio[] = { 138 { 0, AM33XX_GPIO0_BASE }, 139 { 1, AM33XX_GPIO1_BASE }, 140 { 2, AM33XX_GPIO2_BASE }, 141 { 3, AM33XX_GPIO3_BASE }, 142#ifdef CONFIG_AM43XX 143 { 4, AM33XX_GPIO4_BASE }, 144 { 5, AM33XX_GPIO5_BASE }, 145#endif 146}; 147 148U_BOOT_DRVINFOS(am33xx_gpios) = { 149 { "gpio_omap", &am33xx_gpio[0] }, 150 { "gpio_omap", &am33xx_gpio[1] }, 151 { "gpio_omap", &am33xx_gpio[2] }, 152 { "gpio_omap", &am33xx_gpio[3] }, 153#ifdef CONFIG_AM43XX 154 { "gpio_omap", &am33xx_gpio[4] }, 155 { "gpio_omap", &am33xx_gpio[5] }, 156#endif 157}; 158#endif 159#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL) 160static const struct omap3_spi_plat omap3_spi_pdata = { 161 .regs = (struct mcspi *)AM33XX_SPI0_OFFSET, 162 .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT, 163}; 164 165U_BOOT_DRVINFO(am33xx_spi) = { 166 .name = "omap3_spi", 167 .plat = &omap3_spi_pdata, 168}; 169#endif 170#endif 171 172#if !CONFIG_IS_ENABLED(DM_GPIO) 173static const struct gpio_bank gpio_bank_am33xx[] = { 174 { (void *)AM33XX_GPIO0_BASE }, 175 { (void *)AM33XX_GPIO1_BASE }, 176 { (void *)AM33XX_GPIO2_BASE }, 177 { (void *)AM33XX_GPIO3_BASE }, 178#ifdef CONFIG_AM43XX 179 { (void *)AM33XX_GPIO4_BASE }, 180 { (void *)AM33XX_GPIO5_BASE }, 181#endif 182}; 183 184const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 185#endif 186 187#if defined(CONFIG_MMC_OMAP_HS) 188int cpu_mmc_init(struct bd_info *bis) 189{ 190 int ret; 191 192 ret = omap_mmc_init(0, 0, 0, -1, -1); 193 if (ret) 194 return ret; 195 196 return omap_mmc_init(1, 0, 0, -1, -1); 197} 198#endif 199 200/* 201 * RTC only with DDR in self-refresh mode magic value, checked against during 202 * boot to see if we have a valid config. This should be in sync with the value 203 * that will be in drivers/soc/ti/pm33xx.c. 204 */ 205#define RTC_MAGIC_VAL 0x8cd0 206 207/* Board type field bit shift for RTC only with DDR in self-refresh mode */ 208#define RTC_BOARD_TYPE_SHIFT 16 209 210/* AM33XX has two MUSB controllers which can be host or gadget */ 211#if (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 212 defined(CONFIG_SPL_BUILD) 213 214static struct musb_hdrc_config musb_config = { 215 .multipoint = 1, 216 .dyn_fifo = 1, 217 .num_eps = 16, 218 .ram_bits = 12, 219}; 220 221#ifdef CONFIG_AM335X_USB0 222static struct ti_musb_plat usb0 = { 223 .base = (void *)USB0_OTG_BASE, 224 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0, 225 .plat = { 226 .config = &musb_config, 227 .power = 50, 228 .platform_ops = &musb_dsps_ops, 229 }, 230}; 231#endif 232 233#ifdef CONFIG_AM335X_USB1 234static struct ti_musb_plat usb1 = { 235 .base = (void *)USB1_OTG_BASE, 236 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1, 237 .plat = { 238 .config = &musb_config, 239 .power = 50, 240 .platform_ops = &musb_dsps_ops, 241 }, 242}; 243#endif 244 245U_BOOT_DRVINFOS(am33xx_usbs) = { 246#ifdef CONFIG_AM335X_USB0_PERIPHERAL 247 { "ti-musb-peripheral", &usb0 }, 248#elif defined(CONFIG_AM335X_USB0_HOST) 249 { "ti-musb-host", &usb0 }, 250#endif 251#ifdef CONFIG_AM335X_USB1_PERIPHERAL 252 { "ti-musb-peripheral", &usb1 }, 253#elif defined(CONFIG_AM335X_USB1_HOST) 254 { "ti-musb-host", &usb1 }, 255#endif 256}; 257 258int arch_misc_init(void) 259{ 260 return 0; 261} 262#else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 263 264int arch_misc_init(void) 265{ 266 struct udevice *dev; 267 int ret; 268 269 ret = uclass_first_device_err(UCLASS_MISC, &dev); 270 if (ret) 271 return ret; 272 273#if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 274 usb_ether_init(); 275#endif 276 277 return 0; 278} 279 280#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 281 282#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) 283 284#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ 285 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) 286static void rtc32k_unlock(struct davinci_rtc *rtc) 287{ 288 /* 289 * Unlock the RTC's registers. For more details please see the 290 * RTC_SS section of the TRM. In order to unlock we need to 291 * write these specific values (keys) in this order. 292 */ 293 writel(RTC_KICK0R_WE, &rtc->kick0r); 294 writel(RTC_KICK1R_WE, &rtc->kick1r); 295} 296#endif 297 298#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 299/* 300 * Write contents of the RTC_SCRATCH1 register based on board type 301 * Two things are passed 302 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the 303 * control gets to kernel, kernel reads the scratchpad register and gets to 304 * know that bootloader has rtc_only support. 305 * 306 * Second important thing is the board type (16:31). This is needed in the 307 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to 308 * identify the board type and we go ahead and copy the board strings to 309 * am43xx_board_name. 310 */ 311void update_rtc_magic(void) 312{ 313 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 314 u32 magic = RTC_MAGIC_VAL; 315 316 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT); 317 318 rtc32k_unlock(rtc); 319 320 /* write magic */ 321 writel(magic, &rtc->scratch1); 322} 323#endif 324 325/* 326 * In the case of non-SPL based booting we'll want to call these 327 * functions a tiny bit later as it will require gd to be set and cleared 328 * and that's not true in s_init in this case so we cannot do it there. 329 */ 330int board_early_init_f(void) 331{ 332 set_mux_conf_regs(); 333 prcm_init(); 334#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 335 update_rtc_magic(); 336#endif 337 return 0; 338} 339 340/* 341 * This function is the place to do per-board things such as ramp up the 342 * MPU clock frequency. 343 */ 344__weak void am33xx_spl_board_init(void) 345{ 346} 347 348#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 349static void rtc32k_enable(void) 350{ 351 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 352 353 rtc32k_unlock(rtc); 354 355 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 356 writel((1 << 3) | (1 << 6), &rtc->osc); 357} 358#endif 359 360static void uart_soft_reset(void) 361{ 362 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 363 u32 regval; 364 365 regval = readl(&uart_base->uartsyscfg); 366 regval |= UART_RESET; 367 writel(regval, &uart_base->uartsyscfg); 368 while ((readl(&uart_base->uartsyssts) & 369 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 370 ; 371 372 /* Disable smart idle */ 373 regval = readl(&uart_base->uartsyscfg); 374 regval |= UART_SMART_IDLE_EN; 375 writel(regval, &uart_base->uartsyscfg); 376} 377 378static void watchdog_disable(void) 379{ 380 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 381 382 writel(0xAAAA, &wdtimer->wdtwspr); 383 while (readl(&wdtimer->wdtwwps) != 0x0) 384 ; 385 writel(0x5555, &wdtimer->wdtwspr); 386 while (readl(&wdtimer->wdtwwps) != 0x0) 387 ; 388} 389 390#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 391/* 392 * Check if we are executing rtc-only + DDR mode, and resume from it if needed 393 */ 394static void rtc_only(void) 395{ 396 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 397 struct prm_device_inst *prm_device = 398 (struct prm_device_inst *)PRM_DEVICE_INST; 399 400 u32 scratch1, sdrc; 401 void (*resume_func)(void); 402 403 scratch1 = readl(&rtc->scratch1); 404 405 /* 406 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only 407 * written to this register when we want to wake up from RTC only 408 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1: 409 * bits 0-15: RTC_MAGIC_VAL 410 * bits 16-31: board type (needed for sdram_init) 411 */ 412 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL) 413 return; 414 415 rtc32k_unlock(rtc); 416 417 /* Clear RTC magic */ 418 writel(0, &rtc->scratch1); 419 420 /* 421 * Update board type based on value stored on RTC_SCRATCH1, this 422 * is done so that we don't need to read the board type from eeprom 423 * over i2c bus which is expensive 424 */ 425 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT); 426 427 /* 428 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we 429 * are resuming from self-refresh. This avoids an unnecessary re-init 430 * of the DDR. The re-init takes time and we would need to wait for 431 * it to complete before accessing DDR to avoid L3 NOC errors. 432 */ 433 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl); 434 435 rtc_only_prcm_init(); 436 sdram_init(); 437 438 /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */ 439 /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */ 440 sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET); 441 442 sdrc &= AM43XX_SDRAM_TYPE_MASK; 443 sdrc >>= AM43XX_SDRAM_TYPE_SHIFT; 444 445 if (sdrc == AM43XX_SDRAM_TYPE_DDR3) { 446 writel(AM43XX_RDWRLVLFULL_START, 447 AM43XX_EMIF_BASE + 448 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET); 449 mdelay(1); 450 451am43xx_wait: 452 sdrc = readl(AM43XX_EMIF_BASE + 453 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET); 454 if (sdrc == AM43XX_RDWRLVLFULL_START) 455 goto am43xx_wait; 456 } 457 458 resume_func = (void *)readl(&rtc->scratch0); 459 if (resume_func) 460 resume_func(); 461} 462#endif 463 464void s_init(void) 465{ 466#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 467 rtc_only(); 468#endif 469} 470 471void early_system_init(void) 472{ 473 /* 474 * The ROM will only have set up sufficient pinmux to allow for the 475 * first 4KiB NOR to be read, we must finish doing what we know of 476 * the NOR mux in this space in order to continue. 477 */ 478#ifdef CONFIG_NOR_BOOT 479 enable_norboot_pin_mux(); 480#endif 481 watchdog_disable(); 482 set_uart_mux_conf(); 483 setup_early_clocks(); 484 uart_soft_reset(); 485#ifdef CONFIG_SPL_BUILD 486 /* 487 * Save the boot parameters passed from romcode. 488 * We cannot delay the saving further than this, 489 * to prevent overwrites. 490 */ 491 save_omap_boot_params(); 492#endif 493#ifdef CONFIG_DEBUG_UART_OMAP 494 debug_uart_init(); 495#endif 496 497#ifdef CONFIG_SPL_BUILD 498 spl_early_init(); 499#endif 500 501#ifdef CONFIG_TI_I2C_BOARD_DETECT 502 do_board_detect(); 503#endif 504 505#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 506 /* Enable RTC32K clock */ 507 rtc32k_enable(); 508#endif 509} 510 511#ifdef CONFIG_SPL_BUILD 512void board_init_f(ulong dummy) 513{ 514 hw_data_init(); 515 early_system_init(); 516 board_early_init_f(); 517 sdram_init(); 518 /* dram_init must store complete ramsize in gd->ram_size */ 519 gd->ram_size = get_ram_size( 520 (void *)CFG_SYS_SDRAM_BASE, 521 CFG_MAX_RAM_BANK_SIZE); 522} 523#endif 524 525#endif 526 527static int am33xx_dm_post_init(void) 528{ 529 hw_data_init(); 530#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) 531 early_system_init(); 532#endif 533 return 0; 534} 535EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init); 536