1/* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * NEXELL USB HOST EHCI Controller 4 * 5 * (C) Copyright 2016 Nexell 6 * Hyunseok, Jung <hsjung@nexell.co.kr> 7 */ 8 9#ifndef __ASM_ARM_ARCH_EHCI_H__ 10#define __ASM_ARM_ARCH_EHCI_H__ 11 12/* Nexell USBHOST PHY registers */ 13 14/* USBHOST Configuration 0 Register */ 15#define NX_HOST_CON0 0x14 16#define NX_HOST_CON0_SS_WORD_IF BIT(26) 17#define NX_HOST_CON0_SS_WORD_IF_ENB BIT(25) 18#define NX_HOST_CON0_SS_WORD_IF_16 ( \ 19 NX_HOST_CON0_SS_WORD_IF | \ 20 NX_HOST_CON0_SS_WORD_IF_ENB) 21 22#define NX_HOST_CON0_HSIC_480M_FROM_OTG_PHY BIT(24) 23#define NX_HOST_CON0_HSIC_FREE_CLOCK_ENB BIT(23) 24#define NX_HOST_CON0_HSIC_CLK_MASK (0x3 << 23) 25 26#define NX_HOST_CON0_N_HOST_HSIC_RESET_SYNC BIT(22) 27#define NX_HOST_CON0_N_HOST_UTMI_RESET_SYNC BIT(21) 28#define NX_HOST_CON0_N_HOST_PHY_RESET_SYNC BIT(20) 29#define NX_HOST_CON0_UTMI_RESET_SYNC ( \ 30 NX_HOST_CON0_N_HOST_HSIC_RESET_SYNC | \ 31 NX_HOST_CON0_N_HOST_UTMI_RESET_SYNC | \ 32 NX_HOST_CON0_N_HOST_PHY_RESET_SYNC) 33 34#define NX_HOST_CON0_N_AUXWELL_RESET_SYNC BIT(19) 35#define NX_HOST_CON0_N_OHCI_RESET_SYNC BIT(18) 36#define NX_HOST_CON0_N_RESET_SYNC BIT(17) 37#define NX_HOST_CON0_AHB_RESET_SYNC ( \ 38 NX_HOST_CON0_N_AUXWELL_RESET_SYNC | \ 39 NX_HOST_CON0_N_OHCI_RESET_SYNC | \ 40 NX_HOST_CON0_N_RESET_SYNC) 41 42#define NX_HOST_CON0_HSIC_EN_PORT1 (0x2 << 14) 43#define NX_HOST_CON0_HSIC_EN_MASK (0x7 << 14) 44 45/* USBHOST Configuration 1 Register */ 46#define NX_HOST_CON1 0x18 47 48/* USBHOST Configuration 2 Register */ 49#define NX_HOST_CON2 0x1C 50#define NX_HOST_CON2_SS_ENA_INCRX_ALIGN (0x1 << 28) 51#define NX_HOST_CON2_SS_ENA_INCR4 (0x1 << 27) 52#define NX_HOST_CON2_SS_ENA_INCR8 (0x1 << 26) 53#define NX_HOST_CON2_SS_ENA_INCR16 (0x1 << 25) 54#define NX_HOST_CON2_SS_DMA_BURST_MASK \ 55 (NX_HOST_CON2_SS_ENA_INCR16 | NX_HOST_CON2_SS_ENA_INCR8 | \ 56 NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN) 57 58#define NX_HOST_CON2_EHCI_SS_ENABLE_DMA_BURST \ 59 (NX_HOST_CON2_SS_ENA_INCR16 | NX_HOST_CON2_SS_ENA_INCR8 | \ 60 NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN) 61 62#define NX_HOST_CON2_OHCI_SS_ENABLE_DMA_BURST \ 63 (NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN) 64 65#define NX_HOST_CON2_SS_FLADJ_VAL_0_OFFSET (21) 66#define NX_HOST_CON2_SS_FLADJ_VAL_OFFSET (3) 67#define NX_HOST_CON2_SS_FLADJ_VAL_NUM (6) 68#define NX_HOST_CON2_SS_FLADJ_VAL_0_SEL BIT(5) 69#define NX_HOST_CON2_SS_FLADJ_VAL_MAX 0x7 70 71/* USBHOST Configuration 3 Register */ 72#define NX_HOST_CON3 0x20 73#define NX_HOST_CON3_POR BIT(8) 74#define NX_HOST_CON3_POR_ENB BIT(7) 75#define NX_HOST_CON3_POR_MASK (0x3 << 7) 76 77/* USBHOST Configuration 4 Register */ 78#define NX_HOST_CON4 0x24 79#define NX_HOST_CON4_WORDINTERFACE BIT(9) 80#define NX_HOST_CON4_WORDINTERFACE_ENB BIT(8) 81#define NX_HOST_CON4_WORDINTERFACE_16 ( \ 82 NX_HOST_CON4_WORDINTERFACE | \ 83 NX_HOST_CON4_WORDINTERFACE_ENB) 84 85/* USBHOST Configuration 5 Register */ 86#define NX_HOST_CON5 0x28 87#define NX_HOST_CON5_HSIC_POR BIT(19) 88#define NX_HOST_CON5_HSIC_POR_ENB BIT(18) 89#define NX_HOST_CON5_HSIC_POR_MASK (0x3 << 18) 90 91/* USBHOST Configuration 6 Register */ 92#define NX_HOST_CON6 0x2C 93#define NX_HOST_CON6_HSIC_WORDINTERFACE BIT(13) 94#define NX_HOST_CON6_HSIC_WORDINTERFACE_ENB BIT(12) 95#define NX_HOST_CON6_HSIC_WORDINTERFACE_16 ( \ 96 NX_HOST_CON6_HSIC_WORDINTERFACE | \ 97 NX_HOST_CON6_HSIC_WORDINTERFACE_ENB) 98 99/* Register map for PHY control */ 100struct nx_usb_phy { 101 unsigned int reserved; 102 unsigned int others[4]; 103 unsigned int usbhost_con[7]; 104}; 105 106#endif /* __ASM_ARM_ARCH_EHCI_H__ */ 107