1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 * 7 * Header file for the Marvell's Feroceon CPU core. 8 */ 9 10#ifndef _MVEBU_SOC_H 11#define _MVEBU_SOC_H 12 13#ifndef __ASSEMBLY__ 14#include <linux/bitops.h> 15#endif 16 17#define SOC_MV78230_ID 0x7823 18#define SOC_MV78260_ID 0x7826 19#define SOC_MV78460_ID 0x7846 20#define SOC_88F6720_ID 0x6720 21#define SOC_88F6810_ID 0x6810 22#define SOC_88F6820_ID 0x6820 23#define SOC_88F6828_ID 0x6828 24#define SOC_98DX3236_ID 0xf410 25#define SOC_98DX3336_ID 0xf400 26#define SOC_98DX4251_ID 0xfc00 27 28/* A375 revisions */ 29#define MV_88F67XX_A0_ID 0x3 30 31/* A38x revisions */ 32#define MV_88F68XX_Z1_ID 0x0 33#define MV_88F68XX_A0_ID 0x4 34#define MV_88F68XX_B0_ID 0xa 35 36/* SOC specific definations */ 37#define INTREG_BASE 0xd0000000 38#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) 39#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700) 40/* 41 * The SPL U-Boot version still runs with the default 42 * address for the internal registers, configured by 43 * the BootROM. Only the main U-Boot version uses the 44 * new internal register base address, that also is 45 * required for the Linux kernel. 46 */ 47#define SOC_REGS_PHY_BASE 0xd0000000 48#elif defined(CONFIG_ARMADA_8K) 49#define SOC_REGS_PHY_BASE 0xf0000000 50#else 51#define SOC_REGS_PHY_BASE 0xf1000000 52#endif 53#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x) 54 55#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) 56#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) 57#define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE 58#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) 59#define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100)) 60#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) 61#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) 62#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) 63#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180)) 64#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200)) 65#define MVEBU_CLOCK_BASE (MVEBU_REGISTER(0x18700)) 66#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) 67#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) 68#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) 69#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) 70#define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000)) 71#define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) 72#define MVEBU_REG_PCIE0_BASE (MVEBU_REGISTER(0x80000)) 73#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) 74#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) 75#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) 76#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) 77#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000)) 78#ifdef CONFIG_ARMADA_MSYS 79#define MVEBU_DFX_BASE (MBUS_DFX_BASE) 80#else 81#define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000)) 82#endif 83 84#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) 85#define MBUS_ERR_PROP_EN (1 << 8) 86 87#define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250)) 88#define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254)) 89 90#define MVEBU_SOC_DEV_MUX_REG (MVEBU_SYSTEM_REG_BASE + 0x08) 91#define NAND_EN BIT(0) 92#define NAND_ARBITER_EN BIT(27) 93 94#define ARMADA_XP_PUP_ENABLE (MVEBU_SYSTEM_REG_BASE + 0x44c) 95#define GE0_PUP_EN BIT(0) 96#define GE1_PUP_EN BIT(1) 97#define LCD_PUP_EN BIT(2) 98#define NAND_PUP_EN BIT(4) 99#define SPI_PUP_EN BIT(5) 100 101#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8)) 102#ifdef CONFIG_ARMADA_MSYS 103#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4)) 104#define NAND_ECC_DIVCKL_RATIO_OFFS 6 105#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) 106#else 107#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4)) 108#endif 109#ifdef CONFIG_ARMADA_MSYS 110#define NAND_ECC_DIVCKL_RATIO_OFFS 6 111#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) 112#else 113#define NAND_ECC_DIVCKL_RATIO_OFFS 8 114#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS) 115#endif 116 117#define SDRAM_MAX_CS 4 118#define SDRAM_ADDR_MASK 0xFF000000 119 120/* MVEBU CPU memory windows */ 121#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA 122#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE 123#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE 124 125#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) 126 127/* BootROM error register (also includes some status infos) */ 128#define BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) 129#define BOOTROM_ERR_MODE_OFFS 28 130#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) 131#define BOOTROM_ERR_MODE_MAIN 0x2 132#define BOOTROM_ERR_MODE_EXEC 0x3 133#define BOOTROM_ERR_MODE_UART 0x6 134#define BOOTROM_ERR_MODE_PEX 0x8 135#define BOOTROM_ERR_MODE_NOR 0x9 136#define BOOTROM_ERR_MODE_NAND 0xA 137#define BOOTROM_ERR_MODE_SATA 0xB 138#define BOOTROM_ERR_MODE_MMC 0xE 139#define BOOTROM_ERR_CODE_OFFS 0 140#define BOOTROM_ERR_CODE_MASK (0xf << BOOTROM_ERR_CODE_OFFS) 141 142#if defined(CONFIG_ARMADA_375) 143/* SAR values for Armada 375 */ 144#define CFG_SAR_REG (MVEBU_REGISTER(0xe8200)) 145#define CFG_SAR2_REG (MVEBU_REGISTER(0xe8204)) 146 147#define SAR_CPU_FREQ_OFFS 17 148#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) 149 150#define BOOT_DEV_SEL_OFFS 3 151#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) 152 153#define BOOT_FROM_UART(x) (x == 0x30) 154#define BOOT_FROM_SPI(x) (x == 0x38) 155 156#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(20)) ? \ 157 200000000 : 166000000) 158#elif defined(CONFIG_ARMADA_38X) 159/* SAR values for Armada 38x */ 160#define CFG_SAR_REG (MVEBU_REGISTER(0x18600)) 161 162#define SAR_CPU_FREQ_OFFS 10 163#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) 164#define SAR_BOOT_DEVICE_OFFS 4 165#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) 166 167#define BOOT_DEV_SEL_OFFS 4 168#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) 169 170#define BOOT_FROM_NOR(x) ((x >= 0x00 && x <= 0x07) || x == 0x16 || x == 0x17 || x == 0x2E || x == 0x2F || (x >= 0x3A && x <= 0x3C)) 171#define BOOT_FROM_NAND(x) ((x >= 0x08 && x <= 0x15) || (x >= 0x18 && x <= 0x25)) 172#define BOOT_FROM_SPINAND(x) (x == 0x26 || x == 0x27) 173#define BOOT_FROM_UART(x) (x == 0x28 || x == 0x29) 174#define BOOT_FROM_SATA(x) (x == 0x2A || x == 0x2B) 175#define BOOT_FROM_PEX(x) (x == 0x2C || x == 0x2D) 176#define BOOT_FROM_MMC(x) (x == 0x30 || x == 0x31) 177#define BOOT_FROM_SPI(x) (x >= 0x32 && x <= 0x39) 178 179#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(15)) ? \ 180 200000000 : 250000000) 181#elif defined(CONFIG_ARMADA_MSYS) 182/* SAR values for MSYS */ 183#define CFG_SAR_REG (MBUS_DFX_BASE + 0xf8200) 184#define CFG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) 185 186#define SAR_CPU_FREQ_OFFS 18 187#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) 188#define SAR_BOOT_DEVICE_OFFS 11 189#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS) 190 191#define BOOT_DEV_SEL_OFFS 11 192#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS) 193 194#define BOOT_FROM_NAND(x) (x == 0x1) 195#define BOOT_FROM_UART(x) (x == 0x2) 196#define BOOT_FROM_SPI(x) (x == 0x3) 197 198#define CFG_SYS_TCLK 200000000 /* 200MHz */ 199#elif defined(CONFIG_ARMADA_XP) 200/* SAR values for Armada XP */ 201#define CFG_SAR_REG (MVEBU_REGISTER(0x18230)) 202#define CFG_SAR2_REG (MVEBU_REGISTER(0x18234)) 203 204#define SAR_CPU_FREQ_OFFS 21 205#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) 206#define SAR_FFC_FREQ_OFFS 24 207#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) 208#define SAR2_CPU_FREQ_OFFS 20 209#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) 210#define SAR_BOOT_DEVICE_OFFS 5 211#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) 212 213#define BOOT_DEV_SEL_OFFS 5 214#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS) 215 216#define BOOT_FROM_NOR(x) (x == 0x0) 217#define BOOT_FROM_NAND(x) (x == 0x1) 218#define BOOT_FROM_UART(x) (x == 0x2) 219#define BOOT_FROM_SPI(x) (x == 0x3) 220#define BOOT_FROM_PEX(x) (x == 0x4) 221#define BOOT_FROM_SATA(x) (x == 0x5) 222 223#define CFG_SYS_TCLK 250000000 /* 250MHz */ 224#endif 225 226#endif /* _MVEBU_SOC_H */ 227