1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 */ 7 8#ifndef _MVEBU_CPU_H 9#define _MVEBU_CPU_H 10 11#include <asm/system.h> 12 13#ifndef __ASSEMBLY__ 14 15#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) 16#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) 17 18enum memory_bank { 19 BANK0, 20 BANK1, 21 BANK2, 22 BANK3 23}; 24 25enum cpu_winen { 26 CPU_WIN_DISABLE, 27 CPU_WIN_ENABLE 28}; 29 30enum cpu_target { 31 CPU_TARGET_DRAM = 0x0, 32 CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1, 33 CPU_TARGET_ETH23 = 0x3, 34 CPU_TARGET_PCIE02 = 0x4, 35 CPU_TARGET_ETH01 = 0x7, 36 CPU_TARGET_PCIE13 = 0x8, 37 CPU_TARGET_DFX = 0x8, 38 CPU_TARGET_SASRAM = 0x9, 39 CPU_TARGET_SATA01 = 0xa, /* A38X */ 40 CPU_TARGET_NAND = 0xd, 41 CPU_TARGET_SATA23_DFX = 0xe, /* A38X */ 42}; 43 44enum cpu_attrib { 45 CPU_ATTR_SASRAM = 0x01, 46 CPU_ATTR_DRAM_CS0 = 0x0e, 47 CPU_ATTR_DRAM_CS1 = 0x0d, 48 CPU_ATTR_DRAM_CS2 = 0x0b, 49 CPU_ATTR_DRAM_CS3 = 0x07, 50 CPU_ATTR_NANDFLASH = 0x2f, 51 CPU_ATTR_SPIFLASH = 0x1e, 52 CPU_ATTR_SPI0_CS0 = 0x1e, 53 CPU_ATTR_SPI0_CS1 = 0x5e, 54 CPU_ATTR_SPI1_CS2 = 0x9a, 55 CPU_ATTR_BOOTROM = 0x1d, 56 CPU_ATTR_PCIE_IO = 0xe0, 57 CPU_ATTR_PCIE_MEM = 0xe8, 58 CPU_ATTR_DEV_CS0 = 0x3e, 59 CPU_ATTR_DEV_CS1 = 0x3d, 60 CPU_ATTR_DEV_CS2 = 0x3b, 61 CPU_ATTR_DEV_CS3 = 0x37, 62}; 63 64#define MVEBU_SDRAM_SIZE_MAX 0xc0000000 65 66/* 67 * Default Device Address MAP BAR values 68 */ 69#ifdef CONFIG_SPL_BUILD 70#ifdef CONFIG_ARMADA_38X 71#define MBUS_PCI_MEM_BASE 0x88000000 72#define MBUS_PCI_MEM_SIZE ((3 * 128) << 20) 73#else 74#define MBUS_PCI_MEM_BASE 0x80000000 75#define MBUS_PCI_MEM_SIZE ((4 * 128) << 20) 76#endif 77#else 78#define MBUS_PCI_MAX_PORTS 6 79#define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX 80#define MBUS_PCI_MEM_SIZE ((MBUS_PCI_MAX_PORTS * 128) << 20) 81#define MBUS_PCI_IO_BASE 0xF1100000 82#define MBUS_PCI_IO_SIZE ((MBUS_PCI_MAX_PORTS * 64) << 10) 83#endif 84#ifdef CONFIG_SPL_BUILD 85#define MBUS_SPI_BASE 0xD4000000 86#define MBUS_SPI_SIZE (64 << 20) 87#else 88#define MBUS_SPI_BASE 0xF4000000 89#define MBUS_SPI_SIZE (8 << 20) 90#endif 91#ifndef CONFIG_SPL_BUILD 92#define MBUS_DFX_BASE 0xF6000000 93#define MBUS_DFX_SIZE (1 << 20) 94#endif 95#define MBUS_BOOTROM_BASE 0xF8000000 96#ifdef CONFIG_SPL_BUILD 97#define MBUS_BOOTROM_SIZE (128 << 20) 98#else 99#define MBUS_BOOTROM_SIZE (8 << 20) 100#endif 101 102struct mbus_win { 103 u32 base; 104 u32 size; 105 u8 target; 106 u8 attr; 107}; 108 109/* 110 * System registers 111 * Ref: Datasheet sec:A.28 112 */ 113struct mvebu_system_registers { 114#if defined(CONFIG_ARMADA_375) 115 u8 pad1[0x54]; 116#else 117 u8 pad1[0x60]; 118#endif 119 u32 rstoutn_mask; /* 0x60 */ 120 u32 sys_soft_rst; /* 0x64 */ 121}; 122 123/* 124 * GPIO Registers 125 * Ref: Datasheet sec:A.19 126 */ 127struct kwgpio_registers { 128 u32 dout; 129 u32 oe; 130 u32 blink_en; 131 u32 din_pol; 132 u32 din; 133 u32 irq_cause; 134 u32 irq_mask; 135 u32 irq_level; 136}; 137 138struct sar_freq_modes { 139 u8 val; 140 u8 ffc; /* Fabric Frequency Configuration */ 141 u32 p_clk; 142 u32 nb_clk; 143 u32 d_clk; 144}; 145 146/* 147 * functions 148 */ 149unsigned int mvebu_sdram_bar(enum memory_bank bank); 150unsigned int mvebu_sdram_bs(enum memory_bank bank); 151void mvebu_sdram_size_adjust(enum memory_bank bank); 152int mvebu_mbus_probe(const struct mbus_win windows[], int count); 153u32 mvebu_get_nand_clock(void); 154 155void __noreturn return_to_bootrom(void); 156 157#ifndef CONFIG_DM_MMC 158int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); 159#endif 160 161u32 get_boot_device(void); 162 163void get_sar_freq(struct sar_freq_modes *sar_freq); 164 165/* 166 * Highspeed SERDES PHY config init, ported from bin_hdr 167 * to mainline U-Boot 168 */ 169int serdes_phy_config(void); 170 171/* 172 * DDR3 init / training code ported from Marvell bin_hdr. Now 173 * available in mainline U-Boot in: 174 * drivers/ddr/marvell 175 */ 176int ddr3_init(void); 177 178/* Auto Voltage Scaling */ 179#if defined(CONFIG_ARMADA_38X) 180void mv_avs_init(void); 181void mv_rtc_config(void); 182#else 183static inline void mv_avs_init(void) {} 184static inline void mv_rtc_config(void) {} 185#endif 186 187/* A8K dram functions */ 188u64 a8k_dram_scan_ap_sz(void); 189int a8k_dram_init_banksize(void); 190 191/* A3700 dram functions */ 192int a3700_dram_init(void); 193int a3700_dram_init_banksize(void); 194 195/* A3700 PCIe regions fixer for device tree */ 196int a3700_fdt_fix_pcie_regions(void *blob); 197 198/* Alleycat5 dram functions */ 199int alleycat5_dram_init(void); 200int alleycat5_dram_init_banksize(void); 201 202/* 203 * get_ref_clk 204 * 205 * return: reference clock in MHz (25 or 40) 206 */ 207u32 get_ref_clk(void); 208 209#endif /* __ASSEMBLY__ */ 210#endif /* _MVEBU_CPU_H */ 211