1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * K3: AM6 SoC definitions, structures etc. 4 * 5 * (C) Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#ifndef __ASM_ARCH_AM6_HARDWARE_H 8#define __ASM_ARCH_AM6_HARDWARE_H 9 10#include <config.h> 11#ifndef __ASSEMBLY__ 12#include <linux/bitops.h> 13#endif 14 15#define CTRL_MMR0_BASE 0x00100000 16#define WKUP_CTRL_MMR0_BASE 0x43000000 17#define MCU_CTRL_MMR0_BASE 0x40f00000 18 19#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) 20#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0) 21#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0 22#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4) 23#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 4 24#define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK GENMASK(12, 12) 25#define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT 12 26#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK GENMASK(14, 14) 27#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT 14 28#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK GENMASK(17, 17) 29#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 12 30#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT 9 31#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK GENMASK(10, 9) 32 33/* MCU SCRATCHPAD usage */ 34#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE 35 36/* NAVSS Northbridge config */ 37#define NAVSS0_NBSS_NB0_CFG_BASE 0x03802000 38#define NAVSS0_NBSS_NB1_CFG_BASE 0x03803000 39 40#define NAVSS_NBSS_THREADMAP 0x10 41 42#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) 43 44#define AM6_DEV_MCU_RTI0 134 45#define AM6_DEV_MCU_RTI1 135 46#define AM6_DEV_MCU_ARMSS0_CPU0 159 47#define AM6_DEV_MCU_ARMSS0_CPU1 245 48 49static const u32 put_device_ids[] = { 50 AM6_DEV_MCU_RTI0, 51 AM6_DEV_MCU_RTI1, 52}; 53 54static const u32 put_core_ids[] = { 55 AM6_DEV_MCU_ARMSS0_CPU1, 56 AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ 57}; 58 59#endif 60 61#endif /* __ASM_ARCH_AM6_HARDWARE_H */ 62