1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * K3: AM62 SoC definitions, structures etc.
4 *
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 *	Suman Anna <s-anna@ti.com>
7 */
8
9#ifndef __ASM_ARCH_AM62_HARDWARE_H
10#define __ASM_ARCH_AM62_HARDWARE_H
11
12#include <config.h>
13#ifndef __ASSEMBLY__
14#include <linux/bitops.h>
15#endif
16
17#define PADCFG_MMR0_BASE			0x04080000
18#define PADCFG_MMR1_BASE			0x000f0000
19#define CTRL_MMR0_BASE				0x00100000
20#define MCU_CTRL_MMR0_BASE			0x04500000
21#define WKUP_CTRL_MMR0_BASE			0x43000000
22
23#define CTRLMMR_WKUP_JTAG_DEVICE_ID		(WKUP_CTRL_MMR0_BASE + 0x18)
24#define JTAG_DEV_ID_MASK			GENMASK(31, 18)
25#define JTAG_DEV_ID_SHIFT			18
26#define JTAG_DEV_CORE_NR_MASK			GENMASK(21, 19)
27#define JTAG_DEV_CORE_NR_SHIFT			19
28#define JTAG_DEV_GPU_MASK			BIT(18)
29#define JTAG_DEV_GPU_SHIFT			18
30#define JTAG_DEV_FEATURES_MASK			GENMASK(17, 13)
31#define JTAG_DEV_FEATURES_SHIFT			13
32#define JTAG_DEV_SECURITY_MASK			BIT(12)
33#define JTAG_DEV_SECURITY_SHIFT			12
34#define JTAG_DEV_SAFETY_MASK			BIT(11)
35#define JTAG_DEV_SAFETY_SHIFT			11
36#define JTAG_DEV_SPEED_MASK			GENMASK(10, 6)
37#define JTAG_DEV_SPEED_SHIFT			6
38#define JTAG_DEV_TEMP_MASK			GENMASK(5, 3)
39#define JTAG_DEV_TEMP_SHIFT			3
40#define JTAG_DEV_PKG_MASK			GENMASK(2, 0)
41#define JTAG_DEV_PKG_SHIFT			0
42
43#define JTAG_DEV_FEATURE_NO_PRU			0x4
44
45#define JTAG_DEV_TEMP_COMMERCIAL		0x3
46#define JTAG_DEV_TEMP_INDUSTRIAL		0x4
47#define JTAG_DEV_TEMP_AUTOMOTIVE		0x5
48
49#define CTRLMMR_MAIN_DEVSTAT			(WKUP_CTRL_MMR0_BASE + 0x30)
50#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK	GENMASK(6, 3)
51#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT	3
52#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK	GENMASK(9, 7)
53#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT	7
54#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK	GENMASK(12, 10)
55#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT	10
56#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK	BIT(13)
57#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT	13
58#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK	(~BIT(17))
59
60/* Primary Bootmode MMC Config macros */
61#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK	0x4
62#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT	2
63#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK	0x1
64#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT	0
65
66/* Primary Bootmode USB Config macros */
67#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT	1
68#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK	0x02
69
70/* Backup Bootmode USB Config macros */
71#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK	0x01
72
73#define MCU_CTRL_LFXOSC_CTRL			(MCU_CTRL_MMR0_BASE + 0x8038)
74#define MCU_CTRL_LFXOSC_TRIM			(MCU_CTRL_MMR0_BASE + 0x803c)
75#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL		BIT(7)
76
77#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL		(MCU_CTRL_MMR0_BASE + 0x8058)
78#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL	(0x3)
79
80#define CTRLMMR_MCU_RST_CTRL			(MCU_CTRL_MMR0_BASE + 0x18170)
81
82/* Debounce register configuration */
83#define CTRLMMR_DBOUNCE_CFG(index)		(MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4))
84
85#define ROM_EXTENDED_BOOT_DATA_INFO		0x43c3f1e0
86#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM		0x7000F290
87
88#define TI_SRAM_SCRATCH_BOARD_EEPROM_START	0x43c30000
89
90static inline int k3_get_core_nr(void)
91{
92	u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
93
94	return (full_devid & JTAG_DEV_CORE_NR_MASK) >> JTAG_DEV_CORE_NR_SHIFT;
95}
96
97static inline char k3_get_speed_grade(void)
98{
99	u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
100	u32 speed_grade = (full_devid & JTAG_DEV_SPEED_MASK) >>
101			   JTAG_DEV_SPEED_SHIFT;
102
103	return 'A' - 1 + speed_grade;
104}
105
106static inline int k3_get_temp_grade(void)
107{
108	u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
109
110	return (full_devid & JTAG_DEV_TEMP_MASK) >> JTAG_DEV_TEMP_SHIFT;
111}
112
113static inline int k3_get_max_temp(void)
114{
115	switch (k3_get_temp_grade()) {
116	case JTAG_DEV_TEMP_INDUSTRIAL:
117		return 105;
118	case JTAG_DEV_TEMP_AUTOMOTIVE:
119		return 125;
120	case JTAG_DEV_TEMP_COMMERCIAL:
121	default:
122		return 95;
123	}
124}
125
126static inline int k3_get_a53_max_frequency(void)
127{
128	switch (k3_get_speed_grade()) {
129	case 'K':
130		return 800000000;
131	case 'S':
132		return 1000000000;
133	case 'T':
134		return 1250000000;
135	case 'G':
136	default:
137		return 300000000;
138	}
139}
140
141static inline int k3_has_pru(void)
142{
143	u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
144	u32 feature_mask = (full_devid & JTAG_DEV_FEATURES_MASK) >>
145			   JTAG_DEV_FEATURES_SHIFT;
146
147	return !(feature_mask & JTAG_DEV_FEATURE_NO_PRU);
148}
149
150static inline int k3_has_gpu(void)
151{
152	u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
153
154	return (full_devid & JTAG_DEV_GPU_MASK) >> JTAG_DEV_GPU_SHIFT;
155}
156
157#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
158
159static const u32 put_device_ids[] = {};
160
161static const u32 put_core_ids[] = {};
162
163#endif
164
165#endif /* __ASM_ARCH_AM62_HARDWARE_H */
166