1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Machine Specific Values for SMDK5250 board based on EXYNOS5 4 * 5 * Copyright (C) 2012 Samsung Electronics 6 */ 7 8#ifndef _SMDK5250_SETUP_H 9#define _SMDK5250_SETUP_H 10 11#include <asm/arch/dmc.h> 12 13#define NOT_AVAILABLE 0 14#define DATA_MASK 0xFFFFF 15 16#define ENABLE_BIT 0x1 17#define DISABLE_BIT 0x0 18#define CA_SWAP_EN (1 << 0) 19 20/* Set PLL */ 21#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) 22 23/* MEMCONTROL register bit fields */ 24#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0) 25#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1) 26#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2) 27#define DMC_MEMCONTROL_TP_DISABLE (0 << 4) 28#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5) 29#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5) 30#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) 31 32#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8) 33#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) 34#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8) 35 36#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12) 37 38#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) 39#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16) 40 41#define DMC_MEMCONTROL_BL_8 (3 << 20) 42#define DMC_MEMCONTROL_BL_4 (2 << 20) 43 44#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24) 45 46#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) 47#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) 48#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) 49#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) 50 51/* MEMCONFIG0 register bit fields */ 52#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12) 53#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12) 54#define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8) 55#define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4) 56#define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4) 57#define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0) 58 59#define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16) 60#define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0) 61#define DMC_MEMBASECONFIG_VAL(x) ( \ 62 DMC_MEMBASECONFIGX_CHIP_BASE(x) | \ 63 DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \ 64) 65 66/* 67 * As we use channel interleaving, therefore value of the base address 68 * register must be set as half of the bus base address 69 * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so 70 * we need to set half 0x10 to the membaseconfigx registers 71 * see exynos5420 UM section 17.17.3.21 for more. 72 */ 73#define DMC_CHIP_BASE_0 0x10 74#define DMC_CHIP_BASE_1 0x50 75#define DMC_CHIP_MASK 0x7C0 76 77#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) 78#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80) 79 80#define DMC_PRECHCONFIG_VAL 0xFF000000 81#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF 82 83#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000 84#define DFI_INIT_START (1 << 28) 85#define EMPTY (1 << 8) 86#define AREF_EN (1 << 5) 87 88#define DFI_INIT_COMPLETE_CHO (1 << 2) 89#define DFI_INIT_COMPLETE_CH1 (1 << 3) 90 91#define RDLVL_COMPLETE_CHO (1 << 14) 92#define RDLVL_COMPLETE_CH1 (1 << 15) 93 94#define CLK_STOP_EN (1 << 0) 95#define DPWRDN_EN (1 << 1) 96#define DSREF_EN (1 << 5) 97 98/* COJCONTROL register bit fields */ 99#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3) 100#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3) 101#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5) 102#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5) 103#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8) 104#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8) 105#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12) 106#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16) 107#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) 108 109#define DMC_CONCONTROL_VAL 0x1FFF2101 110 111#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \ 112 | DMC_CONCONTROL_AREF_EN_ENABLE \ 113 | DMC_CONCONTROL_IO_PD_CON_ENABLE 114 115#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6) 116 117/* CLK_DIV_CPU1 */ 118#define HPM_RATIO 0x2 119#define COPY_RATIO 0x0 120 121/* CLK_DIV_CPU1 = 0x00000003 */ 122#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ 123 | (COPY_RATIO)) 124 125/* CLK_SRC_CORE0 */ 126#define CLK_SRC_CORE0_VAL 0x00000000 127 128/* CLK_SRC_CORE1 */ 129#define CLK_SRC_CORE1_VAL 0x100 130 131/* CLK_DIV_CORE0 */ 132#define CLK_DIV_CORE0_VAL 0x00120000 133 134/* CLK_DIV_CORE1 */ 135#define CLK_DIV_CORE1_VAL 0x07070700 136 137/* CLK_DIV_SYSRGT */ 138#define CLK_DIV_SYSRGT_VAL 0x00000111 139 140/* CLK_DIV_ACP */ 141#define CLK_DIV_ACP_VAL 0x12 142 143/* CLK_DIV_SYSLFT */ 144#define CLK_DIV_SYSLFT_VAL 0x00000311 145 146#define MUX_APLL_SEL_MASK (1 << 0) 147#define MUX_MPLL_SEL_MASK (1 << 8) 148#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8) 149#define MUX_CPLL_SEL_MASK (1 << 8) 150#define MUX_EPLL_SEL_MASK (1 << 12) 151#define MUX_VPLL_SEL_MASK (1 << 16) 152#define MUX_GPLL_SEL_MASK (1 << 28) 153#define MUX_BPLL_SEL_MASK (1 << 0) 154#define MUX_HPM_SEL_MASK (1 << 20) 155#define HPM_SEL_SCLK_MPLL (1 << 21) 156#define PLL_LOCKED (1 << 29) 157#define APLL_CON0_LOCKED (1 << 29) 158#define MPLL_CON0_LOCKED (1 << 29) 159#define BPLL_CON0_LOCKED (1 << 29) 160#define CPLL_CON0_LOCKED (1 << 29) 161#define EPLL_CON0_LOCKED (1 << 29) 162#define GPLL_CON0_LOCKED (1 << 29) 163#define VPLL_CON0_LOCKED (1 << 29) 164#define CLK_REG_DISABLE 0x0 165#define TOP2_VAL 0x0110000 166 167/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */ 168#define SPI0_ISP_SEL 6 169#define SPI1_ISP_SEL 6 170#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \ 171 | (SPI0_ISP_SEL << 0) 172 173/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */ 174#define SPI0_ISP_RATIO 0xf 175#define SPI1_ISP_RATIO 0xf 176#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \ 177 | (SPI0_ISP_RATIO << 0) 178 179/* CLK_DIV_FSYS2 */ 180#define MMC2_RATIO_MASK 0xf 181#define MMC2_RATIO_VAL 0x3 182#define MMC2_RATIO_OFFSET 0 183 184#define MMC2_PRE_RATIO_MASK 0xff 185#define MMC2_PRE_RATIO_VAL 0x9 186#define MMC2_PRE_RATIO_OFFSET 8 187 188#define MMC3_RATIO_MASK 0xf 189#define MMC3_RATIO_VAL 0x1 190#define MMC3_RATIO_OFFSET 16 191 192#define MMC3_PRE_RATIO_MASK 0xff 193#define MMC3_PRE_RATIO_VAL 0x0 194#define MMC3_PRE_RATIO_OFFSET 24 195 196/* CLK_SRC_LEX */ 197#define CLK_SRC_LEX_VAL 0x0 198 199/* CLK_DIV_LEX */ 200#define CLK_DIV_LEX_VAL 0x10 201 202/* CLK_DIV_R0X */ 203#define CLK_DIV_R0X_VAL 0x10 204 205/* CLK_DIV_L0X */ 206#define CLK_DIV_R1X_VAL 0x10 207 208/* CLK_DIV_ISP2 */ 209#define CLK_DIV_ISP2_VAL 0x1 210 211/* CLK_SRC_KFC */ 212#define SRC_KFC_HPM_SEL (1 << 15) 213 214/* CLK_SRC_KFC */ 215#define CLK_SRC_KFC_VAL 0x00008001 216 217/* CLK_DIV_KFC */ 218#define CLK_DIV_KFC_VAL 0x03300110 219 220/* CLK_DIV2_RATIO */ 221#define CLK_DIV2_RATIO 0x10111150 222 223/* CLK_DIV4_RATIO */ 224#define CLK_DIV4_RATIO 0x00000003 225 226/* CLK_DIV_G2D */ 227#define CLK_DIV_G2D 0x00000010 228 229/* 230 * DIV_DISP1_0 231 * For DP, divisor should be 2 232 */ 233#define CLK_DIV_DISP1_0_FIMD1 (2 << 0) 234 235/* CLK_GATE_IP_DISP1 */ 236#define CLK_GATE_DP1_ALLOW (1 << 4) 237 238/* AUDIO CLK SEL */ 239#define AUDIO0_SEL_EPLL (0x6 << 28) 240#define AUDIO0_RATIO 0x5 241#define PCM0_RATIO 0x3 242#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20) 243 244/* CLK_SRC_CDREX */ 245#define MUX_MCLK_CDR_MSPLL (1 << 4) 246#define MUX_BPLL_SEL_FOUTBPLL (1 << 0) 247#define BPLL_SEL_MASK 0x7 248#define FOUTBPLL 2 249 250#define DDR3PHY_CTRL_PHY_RESET (1 << 0) 251#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) 252 253#define PHY_CON0_RESET_VAL 0x17020a40 254#define P0_CMD_EN (1 << 14) 255#define BYTE_RDLVL_EN (1 << 13) 256#define CTRL_SHGATE (1 << 8) 257 258#define PHY_CON1_RESET_VAL 0x09210100 259#define RDLVL_PASS_ADJ_VAL 0x6 260#define RDLVL_PASS_ADJ_OFFSET 16 261#define CTRL_GATEDURADJ_MASK (0xf << 20) 262#define READ_LEVELLING_DDR3 0x0100 263 264#define PHY_CON2_RESET_VAL 0x00010004 265#define INIT_DESKEW_EN (1 << 6) 266#define DLL_DESKEW_EN (1 << 12) 267#define RDLVL_GATE_EN (1 << 24) 268#define RDLVL_EN (1 << 25) 269#define RDLVL_INCR_ADJ (0x1 << 16) 270 271/* DREX_PAUSE */ 272#define DREX_PAUSE_EN (1 << 0) 273 274#define BYPASS_EN (1 << 22) 275 276/* MEMMORY VAL */ 277#define PHY_CON0_VAL 0x17021A00 278 279#define PHY_CON12_RESET_VAL 0x10100070 280#define PHY_CON12_VAL 0x10107F50 281#define CTRL_START (1 << 6) 282#define CTRL_DLL_ON (1 << 5) 283#define CTRL_LOCK_COARSE_OFFSET 10 284#define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET) 285#define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \ 286 CTRL_LOCK_COARSE_OFFSET) 287#define CTRL_FORCE_MASK (0x7F << 8) 288#define CTRL_FINE_LOCKED 0x7 289 290#define CTRL_OFFSETD_RESET_VAL 0x8 291#define CTRL_OFFSETD_VAL 0x7F 292 293#define CTRL_OFFSETR0 0x7F 294#define CTRL_OFFSETR1 0x7F 295#define CTRL_OFFSETR2 0x7F 296#define CTRL_OFFSETR3 0x7F 297#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \ 298 CTRL_OFFSETR1 << 8 | \ 299 CTRL_OFFSETR2 << 16 | \ 300 CTRL_OFFSETR3 << 24) 301#define PHY_CON4_RESET_VAL 0x08080808 302 303#define CTRL_OFFSETW0 0x7F 304#define CTRL_OFFSETW1 0x7F 305#define CTRL_OFFSETW2 0x7F 306#define CTRL_OFFSETW3 0x7F 307#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \ 308 CTRL_OFFSETW1 << 8 | \ 309 CTRL_OFFSETW2 << 16 | \ 310 CTRL_OFFSETW3 << 24) 311#define PHY_CON6_RESET_VAL 0x08080808 312 313#define PHY_CON14_RESET_VAL 0x001F0000 314#define CTRL_PULLD_DQS 0xF 315#define CTRL_PULLD_DQS_OFFSET 0 316 317/* ZQ Configurations */ 318#define PHY_CON16_RESET_VAL 0x08000304 319 320#define ZQ_CLK_EN (1 << 27) 321#define ZQ_CLK_DIV_EN (1 << 18) 322#define ZQ_MANUAL_STR (1 << 1) 323#define ZQ_DONE (1 << 0) 324#define ZQ_MODE_DDS_OFFSET 24 325 326#define CTRL_RDLVL_GATE_ENABLE 1 327#define CTRL_RDLVL_GATE_DISABLE 0 328#define CTRL_RDLVL_DATA_ENABLE 2 329 330/* Direct Command */ 331#define DIRECT_CMD_NOP 0x07000000 332#define DIRECT_CMD_PALL 0x01000000 333#define DIRECT_CMD_ZQINIT 0x0a000000 334#define DIRECT_CMD_CHANNEL_SHIFT 28 335#define DIRECT_CMD_CHIP_SHIFT 20 336#define DIRECT_CMD_BANK_SHIFT 16 337#define DIRECT_CMD_REFA (5 << 24) 338#define DIRECT_CMD_MRS1 0x71C00 339#define DIRECT_CMD_MRS2 0x10BFC 340#define DIRECT_CMD_MRS3 0x0050C 341#define DIRECT_CMD_MRS4 0x00868 342#define DIRECT_CMD_MRS5 0x00C04 343 344/* Drive Strength */ 345#define IMPEDANCE_48_OHM 4 346#define IMPEDANCE_40_OHM 5 347#define IMPEDANCE_34_OHM 6 348#define IMPEDANCE_30_OHM 7 349#define PHY_CON39_VAL_48_OHM 0x09240924 350#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D 351#define PHY_CON39_VAL_34_OHM 0x0DB60DB6 352#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF 353 354#define CTRL_BSTLEN_OFFSET 8 355#define CTRL_RDLAT_OFFSET 0 356 357#define CMD_DEFAULT_LPDDR3 0xF 358#define CMD_DEFUALT_OFFSET 0 359#define T_WRDATA_EN 0x7 360#define T_WRDATA_EN_DDR3 0x8 361#define T_WRDATA_EN_OFFSET 16 362#define T_WRDATA_EN_MASK 0x1f 363 364#define PHY_CON31_VAL 0x0C183060 365#define PHY_CON32_VAL 0x60C18306 366#define PHY_CON33_VAL 0x00000030 367 368#define PHY_CON31_RESET_VAL 0x0 369#define PHY_CON32_RESET_VAL 0x0 370#define PHY_CON33_RESET_VAL 0x0 371 372#define SL_DLL_DYN_CON_EN (1 << 1) 373#define FP_RESYNC (1 << 3) 374#define CTRL_START (1 << 6) 375 376#define DMC_AREF_EN (1 << 5) 377#define DMC_CONCONTROL_EMPTY (1 << 8) 378#define DFI_INIT_START (1 << 28) 379 380#define DMC_MEMCONTROL_VAL 0x00312700 381#define CLK_STOP_EN (1 << 0) 382#define DPWRDN_EN (1 << 1) 383#define DSREF_EN (1 << 5) 384 385#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0 386#define MEMBASECONFIG_CHIP_MASK_OFFSET 0 387#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20 388#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40 389#define CHIP_BASE_OFFSET 16 390 391#define MEMCONFIG_VAL 0x1323 392#define PRECHCONFIG_DEFAULT_VAL 0xFF000000 393#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF 394 395#define TIMINGAREF_VAL 0x5d 396#define TIMINGROW_VAL 0x345A8692 397#define TIMINGDATA_VAL 0x3630065C 398#define TIMINGPOWER_VAL 0x50380336 399#define DFI_INIT_COMPLETE (1 << 3) 400 401#define BRBRSVCONTROL_VAL 0x00000033 402#define BRBRSVCONFIG_VAL 0x88778877 403 404/* Clock Gating Control (CGCONTROL) register */ 405#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */ 406#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */ 407#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */ 408#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */ 409#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \ 410 BUSIF_WR_CG_EN | BUSIF_RD_CG_EN) 411 412/* DMC PHY Control0 register */ 413#define PHY_CONTROL0_RESET_VAL 0x0 414#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ 415#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */ 416#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */ 417#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */ 418 419/* Driver strength for CK, CKE, CS & CA */ 420#define IMP_OUTPUT_DRV_40_OHM 0x5 421#define IMP_OUTPUT_DRV_30_OHM 0x7 422#define DA_3_DS_OFFSET 25 423#define DA_2_DS_OFFSET 22 424#define DA_1_DS_OFFSET 19 425#define DA_0_DS_OFFSET 16 426#define CA_CK_DRVR_DS_OFFSET 9 427#define CA_CKE_DRVR_DS_OFFSET 6 428#define CA_CS_DRVR_DS_OFFSET 3 429#define CA_ADR_DRVR_DS_OFFSET 0 430 431#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 432#define PHY_CON42_CTRL_RDLAT_SHIFT 0 433 434/* 435 * Definitions that differ with SoC's. 436 * Below is the part defining macros for Exynos5250. 437 * Else part introduces macros for Exynos5420. 438 */ 439#ifndef CONFIG_EXYNOS5420 440 441/* APLL_CON1 */ 442#define APLL_CON1_VAL (0x00203800) 443 444/* MPLL_CON1 */ 445#define MPLL_CON1_VAL (0x00203800) 446 447/* CPLL_CON1 */ 448#define CPLL_CON1_VAL (0x00203800) 449 450/* DPLL_CON1 */ 451#define DPLL_CON1_VAL (NOT_AVAILABLE) 452 453/* GPLL_CON1 */ 454#define GPLL_CON1_VAL (0x00203800) 455 456/* EPLL_CON1, CON2 */ 457#define EPLL_CON1_VAL 0x00000000 458#define EPLL_CON2_VAL 0x00000080 459 460/* VPLL_CON1, CON2 */ 461#define VPLL_CON1_VAL 0x00000000 462#define VPLL_CON2_VAL 0x00000080 463 464/* RPLL_CON1, CON2 */ 465#define RPLL_CON1_VAL NOT_AVAILABLE 466#define RPLL_CON2_VAL NOT_AVAILABLE 467 468/* BPLL_CON1 */ 469#define BPLL_CON1_VAL 0x00203800 470 471/* SPLL_CON1 */ 472#define SPLL_CON1_VAL NOT_AVAILABLE 473 474/* IPLL_CON1 */ 475#define IPLL_CON1_VAL NOT_AVAILABLE 476 477/* KPLL_CON1 */ 478#define KPLL_CON1_VAL NOT_AVAILABLE 479 480/* CLK_SRC_ISP */ 481#define CLK_SRC_ISP_VAL NOT_AVAILABLE 482#define CLK_DIV_ISP0_VAL 0x31 483#define CLK_DIV_ISP1_VAL 0x0 484 485/* CLK_FSYS */ 486#define CLK_SRC_FSYS0_VAL 0x66666 487#define CLK_DIV_FSYS0_VAL 0x0BB00000 488#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE 489#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE 490 491/* CLK_SRC_CPU */ 492/* 0 = MOUTAPLL, 1 = SCLKMPLL */ 493#define MUX_HPM_SEL 0 494#define MUX_CPU_SEL 0 495#define MUX_APLL_SEL 1 496 497#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ 498 | (MUX_CPU_SEL << 16) \ 499 | (MUX_APLL_SEL)) 500 501/* CLK_SRC_CDREX */ 502#define CLK_SRC_CDREX_VAL 0x1 503 504/* CLK_DIV_CDREX */ 505#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE 506#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE 507 508/* CLK_DIV_CPU0_VAL */ 509#define CLK_DIV_CPU0_VAL NOT_AVAILABLE 510 511#define MCLK_CDREX2_RATIO 0x0 512#define ACLK_EFCON_RATIO 0x1 513#define MCLK_DPHY_RATIO 0x1 514#define MCLK_CDREX_RATIO 0x1 515#define ACLK_C2C_200_RATIO 0x1 516#define C2C_CLK_400_RATIO 0x1 517#define PCLK_CDREX_RATIO 0x1 518#define ACLK_CDREX_RATIO 0x1 519 520#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \ 521 | (C2C_CLK_400_RATIO << 6) \ 522 | (PCLK_CDREX_RATIO << 4) \ 523 | (ACLK_CDREX_RATIO)) 524 525/* CLK_SRC_TOP0 */ 526#define MUX_ACLK_300_GSCL_SEL 0x0 527#define MUX_ACLK_300_GSCL_MID_SEL 0x0 528#define MUX_ACLK_400_G3D_MID_SEL 0x0 529#define MUX_ACLK_333_SEL 0x0 530#define MUX_ACLK_300_DISP1_SEL 0x0 531#define MUX_ACLK_300_DISP1_MID_SEL 0x0 532#define MUX_ACLK_200_SEL 0x0 533#define MUX_ACLK_166_SEL 0x0 534#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \ 535 | (MUX_ACLK_300_GSCL_MID_SEL << 24) \ 536 | (MUX_ACLK_400_G3D_MID_SEL << 20) \ 537 | (MUX_ACLK_333_SEL << 16) \ 538 | (MUX_ACLK_300_DISP1_SEL << 15) \ 539 | (MUX_ACLK_300_DISP1_MID_SEL << 14) \ 540 | (MUX_ACLK_200_SEL << 12) \ 541 | (MUX_ACLK_166_SEL << 8)) 542 543/* CLK_SRC_TOP1 */ 544#define MUX_ACLK_400_G3D_SEL 0x1 545#define MUX_ACLK_400_ISP_SEL 0x0 546#define MUX_ACLK_400_IOP_SEL 0x0 547#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 548#define MUX_ACLK_300_GSCL_MID1_SEL 0x0 549#define MUX_ACLK_300_DISP1_MID1_SEL 0x0 550#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ 551 |(MUX_ACLK_400_ISP_SEL << 24) \ 552 |(MUX_ACLK_400_IOP_SEL << 20) \ 553 |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \ 554 |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \ 555 |(MUX_ACLK_300_DISP1_MID1_SEL << 8)) 556 557/* CLK_SRC_TOP2 */ 558#define MUX_GPLL_SEL 0x1 559#define MUX_BPLL_USER_SEL 0x0 560#define MUX_MPLL_USER_SEL 0x0 561#define MUX_VPLL_SEL 0x1 562#define MUX_EPLL_SEL 0x1 563#define MUX_CPLL_SEL 0x1 564#define VPLLSRC_SEL 0x0 565#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \ 566 | (MUX_BPLL_USER_SEL << 24) \ 567 | (MUX_MPLL_USER_SEL << 20) \ 568 | (MUX_VPLL_SEL << 16) \ 569 | (MUX_EPLL_SEL << 12) \ 570 | (MUX_CPLL_SEL << 8) \ 571 | (VPLLSRC_SEL)) 572/* CLK_SRC_TOP3 */ 573#define MUX_ACLK_333_SUB_SEL 0x1 574#define MUX_ACLK_400_SUB_SEL 0x1 575#define MUX_ACLK_266_ISP_SUB_SEL 0x1 576#define MUX_ACLK_266_GPS_SUB_SEL 0x0 577#define MUX_ACLK_300_GSCL_SUB_SEL 0x1 578#define MUX_ACLK_266_GSCL_SUB_SEL 0x1 579#define MUX_ACLK_300_DISP1_SUB_SEL 0x1 580#define MUX_ACLK_200_DISP1_SUB_SEL 0x1 581#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \ 582 | (MUX_ACLK_400_SUB_SEL << 20) \ 583 | (MUX_ACLK_266_ISP_SUB_SEL << 16) \ 584 | (MUX_ACLK_266_GPS_SUB_SEL << 12) \ 585 | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \ 586 | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \ 587 | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ 588 | (MUX_ACLK_200_DISP1_SUB_SEL << 4)) 589 590#define CLK_SRC_TOP4_VAL NOT_AVAILABLE 591#define CLK_SRC_TOP5_VAL NOT_AVAILABLE 592#define CLK_SRC_TOP6_VAL NOT_AVAILABLE 593#define CLK_SRC_TOP7_VAL NOT_AVAILABLE 594 595/* CLK_DIV_TOP0 */ 596#define ACLK_300_DISP1_RATIO 0x2 597#define ACLK_400_G3D_RATIO 0x0 598#define ACLK_333_RATIO 0x0 599#define ACLK_266_RATIO 0x2 600#define ACLK_200_RATIO 0x3 601#define ACLK_166_RATIO 0x1 602#define ACLK_133_RATIO 0x1 603#define ACLK_66_RATIO 0x5 604 605#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \ 606 | (ACLK_400_G3D_RATIO << 24) \ 607 | (ACLK_333_RATIO << 20) \ 608 | (ACLK_266_RATIO << 16) \ 609 | (ACLK_200_RATIO << 12) \ 610 | (ACLK_166_RATIO << 8) \ 611 | (ACLK_133_RATIO << 4) \ 612 | (ACLK_66_RATIO)) 613 614/* CLK_DIV_TOP1 */ 615#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3 616#define ACLK_66_PRE_RATIO 0x1 617#define ACLK_400_ISP_RATIO 0x1 618#define ACLK_400_IOP_RATIO 0x1 619#define ACLK_300_GSCL_RATIO 0x2 620 621#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \ 622 | (ACLK_66_PRE_RATIO << 24) \ 623 | (ACLK_400_ISP_RATIO << 20) \ 624 | (ACLK_400_IOP_RATIO << 16) \ 625 | (ACLK_300_GSCL_RATIO << 12)) 626 627#define CLK_DIV_TOP2_VAL NOT_AVAILABLE 628 629/* PLL Lock Value Factor */ 630#define PLL_LOCK_FACTOR 250 631#define PLL_X_LOCK_FACTOR 3000 632 633/* CLK_SRC_PERIC0 */ 634#define PWM_SEL 6 635#define UART3_SEL 6 636#define UART2_SEL 6 637#define UART1_SEL 6 638#define UART0_SEL 6 639/* SRC_CLOCK = SCLK_MPLL */ 640#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ 641 | (UART3_SEL << 12) \ 642 | (UART2_SEL << 8) \ 643 | (UART1_SEL << 4) \ 644 | (UART0_SEL)) 645 646/* CLK_SRC_PERIC1 */ 647/* SRC_CLOCK = SCLK_MPLL */ 648#define SPI0_SEL 6 649#define SPI1_SEL 6 650#define SPI2_SEL 6 651#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \ 652 | (SPI1_SEL << 20) \ 653 | (SPI0_SEL << 16)) 654 655/* CLK_DIV_PERIL0 */ 656#define UART5_RATIO 7 657#define UART4_RATIO 7 658#define UART3_RATIO 7 659#define UART2_RATIO 7 660#define UART1_RATIO 7 661#define UART0_RATIO 7 662 663#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ 664 | (UART2_RATIO << 8) \ 665 | (UART1_RATIO << 4) \ 666 | (UART0_RATIO)) 667/* CLK_DIV_PERIC1 */ 668#define SPI1_RATIO 0x7 669#define SPI0_RATIO 0xf 670#define SPI1_SUB_RATIO 0x0 671#define SPI0_SUB_RATIO 0x0 672#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \ 673 | ((SPI1_RATIO << 16) \ 674 | (SPI0_SUB_RATIO << 8) \ 675 | (SPI0_RATIO << 0))) 676 677/* CLK_DIV_PERIC2 */ 678#define SPI2_RATIO 0xf 679#define SPI2_SUB_RATIO 0x0 680#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \ 681 | (SPI2_RATIO << 0)) 682 683/* CLK_DIV_PERIC3 */ 684#define PWM_RATIO 8 685#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0) 686 687 688/* CLK_DIV_PERIC4 */ 689#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE 690 691/* CLK_SRC_DISP1_0 */ 692#define CLK_SRC_DISP1_0_VAL 0x6 693#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE 694 695#define APLL_FOUT (1 << 0) 696#define KPLL_FOUT NOT_AVAILABLE 697 698#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE 699 700#else 701 702#define CPU_CONFIG_STATUS_OFFSET 0x80 703#define CPU_RST_FLAG_VAL 0xFCBA0D10 704#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000 705 706/* APLL_CON1 */ 707#define APLL_CON1_VAL (0x0020F300) 708 709/* MPLL_CON1 */ 710#define MPLL_CON1_VAL (0x0020F300) 711 712 713/* CPLL_CON1 */ 714#define CPLL_CON1_VAL 0x0020f300 715 716/* DPLL_CON1 */ 717#define DPLL_CON1_VAL (0x0020F300) 718 719/* GPLL_CON1 */ 720#define GPLL_CON1_VAL (NOT_AVAILABLE) 721 722 723/* EPLL_CON1, CON2 */ 724#define EPLL_CON1_VAL 0x00000000 725#define EPLL_CON2_VAL 0x00000080 726 727/* VPLL_CON1, CON2 */ 728#define VPLL_CON1_VAL 0x0020f300 729#define VPLL_CON2_VAL NOT_AVAILABLE 730 731/* RPLL_CON1, CON2 */ 732#define RPLL_CON1_VAL 0x00000000 733#define RPLL_CON2_VAL 0x00000080 734 735/* BPLL_CON1 */ 736#define BPLL_CON1_VAL 0x0020f300 737 738/* SPLL_CON1 */ 739#define SPLL_CON1_VAL 0x0020f300 740 741/* IPLL_CON1 */ 742#define IPLL_CON1_VAL 0x00000080 743 744/* KPLL_CON1 */ 745#define KPLL_CON1_VAL 0x200000 746 747/* CLK_SRC_ISP */ 748#define CLK_SRC_ISP_VAL 0x33366000 749#define CLK_DIV_ISP0_VAL 0x13131300 750#define CLK_DIV_ISP1_VAL 0xbb110202 751 752 753/* CLK_FSYS */ 754#define CLK_SRC_FSYS0_VAL 0x33033300 755#define CLK_DIV_FSYS0_VAL 0x0 756#define CLK_DIV_FSYS1_VAL 0x04f13c4f 757#define CLK_DIV_FSYS2_VAL 0x041d0000 758 759/* CLK_SRC_CPU */ 760/* 0 = MOUTAPLL, 1 = SCLKMPLL */ 761#define MUX_HPM_SEL 1 762#define MUX_CPU_SEL 0 763#define MUX_APLL_SEL 1 764 765#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ 766 | (MUX_CPU_SEL << 16) \ 767 | (MUX_APLL_SEL)) 768 769/* CLK_SRC_CDREX */ 770#define CLK_SRC_CDREX_VAL 0x00000011 771 772/* CLK_DIV_CDREX */ 773#define CLK_DIV_CDREX0_VAL 0x30010100 774#define CLK_DIV_CDREX1_VAL 0x300 775 776#define CLK_DIV_CDREX_VAL 0x17010100 777 778/* CLK_DIV_CPU0_VAL */ 779#define CLK_DIV_CPU0_VAL 0x01440020 780 781/* CLK_SRC_TOP */ 782#define CLK_SRC_TOP0_VAL 0x12221222 783#define CLK_SRC_TOP1_VAL 0x00100200 784#define CLK_SRC_TOP2_VAL 0x11101000 785#define CLK_SRC_TOP3_VAL 0x11111111 786#define CLK_SRC_TOP4_VAL 0x11110111 787#define CLK_SRC_TOP5_VAL 0x11111101 788#define CLK_SRC_TOP6_VAL 0x11110111 789#define CLK_SRC_TOP7_VAL 0x00022200 790 791/* CLK_DIV_TOP */ 792#define CLK_DIV_TOP0_VAL 0x23712311 793#define CLK_DIV_TOP1_VAL 0x13100B00 794#define CLK_DIV_TOP2_VAL 0x11101100 795 796/* PLL Lock Value Factor */ 797#define PLL_LOCK_FACTOR 200 798#define PLL_X_LOCK_FACTOR 3000 799 800/* CLK_SRC_PERIC0 */ 801#define SPDIF_SEL 1 802#define PWM_SEL 3 803#define UART4_SEL 3 804#define UART3_SEL 3 805#define UART2_SEL 3 806#define UART1_SEL 3 807#define UART0_SEL 3 808/* SRC_CLOCK = SCLK_RPLL */ 809#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \ 810 | (PWM_SEL << 24) \ 811 | (UART4_SEL << 20) \ 812 | (UART3_SEL << 16) \ 813 | (UART2_SEL << 12) \ 814 | (UART1_SEL << 8) \ 815 | (UART0_SEL << 4)) 816 817/* CLK_SRC_PERIC1 */ 818/* SRC_CLOCK = SCLK_EPLL */ 819#define SPI0_SEL 6 820#define SPI1_SEL 6 821#define SPI2_SEL 6 822#define AUDIO0_SEL 6 823#define AUDIO1_SEL 6 824#define AUDIO2_SEL 6 825#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \ 826 | (SPI1_SEL << 24) \ 827 | (SPI0_SEL << 20) \ 828 | (AUDIO2_SEL << 16) \ 829 | (AUDIO2_SEL << 12) \ 830 | (AUDIO2_SEL << 8)) 831 832/* CLK_DIV_PERIC0 */ 833#define PWM_RATIO 8 834#define UART4_RATIO 9 835#define UART3_RATIO 9 836#define UART2_RATIO 9 837#define UART1_RATIO 9 838#define UART0_RATIO 9 839 840#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \ 841 | (UART4_RATIO << 24) \ 842 | (UART3_RATIO << 20) \ 843 | (UART2_RATIO << 16) \ 844 | (UART1_RATIO << 12) \ 845 | (UART0_RATIO << 8)) 846/* CLK_DIV_PERIC1 */ 847#define SPI2_RATIO 0x1 848#define SPI1_RATIO 0x1 849#define SPI0_RATIO 0x1 850#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \ 851 | (SPI1_RATIO << 24) \ 852 | (SPI0_RATIO << 20)) 853 854/* CLK_DIV_PERIC2 */ 855#define PCM2_RATIO 0x3 856#define PCM1_RATIO 0x3 857#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \ 858 | (PCM1_RATIO << 16)) 859 860/* CLK_DIV_PERIC3 */ 861#define AUDIO2_RATIO 0x5 862#define AUDIO1_RATIO 0x5 863#define AUDIO0_RATIO 0x5 864#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \ 865 | (AUDIO1_RATIO << 24) \ 866 | (AUDIO0_RATIO << 20)) 867 868/* CLK_DIV_PERIC4 */ 869#define SPI2_PRE_RATIO 0x2 870#define SPI1_PRE_RATIO 0x2 871#define SPI0_PRE_RATIO 0x2 872#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \ 873 | (SPI1_PRE_RATIO << 16) \ 874 | (SPI0_PRE_RATIO << 8)) 875 876/* CLK_SRC_DISP1_0 */ 877#define CLK_SRC_DISP1_0_VAL 0x10666600 878#define CLK_DIV_DISP1_0_VAL 0x01050211 879 880#define APLL_FOUT (1 << 0) 881#define KPLL_FOUT (1 << 0) 882 883#define CLK_DIV_CPERI1_VAL 0x3f3f0000 884#endif 885 886struct mem_timings; 887 888/* Errors that we can encourter in low-level setup */ 889enum { 890 SETUP_ERR_OK, 891 SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1, 892 SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2, 893}; 894 895/* 896 * Memory variant specific initialization code for DDR3 897 * 898 * @param mem Memory timings for this memory type. 899 * @param reset Reset DDR PHY during initialization. 900 * Return: 0 if ok, SETUP_ERR_... if there is a problem 901 */ 902int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset); 903 904/* Memory variant specific initialization code for LPDDR3 */ 905void lpddr3_mem_ctrl_init(void); 906 907/* 908 * Configure ZQ I/O interface 909 * 910 * @param mem Memory timings for this memory type. 911 * @param phy0_con16 Register address for dmc_phy0->phy_con16 912 * @param phy1_con16 Register address for dmc_phy1->phy_con16 913 * @param phy0_con17 Register address for dmc_phy0->phy_con17 914 * @param phy1_con17 Register address for dmc_phy1->phy_con17 915 * Return: 0 if ok, -1 on error 916 */ 917int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16, 918 uint32_t *phy1_con16, uint32_t *phy0_con17, 919 uint32_t *phy1_con17); 920/* 921 * Send NOP and MRS/EMRS Direct commands 922 * 923 * @param mem Memory timings for this memory type. 924 * @param directcmd Register address for dmc_phy->directcmd 925 */ 926void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd); 927 928/* 929 * Send PALL Direct commands 930 * 931 * @param mem Memory timings for this memory type. 932 * @param directcmd Register address for dmc_phy->directcmd 933 */ 934void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd); 935 936/* 937 * Reset the DLL. This function is common between DDR3 and LPDDR2. 938 * However, the reset value is different. So we are passing a flag 939 * ddr_mode to distinguish between LPDDR2 and DDR3. 940 * 941 * @param phycontrol0 Register address for dmc_phy->phycontrol0 942 * @param ddr_mode Type of DDR memory 943 */ 944void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode); 945#endif 946