1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
4 *
5 * Copyright (C) 2010 Texas Instruments Incorporated
6 */
7
8#ifndef _SDMMC_DEFS_H_
9#define _SDMMC_DEFS_H_
10
11#include <asm/arch/hardware.h>
12
13/* MMC Control Reg fields */
14#define MMCCTL_DATRST		(1 << 0)
15#define MMCCTL_CMDRST		(1 << 1)
16#define MMCCTL_WIDTH_4_BIT	(1 << 2)
17#define MMCCTL_DATEG_DISABLED	(0 << 6)
18#define MMCCTL_DATEG_RISING	(1 << 6)
19#define MMCCTL_DATEG_FALLING	(2 << 6)
20#define MMCCTL_DATEG_BOTH	(3 << 6)
21#define MMCCTL_PERMDR_LE	(0 << 9)
22#define MMCCTL_PERMDR_BE	(1 << 9)
23#define MMCCTL_PERMDX_LE	(0 << 10)
24#define MMCCTL_PERMDX_BE	(1 << 10)
25
26/* MMC Clock Control Reg fields */
27#define MMCCLK_CLKEN		(1 << 8)
28#define MMCCLK_CLKRT_MASK	(0xFF << 0)
29
30/* MMC Status Reg0 fields */
31#define MMCST0_DATDNE		(1 << 0)
32#define MMCST0_BSYDNE		(1 << 1)
33#define MMCST0_RSPDNE		(1 << 2)
34#define MMCST0_TOUTRD		(1 << 3)
35#define MMCST0_TOUTRS		(1 << 4)
36#define MMCST0_CRCWR		(1 << 5)
37#define MMCST0_CRCRD		(1 << 6)
38#define MMCST0_CRCRS		(1 << 7)
39#define MMCST0_DXRDY		(1 << 9)
40#define MMCST0_DRRDY		(1 << 10)
41#define MMCST0_DATED		(1 << 11)
42#define MMCST0_TRNDNE		(1 << 12)
43
44#define MMCST0_ERR_MASK		(0x00F8)
45
46/* MMC Status Reg1 fields */
47#define MMCST1_BUSY		(1 << 0)
48#define MMCST1_CLKSTP		(1 << 1)
49#define MMCST1_DXEMP		(1 << 2)
50#define MMCST1_DRFUL		(1 << 3)
51#define MMCST1_DAT3ST		(1 << 4)
52#define MMCST1_FIFOEMP		(1 << 5)
53#define MMCST1_FIFOFUL		(1 << 6)
54
55/* MMC INT Mask Reg fields */
56#define MMCIM_EDATDNE		(1 << 0)
57#define MMCIM_EBSYDNE		(1 << 1)
58#define MMCIM_ERSPDNE		(1 << 2)
59#define MMCIM_ETOUTRD		(1 << 3)
60#define MMCIM_ETOUTRS		(1 << 4)
61#define MMCIM_ECRCWR		(1 << 5)
62#define MMCIM_ECRCRD		(1 << 6)
63#define MMCIM_ECRCRS		(1 << 7)
64#define MMCIM_EDXRDY		(1 << 9)
65#define MMCIM_EDRRDY		(1 << 10)
66#define MMCIM_EDATED		(1 << 11)
67#define MMCIM_ETRNDNE		(1 << 12)
68
69#define MMCIM_MASKALL		(0xFFFFFFFF)
70
71/* MMC Resp Tout Reg fields */
72#define MMCTOR_TOR_MASK		(0xFF)		/* dont write to reg, | it */
73#define MMCTOR_TOD_20_16_SHIFT  (8)
74
75/* MMC Data Read Tout Reg fields */
76#define MMCTOD_TOD_0_15_MASK	(0xFFFF)
77
78/* MMC Block len Reg fields */
79#define MMCBLEN_BLEN_MASK	(0xFFF)
80
81/* MMC Num Blocks Reg fields */
82#define MMCNBLK_NBLK_MASK	(0xFFFF)
83#define MMCNBLK_NBLK_MAX	(0xFFFF)
84
85/* MMC Num Blocks Counter Reg fields */
86#define MMCNBLC_NBLC_MASK	(0xFFFF)
87
88/* MMC Cmd Reg fields */
89#define MMCCMD_CMD_MASK		(0x3F)
90#define MMCCMD_PPLEN		(1 << 7)
91#define MMCCMD_BSYEXP		(1 << 8)
92#define MMCCMD_RSPFMT_NONE	(0 << 9)
93#define MMCCMD_RSPFMT_R1567	(1 << 9)
94#define MMCCMD_RSPFMT_R2	(2 << 9)
95#define MMCCMD_RSPFMT_R3	(3 << 9)
96#define MMCCMD_DTRW		(1 << 11)
97#define MMCCMD_STRMTP		(1 << 12)
98#define MMCCMD_WDATX		(1 << 13)
99#define MMCCMD_INITCK		(1 << 14)
100#define MMCCMD_DCLR		(1 << 15)
101#define MMCCMD_DMATRIG		(1 << 16)
102
103/* FIFO control Reg fields */
104#define MMCFIFOCTL_FIFORST	(1 << 0)
105#define MMCFIFOCTL_FIFODIR	(1 << 1)
106#define MMCFIFOCTL_FIFOLEV	(1 << 2)
107#define MMCFIFOCTL_ACCWD_4	(0 << 3)	/* access width of 4 bytes */
108#define MMCFIFOCTL_ACCWD_3	(1 << 3)	/* access width of 3 bytes */
109#define MMCFIFOCTL_ACCWD_2	(2 << 3)	/* access width of 2 bytes */
110#define MMCFIFOCTL_ACCWD_1	(3 << 3)	/* access width of 1 byte */
111
112/* Davinci MMC Register definitions */
113struct davinci_mmc_regs {
114	dv_reg mmcctl;
115	dv_reg mmcclk;
116	dv_reg mmcst0;
117	dv_reg mmcst1;
118	dv_reg mmcim;
119	dv_reg mmctor;
120	dv_reg mmctod;
121	dv_reg mmcblen;
122	dv_reg mmcnblk;
123	dv_reg mmcnblc;
124	dv_reg mmcdrr;
125	dv_reg mmcdxr;
126	dv_reg mmccmd;
127	dv_reg mmcarghl;
128	dv_reg mmcrsp01;
129	dv_reg mmcrsp23;
130	dv_reg mmcrsp45;
131	dv_reg mmcrsp67;
132	dv_reg mmcdrsp;
133	dv_reg mmcetok;
134	dv_reg mmccidx;
135	dv_reg mmcckc;
136	dv_reg mmctorc;
137	dv_reg mmctodc;
138	dv_reg mmcblnc;
139	dv_reg sdioctl;
140	dv_reg sdiost0;
141	dv_reg sdioien;
142	dv_reg sdioist;
143	dv_reg mmcfifoctl;
144};
145
146/* Davinci MMC board definitions */
147struct davinci_mmc {
148	struct davinci_mmc_regs *reg_base;	/* Register base address */
149	uint input_clk;		/* Input clock to MMC controller */
150	uint host_caps;		/* Host capabilities */
151	uint voltages;		/* Host supported voltages */
152	struct mmc_config cfg;
153};
154
155#define DAVINCI_MAX_BLOCKS	(32)
156struct davinci_mmc_plat {
157	struct davinci_mmc_regs *reg_base;	/* Register base address */
158	struct mmc_config cfg;
159	struct mmc mmc;
160};
161
162int davinci_mmc_init(struct bd_info *bis, struct davinci_mmc *host);
163
164#endif /* _SDMMC_DEFS_H */
165