1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Chip-specific header file for the SAMA5D3 family 4 * 5 * (C) 2012 - 2013 Atmel Corporation. 6 * Bo Shen <voice.shen@atmel.com> 7 * 8 * Definitions for the SoC: 9 * SAMA5D3 10 */ 11 12#ifndef SAMA5D3_H 13#define SAMA5D3_H 14 15/* 16 * Peripheral identifiers/interrupts. 17 */ 18#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 19#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ 20#define ATMEL_ID_DBGU 2 /* Debug Unit Interrupt */ 21#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */ 22#define ATMEL_ID_WDT 4 /* Watchdog timer Interrupt */ 23#define ATMEL_ID_SMC 5 /* Multi-bit ECC Interrupt */ 24#define ATMEL_ID_PIOA 6 /* Parallel I/O Controller A */ 25#define ATMEL_ID_PIOB 7 /* Parallel I/O Controller B */ 26#define ATMEL_ID_PIOC 8 /* Parallel I/O Controller C */ 27#define ATMEL_ID_PIOD 9 /* Parallel I/O Controller D */ 28#define ATMEL_ID_PIOE 10 /* Parallel I/O Controller E */ 29#define ATMEL_ID_SMD 11 /* SMD Soft Modem */ 30#define ATMEL_ID_USART0 12 /* USART 0 */ 31#define ATMEL_ID_USART1 13 /* USART 1 */ 32#define ATMEL_ID_USART2 14 /* USART 2 */ 33#define ATMEL_ID_USART3 15 /* USART 3 */ 34#define ATMEL_ID_UART0 16 35#define ATMEL_ID_UART1 17 36#define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */ 37#define ATMEL_ID_TWI1 19 /* Two-Wire Interface 1 */ 38#define ATMEL_ID_TWI2 20 /* Two-Wire Interface 2 */ 39#define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */ 40#define ATMEL_ID_MCI1 22 /* */ 41#define ATMEL_ID_MCI2 23 /* */ 42#define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */ 43#define ATMEL_ID_SPI1 25 /* Serial Peripheral Interface 1 */ 44#define ATMEL_ID_TC0 26 /* */ 45#define ATMEL_ID_TC1 27 /* */ 46#define ATMEL_ID_PWMC 28 /* Pulse Width Modulation Controller */ 47#define ATMEL_ID_TSC 29 /* Touch Screen ADC Controller */ 48#define ATMEL_ID_DMA0 30 /* DMA Controller */ 49#define ATMEL_ID_DMA1 31 /* DMA Controller */ 50#define ATMEL_ID_UHPHS 32 /* USB Host High Speed */ 51#define ATMEL_ID_UDPHS 33 /* USB Device High Speed */ 52#define ATMEL_ID_GMAC 34 53#define ATMEL_ID_EMAC 35 /* Ethernet MAC */ 54#define ATMEL_ID_LCDC 36 /* LCD Controller */ 55#define ATMEL_ID_ISI 37 /* Image Sensor Interface */ 56#define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */ 57#define ATMEL_ID_SSC1 39 /* Synchronous Serial Controller 1 */ 58#define ATMEL_ID_CAN0 40 59#define ATMEL_ID_CAN1 41 60#define ATMEL_ID_SHA 42 61#define ATMEL_ID_AES 43 62#define ATMEL_ID_TDES 44 63#define ATMEL_ID_TRNG 45 64#define ATMEL_ID_ARM 46 65#define ATMEL_ID_IRQ0 47 /* Advanced Interrupt Controller */ 66#define ATMEL_ID_FUSE 48 67#define ATMEL_ID_MPDDRC 49 68 69/* sama5d3 series chip id definitions */ 70#define ARCH_ID_SAMA5D3 0x8a5c07c0 71#define ARCH_EXID_SAMA5D31 0x00444300 72#define ARCH_EXID_SAMA5D33 0x00414300 73#define ARCH_EXID_SAMA5D34 0x00414301 74#define ARCH_EXID_SAMA5D35 0x00584300 75#define ARCH_EXID_SAMA5D36 0x00004301 76 77#define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3) 78#define cpu_is_sama5d31() (cpu_is_sama5d3() && \ 79 (get_extension_chip_id() == ARCH_EXID_SAMA5D31)) 80#define cpu_is_sama5d33() (cpu_is_sama5d3() && \ 81 (get_extension_chip_id() == ARCH_EXID_SAMA5D33)) 82#define cpu_is_sama5d34() (cpu_is_sama5d3() && \ 83 (get_extension_chip_id() == ARCH_EXID_SAMA5D34)) 84#define cpu_is_sama5d35() (cpu_is_sama5d3() && \ 85 (get_extension_chip_id() == ARCH_EXID_SAMA5D35)) 86#define cpu_is_sama5d36() (cpu_is_sama5d3() && \ 87 (get_extension_chip_id() == ARCH_EXID_SAMA5D36)) 88 89/* 90 * User Peripherals physical base addresses. 91 */ 92#define ATMEL_BASE_MCI0 0xf0000000 93#define ATMEL_BASE_SPI0 0xf0004000 94#define ATMEL_BASE_SSC0 0xf000C000 95#define ATMEL_BASE_TC2 0xf0010000 96#define ATMEL_BASE_TWI0 0xf0014000 97#define ATMEL_BASE_TWI1 0xf0018000 98#define ATMEL_BASE_USART0 0xf001c000 99#define ATMEL_BASE_USART1 0xf0020000 100#define ATMEL_BASE_UART0 0xf0024000 101#define ATMEL_BASE_GMAC 0xf0028000 102#define ATMEL_BASE_PWMC 0xf002c000 103#define ATMEL_BASE_LCDC 0xf0030000 104#define ATMEL_BASE_ISI 0xf0034000 105#define ATMEL_BASE_SFR 0xf0038000 106/* Reserved: 0xf003c000 - 0xf8000000 */ 107#define ATMEL_BASE_MCI1 0xf8000000 108#define ATMEL_BASE_MCI2 0xf8004000 109#define ATMEL_BASE_SPI1 0xf8008000 110#define ATMEL_BASE_SSC1 0xf800c000 111#define ATMEL_BASE_CAN1 0xf8010000 112#define ATMEL_BASE_TC3 0xf8014000 113#define ATMEL_BASE_TSADC 0xf8018000 114#define ATMEL_BASE_TWI2 0xf801c000 115#define ATMEL_BASE_USART2 0xf8020000 116#define ATMEL_BASE_USART3 0xf8024000 117#define ATMEL_BASE_UART1 0xf8028000 118#define ATMEL_BASE_EMAC 0xf802c000 119#define ATMEL_BASE_UDPHS 0xf8030000 120#define ATMEL_BASE_SHA 0xf8034000 121#define ATMEL_BASE_AES 0xf8038000 122#define ATMEL_BASE_TDES 0xf803c000 123#define ATMEL_BASE_TRNG 0xf8040000 124/* Reserved: 0xf804400 - 0xffffc00 */ 125 126/* 127 * System Peripherals physical base addresses. 128 */ 129#define ATMEL_BASE_SYS 0xffffc000 130#define ATMEL_BASE_SMC 0xffffc000 131#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070) 132#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500) 133#define ATMEL_BASE_FUSE 0xffffe400 134#define ATMEL_BASE_DMAC0 0xffffe600 135#define ATMEL_BASE_DMAC1 0xffffe800 136#define ATMEL_BASE_MPDDRC 0xffffea00 137#define ATMEL_BASE_MATRIX 0xffffec00 138#define ATMEL_BASE_DBGU 0xffffee00 139#define ATMEL_BASE_AIC 0xfffff000 140#define ATMEL_BASE_PIOA 0xfffff200 141#define ATMEL_BASE_PIOB 0xfffff400 142#define ATMEL_BASE_PIOC 0xfffff600 143#define ATMEL_BASE_PIOD 0xfffff800 144#define ATMEL_BASE_PIOE 0xfffffa00 145#define ATMEL_BASE_PMC 0xfffffc00 146#define ATMEL_BASE_RSTC 0xfffffe00 147#define ATMEL_BASE_SHDWN 0xfffffe10 148#define ATMEL_BASE_PIT 0xfffffe30 149#define ATMEL_BASE_WDT 0xfffffe40 150#define ATMEL_BASE_SCKCR 0xfffffe50 151#define ATMEL_BASE_GPBR 0xfffffe60 152#define ATMEL_BASE_RTC 0xfffffeb0 153/* Reserved: 0xfffffee0 - 0xffffffff */ 154 155#define ATMEL_CHIPID_CIDR 0xffffee40 156#define ATMEL_CHIPID_EXID 0xffffee44 157 158/* 159 * Internal Memory. 160 */ 161#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ 162#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */ 163#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM base address */ 164#define ATMEL_BASE_SRAM1 0x00310000 /* Internal SRAM base address */ 165#define ATMEL_BASE_SMD 0x00400000 /* Internal ROM base address */ 166#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ 167#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */ 168#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ 169#define ATMEL_BASE_AXI 0x00800000 /* Video Decoder Controller */ 170#define ATMEL_BASE_DAP 0x00900000 /* Video Decoder Controller */ 171 172/* 173 * External memory 174 */ 175#define ATMEL_BASE_CS0 0x10000000 176#define ATMEL_BASE_DDRCS 0x20000000 177#define ATMEL_BASE_CS1 0x40000000 178#define ATMEL_BASE_CS2 0x50000000 179#define ATMEL_BASE_CS3 0x60000000 180 181/* 182 * Other misc defines 183 */ 184#define ATMEL_PIO_PORTS 5 185#define CPU_HAS_PCR 186 187/* Timer */ 188#define CFG_SYS_TIMER_COUNTER 0xfffffe3c 189 190/* 191 * PMECC table in ROM 192 */ 193#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000 194#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000 195 196/* 197 * SAMA5D3 specific prototypes 198 */ 199#ifndef __ASSEMBLY__ 200unsigned int get_chip_id(void); 201unsigned int get_extension_chip_id(void); 202unsigned int has_emac(void); 203unsigned int has_gmac(void); 204unsigned int has_lcdc(void); 205char *get_cpu_name(void); 206#endif 207 208#endif 209