1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
4 *
5 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6 * Copyright (C) 2007 Andrew Victor
7 * Copyright (C) 2007 Atmel Corporation.
8 *
9 * SDRAM Controllers (SDRAMC) - System peripherals registers.
10 * Based on AT91SAM9261 datasheet revision D.
11 */
12
13#ifndef AT91SAM9_SDRAMC_H
14#define AT91SAM9_SDRAMC_H
15
16#ifdef __ASSEMBLY__
17
18#ifndef ATMEL_BASE_SDRAMC
19#define ATMEL_BASE_SDRAMC	ATMEL_BASE_SDRAMC0
20#endif
21
22#define AT91_ASM_SDRAMC_MR	ATMEL_BASE_SDRAMC
23#define AT91_ASM_SDRAMC_TR	(ATMEL_BASE_SDRAMC + 0x04)
24#define AT91_ASM_SDRAMC_CR	(ATMEL_BASE_SDRAMC + 0x08)
25#define AT91_ASM_SDRAMC_MDR	(ATMEL_BASE_SDRAMC + 0x24)
26
27#else
28struct sdramc_reg {
29	u32	mr;
30	u32	tr;
31	u32	cr;
32	u32	lpr;
33	u32	ier;
34	u32	idr;
35	u32	imr;
36	u32	isr;
37	u32	mdr;
38};
39
40int sdramc_initialize(unsigned int sdram_address,
41		      const struct sdramc_reg *p);
42#endif
43
44/* SDRAM Controller (SDRAMC) registers */
45#define AT91_SDRAMC_MR		(ATMEL_BASE_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
46#define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
47#define			AT91_SDRAMC_MODE_NORMAL		0
48#define			AT91_SDRAMC_MODE_NOP		1
49#define			AT91_SDRAMC_MODE_PRECHARGE	2
50#define			AT91_SDRAMC_MODE_LMR		3
51#define			AT91_SDRAMC_MODE_REFRESH	4
52#define			AT91_SDRAMC_MODE_EXT_LMR	5
53#define			AT91_SDRAMC_MODE_DEEP		6
54
55#define AT91_SDRAMC_TR		(ATMEL_BASE_SDRAMC + 0x04)	/* SDRAM Controller Refresh Timer Register */
56#define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */
57
58#define AT91_SDRAMC_CR		(ATMEL_BASE_SDRAMC + 0x08)	/* SDRAM Controller Configuration Register */
59#define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
60#define			AT91_SDRAMC_NC_8	(0 << 0)
61#define			AT91_SDRAMC_NC_9	(1 << 0)
62#define			AT91_SDRAMC_NC_10	(2 << 0)
63#define			AT91_SDRAMC_NC_11	(3 << 0)
64#define		AT91_SDRAMC_NR		(3 << 2)		/* Number of Row Bits */
65#define			AT91_SDRAMC_NR_11	(0 << 2)
66#define			AT91_SDRAMC_NR_12	(1 << 2)
67#define			AT91_SDRAMC_NR_13	(2 << 2)
68#define		AT91_SDRAMC_NB		(1 << 4)		/* Number of Banks */
69#define			AT91_SDRAMC_NB_2	(0 << 4)
70#define			AT91_SDRAMC_NB_4	(1 << 4)
71#define		AT91_SDRAMC_CAS		(3 << 5)		/* CAS Latency */
72#define			AT91_SDRAMC_CAS_1	(1 << 5)
73#define			AT91_SDRAMC_CAS_2	(2 << 5)
74#define			AT91_SDRAMC_CAS_3	(3 << 5)
75#define		AT91_SDRAMC_DBW		(1 << 7)		/* Data Bus Width */
76#define			AT91_SDRAMC_DBW_32	(0 << 7)
77#define			AT91_SDRAMC_DBW_16	(1 << 7)
78#define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
79#define		AT91_SDRAMC_TWR_VAL(x)	(x << 8)
80#define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
81#define			AT91_SDRAMC_TRC_VAL(x)	(x << 12)
82#define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
83#define		AT91_SDRAMC_TRP_VAL(x)	(x << 16)
84#define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
85#define			AT91_SDRAMC_TRCD_VAL(x)	(x << 20)
86#define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
87#define		AT91_SDRAMC_TRAS_VAL(x)	(x << 24)
88#define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
89#define		AT91_SDRAMC_TXSR_VAL(x)	(x << 28)
90
91#define AT91_SDRAMC_LPR		(ATMEL_BASE_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
92#define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
93#define			AT91_SDRAMC_LPCB_DISABLE		0
94#define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
95#define			AT91_SDRAMC_LPCB_POWER_DOWN		2
96#define			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
97#define		AT91_SDRAMC_PASR		(7 << 4)	/* Partial Array Self Refresh */
98#define		AT91_SDRAMC_TCSR		(3 << 8)	/* Temperature Compensated Self Refresh */
99#define		AT91_SDRAMC_DS			(3 << 10)	/* Drive Strength */
100#define		AT91_SDRAMC_TIMEOUT		(3 << 12)	/* Time to define when Low Power Mode is enabled */
101#define			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	(0 << 12)
102#define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
103#define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)
104
105#define AT91_SDRAMC_IER		(ATMEL_BASE_SDRAMC + 0x14)	/* SDRAM Controller Interrupt Enable Register */
106#define AT91_SDRAMC_IDR		(ATMEL_BASE_SDRAMC + 0x18)	/* SDRAM Controller Interrupt Disable Register */
107#define AT91_SDRAMC_IMR		(ATMEL_BASE_SDRAMC + 0x1C)	/* SDRAM Controller Interrupt Mask Register */
108#define AT91_SDRAMC_ISR		(ATMEL_BASE_SDRAMC + 0x20)	/* SDRAM Controller Interrupt Status Register */
109#define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */
110
111#define AT91_SDRAMC_MDR		(ATMEL_BASE_SDRAMC + 0x24)	/* SDRAM Memory Device Register */
112#define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
113#define			AT91_SDRAMC_MD_SDRAM		0
114#define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
115
116#endif
117