1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Broadcom.
4 */
5#include <common.h>
6#include <cpu_func.h>
7#include <dm.h>
8#include <asm/gic.h>
9#include <asm/gic-v3.h>
10#include <asm/io.h>
11#include <linux/bitops.h>
12#include <linux/printk.h>
13#include <linux/sizes.h>
14
15static u32 lpi_id_bits;
16
17#define LPI_NRBITS		lpi_id_bits
18#define LPI_PROPBASE_SZ		ALIGN(BIT(LPI_NRBITS), SZ_64K)
19#define LPI_PENDBASE_SZ		ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
20
21/*
22 * gic_v3_its_priv - gic details
23 *
24 * @gicd_base: gicd base address
25 * @gicr_base: gicr base address
26 */
27struct gic_v3_its_priv {
28	ulong gicd_base;
29	ulong gicr_base;
30};
31
32static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
33{
34	struct udevice *dev;
35	fdt_addr_t addr;
36	int ret;
37
38	ret = uclass_get_device_by_driver(UCLASS_IRQ,
39					  DM_DRIVER_GET(arm_gic_v3_its), &dev);
40	if (ret) {
41		pr_err("%s: failed to get %s irq device\n", __func__,
42		       DM_DRIVER_GET(arm_gic_v3_its)->name);
43		return ret;
44	}
45
46	addr = dev_read_addr_index(dev, 0);
47	if (addr == FDT_ADDR_T_NONE) {
48		pr_err("%s: failed to get GICD address\n", __func__);
49		return -EINVAL;
50	}
51	priv->gicd_base = addr;
52
53	addr = dev_read_addr_index(dev, 1);
54	if (addr == FDT_ADDR_T_NONE) {
55		pr_err("%s: failed to get GICR address\n", __func__);
56		return -EINVAL;
57	}
58	priv->gicr_base = addr;
59
60	return 0;
61}
62
63/*
64 * Program the GIC LPI configuration tables for all
65 * the re-distributors and enable the LPI table
66 * base: Configuration table address
67 * num_redist: number of redistributors
68 */
69int gic_lpi_tables_init(u64 base, u32 num_redist)
70{
71	struct gic_v3_its_priv priv;
72	u32 gicd_typer;
73	u64 val;
74	u64 tmp;
75	int i;
76	u64 redist_lpi_base;
77	u64 pend_base;
78	ulong pend_tab_total_sz = num_redist * LPI_PENDBASE_SZ;
79	void *pend_tab_va;
80
81	if (gic_v3_its_get_gic_addr(&priv))
82		return -EINVAL;
83
84	gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
85	/* GIC support for Locality specific peripheral interrupts (LPI's) */
86	if (!(gicd_typer & GICD_TYPER_LPIS)) {
87		pr_err("GIC implementation does not support LPI's\n");
88		return -EINVAL;
89	}
90
91	/*
92	 * Check for LPI is disabled for all the redistributors.
93	 * Once the LPI table is enabled, can not program the
94	 * LPI configuration tables again, unless the GIC is reset.
95	 */
96	for (i = 0; i < num_redist; i++) {
97		u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
98
99		if ((readl((uintptr_t)(priv.gicr_base + offset))) &
100		    GICR_CTLR_ENABLE_LPIS) {
101			pr_err("Re-Distributor %d LPI is already enabled\n",
102			       i);
103			return -EINVAL;
104		}
105	}
106
107	/* lpi_id_bits to get LPI_PENDBASE_SZ and LPi_PROPBASE_SZ */
108	lpi_id_bits = min_t(u32, GICD_TYPER_ID_BITS(gicd_typer),
109			    ITS_MAX_LPI_NRBITS);
110
111	/* Set PropBase */
112	val = (base |
113	       GICR_PROPBASER_INNERSHAREABLE |
114	       GICR_PROPBASER_RAWAWB |
115	       ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
116
117	writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
118	tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
119	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
120		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
121			val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
122				GICR_PROPBASER_CACHEABILITY_MASK);
123			val |= GICR_PROPBASER_NC;
124			writeq(val,
125			       (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
126		}
127	}
128
129	redist_lpi_base = base + LPI_PROPBASE_SZ;
130	pend_tab_va = map_physmem(redist_lpi_base, pend_tab_total_sz,
131				  MAP_NOCACHE);
132	memset(pend_tab_va, 0, pend_tab_total_sz);
133	flush_cache((ulong)pend_tab_va, pend_tab_total_sz);
134	unmap_physmem(pend_tab_va, MAP_NOCACHE);
135
136	pend_base = priv.gicr_base + GICR_PENDBASER;
137	for (i = 0; i < num_redist; i++) {
138		u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
139
140		val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
141			GICR_PENDBASER_INNERSHAREABLE |
142			GICR_PENDBASER_RAWAWB |
143			GICR_PENDBASER_PTZ);
144
145		writeq(val, (uintptr_t)(pend_base + offset));
146		tmp = readq((uintptr_t)(pend_base + offset));
147		if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
148			val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
149				 GICR_PENDBASER_CACHEABILITY_MASK);
150			val |= GICR_PENDBASER_NC;
151			writeq(val, (uintptr_t)(pend_base + offset));
152		}
153
154		/* Enable LPI for the redistributor */
155		writel(GICR_CTLR_ENABLE_LPIS,
156		       (uintptr_t)(priv.gicr_base + offset));
157	}
158
159	return 0;
160}
161
162static const struct udevice_id gic_v3_its_ids[] = {
163	{ .compatible = "arm,gic-v3" },
164	{}
165};
166
167U_BOOT_DRIVER(arm_gic_v3_its) = {
168	.name		= "gic-v3",
169	.id		= UCLASS_IRQ,
170	.of_match	= gic_v3_its_ids,
171};
172