1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2010 4 * Texas Instruments, <www.ti.com> 5 * 6 * Aneesh V <aneesh@ti.com> 7 */ 8#ifndef _OMAP_COMMON_H_ 9#define _OMAP_COMMON_H_ 10 11#ifndef __ASSEMBLY__ 12 13#include <linux/types.h> 14 15#define NUM_SYS_CLKS 7 16#define SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 17 18struct bd_info; 19 20struct prcm_regs { 21 /* cm1.ckgen */ 22 u32 cm_clksel_core; 23 u32 cm_clksel_abe; 24 u32 cm_dll_ctrl; 25 u32 cm_clkmode_dpll_core; 26 u32 cm_idlest_dpll_core; 27 u32 cm_autoidle_dpll_core; 28 u32 cm_clksel_dpll_core; 29 u32 cm_div_m2_dpll_core; 30 u32 cm_div_m3_dpll_core; 31 u32 cm_div_h11_dpll_core; 32 u32 cm_div_h12_dpll_core; 33 u32 cm_div_h13_dpll_core; 34 u32 cm_div_h14_dpll_core; 35 u32 cm_div_h21_dpll_core; 36 u32 cm_div_h24_dpll_core; 37 u32 cm_ssc_deltamstep_dpll_core; 38 u32 cm_ssc_modfreqdiv_dpll_core; 39 u32 cm_emu_override_dpll_core; 40 u32 cm_div_h22_dpllcore; 41 u32 cm_div_h23_dpll_core; 42 u32 cm_clkmode_dpll_mpu; 43 u32 cm_idlest_dpll_mpu; 44 u32 cm_autoidle_dpll_mpu; 45 u32 cm_clksel_dpll_mpu; 46 u32 cm_div_m2_dpll_mpu; 47 u32 cm_ssc_deltamstep_dpll_mpu; 48 u32 cm_ssc_modfreqdiv_dpll_mpu; 49 u32 cm_bypclk_dpll_mpu; 50 u32 cm_clkmode_dpll_iva; 51 u32 cm_idlest_dpll_iva; 52 u32 cm_autoidle_dpll_iva; 53 u32 cm_clksel_dpll_iva; 54 u32 cm_div_h11_dpll_iva; 55 u32 cm_div_h12_dpll_iva; 56 u32 cm_ssc_deltamstep_dpll_iva; 57 u32 cm_ssc_modfreqdiv_dpll_iva; 58 u32 cm_bypclk_dpll_iva; 59 u32 cm_clkmode_dpll_abe; 60 u32 cm_idlest_dpll_abe; 61 u32 cm_autoidle_dpll_abe; 62 u32 cm_clksel_dpll_abe; 63 u32 cm_div_m2_dpll_abe; 64 u32 cm_div_m3_dpll_abe; 65 u32 cm_ssc_deltamstep_dpll_abe; 66 u32 cm_ssc_modfreqdiv_dpll_abe; 67 u32 cm_clkmode_dpll_ddrphy; 68 u32 cm_idlest_dpll_ddrphy; 69 u32 cm_autoidle_dpll_ddrphy; 70 u32 cm_clksel_dpll_ddrphy; 71 u32 cm_div_m2_dpll_ddrphy; 72 u32 cm_div_h11_dpll_ddrphy; 73 u32 cm_div_h12_dpll_ddrphy; 74 u32 cm_div_h13_dpll_ddrphy; 75 u32 cm_ssc_deltamstep_dpll_ddrphy; 76 u32 cm_clkmode_dpll_dsp; 77 u32 cm_shadow_freq_config1; 78 u32 cm_clkmode_dpll_gmac; 79 u32 cm_mpu_mpu_clkctrl; 80 81 /* cm1.dsp */ 82 u32 cm_dsp_clkstctrl; 83 u32 cm_dsp_dsp_clkctrl; 84 85 /* cm1.abe */ 86 u32 cm1_abe_clkstctrl; 87 u32 cm1_abe_l4abe_clkctrl; 88 u32 cm1_abe_aess_clkctrl; 89 u32 cm1_abe_pdm_clkctrl; 90 u32 cm1_abe_dmic_clkctrl; 91 u32 cm1_abe_mcasp_clkctrl; 92 u32 cm1_abe_mcbsp1_clkctrl; 93 u32 cm1_abe_mcbsp2_clkctrl; 94 u32 cm1_abe_mcbsp3_clkctrl; 95 u32 cm1_abe_slimbus_clkctrl; 96 u32 cm1_abe_timer5_clkctrl; 97 u32 cm1_abe_timer6_clkctrl; 98 u32 cm1_abe_timer7_clkctrl; 99 u32 cm1_abe_timer8_clkctrl; 100 u32 cm1_abe_wdt3_clkctrl; 101 102 /* cm2.ckgen */ 103 u32 cm_clksel_mpu_m3_iss_root; 104 u32 cm_clksel_usb_60mhz; 105 u32 cm_scale_fclk; 106 u32 cm_core_dvfs_perf1; 107 u32 cm_core_dvfs_perf2; 108 u32 cm_core_dvfs_perf3; 109 u32 cm_core_dvfs_perf4; 110 u32 cm_core_dvfs_current; 111 u32 cm_iva_dvfs_perf_tesla; 112 u32 cm_iva_dvfs_perf_ivahd; 113 u32 cm_iva_dvfs_perf_abe; 114 u32 cm_iva_dvfs_current; 115 u32 cm_clkmode_dpll_per; 116 u32 cm_idlest_dpll_per; 117 u32 cm_autoidle_dpll_per; 118 u32 cm_clksel_dpll_per; 119 u32 cm_div_m2_dpll_per; 120 u32 cm_div_m3_dpll_per; 121 u32 cm_div_h11_dpll_per; 122 u32 cm_div_h12_dpll_per; 123 u32 cm_div_h13_dpll_per; 124 u32 cm_div_h14_dpll_per; 125 u32 cm_ssc_deltamstep_dpll_per; 126 u32 cm_ssc_modfreqdiv_dpll_per; 127 u32 cm_emu_override_dpll_per; 128 u32 cm_clkmode_dpll_usb; 129 u32 cm_idlest_dpll_usb; 130 u32 cm_autoidle_dpll_usb; 131 u32 cm_clksel_dpll_usb; 132 u32 cm_div_m2_dpll_usb; 133 u32 cm_ssc_deltamstep_dpll_usb; 134 u32 cm_ssc_modfreqdiv_dpll_usb; 135 u32 cm_clkdcoldo_dpll_usb; 136 u32 cm_clkmode_dpll_pcie_ref; 137 u32 cm_clkmode_apll_pcie; 138 u32 cm_idlest_apll_pcie; 139 u32 cm_div_m2_apll_pcie; 140 u32 cm_clkvcoldo_apll_pcie; 141 u32 cm_clkmode_dpll_unipro; 142 u32 cm_idlest_dpll_unipro; 143 u32 cm_autoidle_dpll_unipro; 144 u32 cm_clksel_dpll_unipro; 145 u32 cm_div_m2_dpll_unipro; 146 u32 cm_ssc_deltamstep_dpll_unipro; 147 u32 cm_ssc_modfreqdiv_dpll_unipro; 148 u32 cm_coreaon_usb_phy1_core_clkctrl; 149 u32 cm_coreaon_usb_phy2_core_clkctrl; 150 u32 cm_coreaon_usb_phy3_core_clkctrl; 151 u32 cm_coreaon_l3init_60m_gfclk_clkctrl; 152 153 /* cm2.core */ 154 u32 cm_coreaon_bandgap_clkctrl; 155 u32 cm_coreaon_io_srcomp_clkctrl; 156 u32 cm_l3_1_clkstctrl; 157 u32 cm_l3_1_dynamicdep; 158 u32 cm_l3_1_l3_1_clkctrl; 159 u32 cm_l3_2_clkstctrl; 160 u32 cm_l3_2_dynamicdep; 161 u32 cm_l3_2_l3_2_clkctrl; 162 u32 cm_l3_gpmc_clkctrl; 163 u32 cm_l3_2_ocmc_ram_clkctrl; 164 u32 cm_mpu_m3_clkstctrl; 165 u32 cm_mpu_m3_staticdep; 166 u32 cm_mpu_m3_dynamicdep; 167 u32 cm_mpu_m3_mpu_m3_clkctrl; 168 u32 cm_sdma_clkstctrl; 169 u32 cm_sdma_staticdep; 170 u32 cm_sdma_dynamicdep; 171 u32 cm_sdma_sdma_clkctrl; 172 u32 cm_memif_clkstctrl; 173 u32 cm_memif_dmm_clkctrl; 174 u32 cm_memif_emif_fw_clkctrl; 175 u32 cm_memif_emif_1_clkctrl; 176 u32 cm_memif_emif_2_clkctrl; 177 u32 cm_memif_dll_clkctrl; 178 u32 cm_memif_emif_h1_clkctrl; 179 u32 cm_memif_emif_h2_clkctrl; 180 u32 cm_memif_dll_h_clkctrl; 181 u32 cm_c2c_clkstctrl; 182 u32 cm_c2c_staticdep; 183 u32 cm_c2c_dynamicdep; 184 u32 cm_c2c_sad2d_clkctrl; 185 u32 cm_c2c_modem_icr_clkctrl; 186 u32 cm_c2c_sad2d_fw_clkctrl; 187 u32 cm_l4cfg_clkstctrl; 188 u32 cm_l4cfg_dynamicdep; 189 u32 cm_l4cfg_l4_cfg_clkctrl; 190 u32 cm_l4cfg_hw_sem_clkctrl; 191 u32 cm_l4cfg_mailbox_clkctrl; 192 u32 cm_l4cfg_sar_rom_clkctrl; 193 u32 cm_l3instr_clkstctrl; 194 u32 cm_l3instr_l3_3_clkctrl; 195 u32 cm_l3instr_l3_instr_clkctrl; 196 u32 cm_l3instr_intrconn_wp1_clkctrl; 197 198 /* cm2.ivahd */ 199 u32 cm_ivahd_clkstctrl; 200 u32 cm_ivahd_ivahd_clkctrl; 201 u32 cm_ivahd_sl2_clkctrl; 202 203 /* cm2.cam */ 204 u32 cm_cam_clkstctrl; 205 u32 cm_cam_iss_clkctrl; 206 u32 cm_cam_fdif_clkctrl; 207 u32 cm_cam_vip1_clkctrl; 208 u32 cm_cam_vip2_clkctrl; 209 u32 cm_cam_vip3_clkctrl; 210 u32 cm_cam_lvdsrx_clkctrl; 211 u32 cm_cam_csi1_clkctrl; 212 u32 cm_cam_csi2_clkctrl; 213 214 /* cm2.dss */ 215 u32 cm_dss_clkstctrl; 216 u32 cm_dss_dss_clkctrl; 217 218 /* cm2.sgx */ 219 u32 cm_sgx_clkstctrl; 220 u32 cm_sgx_sgx_clkctrl; 221 222 /* cm2.l3init */ 223 u32 cm_l3init_clkstctrl; 224 225 /* cm2.l3init */ 226 u32 cm_l3init_hsmmc1_clkctrl; 227 u32 cm_l3init_hsmmc2_clkctrl; 228 u32 cm_l3init_hsi_clkctrl; 229 u32 cm_l3init_hsusbhost_clkctrl; 230 u32 cm_l3init_hsusbotg_clkctrl; 231 u32 cm_l3init_hsusbtll_clkctrl; 232 u32 cm_l3init_p1500_clkctrl; 233 u32 cm_l3init_sata_clkctrl; 234 u32 cm_l3init_fsusb_clkctrl; 235 u32 cm_l3init_ocp2scp1_clkctrl; 236 u32 cm_l3init_ocp2scp3_clkctrl; 237 u32 cm_l3init_usb_otg_ss1_clkctrl; 238 u32 cm_l3init_usb_otg_ss2_clkctrl; 239 240 u32 prm_irqstatus_mpu; 241 u32 prm_irqstatus_mpu_2; 242 243 /* cm2.l4per */ 244 u32 cm_l4per_clkstctrl; 245 u32 cm_l4per_dynamicdep; 246 u32 cm_l4per_adc_clkctrl; 247 u32 cm_l4per_gptimer10_clkctrl; 248 u32 cm_l4per_gptimer11_clkctrl; 249 u32 cm_l4per_gptimer2_clkctrl; 250 u32 cm_l4per_gptimer3_clkctrl; 251 u32 cm_l4per_gptimer4_clkctrl; 252 u32 cm_l4per_gptimer9_clkctrl; 253 u32 cm_l4per_elm_clkctrl; 254 u32 cm_l4per_gpio2_clkctrl; 255 u32 cm_l4per_gpio3_clkctrl; 256 u32 cm_l4per_gpio4_clkctrl; 257 u32 cm_l4per_gpio5_clkctrl; 258 u32 cm_l4per_gpio6_clkctrl; 259 u32 cm_l4per_hdq1w_clkctrl; 260 u32 cm_l4per_hecc1_clkctrl; 261 u32 cm_l4per_hecc2_clkctrl; 262 u32 cm_l4per_i2c1_clkctrl; 263 u32 cm_l4per_i2c2_clkctrl; 264 u32 cm_l4per_i2c3_clkctrl; 265 u32 cm_l4per_i2c4_clkctrl; 266 u32 cm_l4per_l4per_clkctrl; 267 u32 cm_l4per_mcasp2_clkctrl; 268 u32 cm_l4per_mcasp3_clkctrl; 269 u32 cm_l4per_mgate_clkctrl; 270 u32 cm_l4per_mcspi1_clkctrl; 271 u32 cm_l4per_mcspi2_clkctrl; 272 u32 cm_l4per_mcspi3_clkctrl; 273 u32 cm_l4per_mcspi4_clkctrl; 274 u32 cm_l4per_gpio7_clkctrl; 275 u32 cm_l4per_gpio8_clkctrl; 276 u32 cm_l4per_mmcsd3_clkctrl; 277 u32 cm_l4per_mmcsd4_clkctrl; 278 u32 cm_l4per_msprohg_clkctrl; 279 u32 cm_l4per_slimbus2_clkctrl; 280 u32 cm_l4per_qspi_clkctrl; 281 u32 cm_l4per_uart1_clkctrl; 282 u32 cm_l4per_uart2_clkctrl; 283 u32 cm_l4per_uart3_clkctrl; 284 u32 cm_l4per_uart4_clkctrl; 285 u32 cm_l4per_mmcsd5_clkctrl; 286 u32 cm_l4per_i2c5_clkctrl; 287 u32 cm_l4per_uart5_clkctrl; 288 u32 cm_l4per_uart6_clkctrl; 289 u32 cm_l4sec_clkstctrl; 290 u32 cm_l4sec_staticdep; 291 u32 cm_l4sec_dynamicdep; 292 u32 cm_l4sec_aes1_clkctrl; 293 u32 cm_l4sec_aes2_clkctrl; 294 u32 cm_l4sec_des3des_clkctrl; 295 u32 cm_l4sec_pkaeip29_clkctrl; 296 u32 cm_l4sec_rng_clkctrl; 297 u32 cm_l4sec_sha2md51_clkctrl; 298 u32 cm_l4sec_cryptodma_clkctrl; 299 300 /* l4 wkup regs */ 301 u32 cm_abe_pll_ref_clksel; 302 u32 cm_sys_clksel; 303 u32 cm_abe_pll_sys_clksel; 304 u32 cm_wkup_clkstctrl; 305 u32 cm_wkup_l4wkup_clkctrl; 306 u32 cm_wkup_wdtimer1_clkctrl; 307 u32 cm_wkup_wdtimer2_clkctrl; 308 u32 cm_wkup_gpio1_clkctrl; 309 u32 cm_wkup_gptimer1_clkctrl; 310 u32 cm_wkup_gptimer12_clkctrl; 311 u32 cm_wkup_synctimer_clkctrl; 312 u32 cm_wkup_usim_clkctrl; 313 u32 cm_wkup_sarram_clkctrl; 314 u32 cm_wkup_keyboard_clkctrl; 315 u32 cm_wkup_rtc_clkctrl; 316 u32 cm_wkup_bandgap_clkctrl; 317 u32 cm_wkupaon_scrm_clkctrl; 318 u32 cm_wkupaon_io_srcomp_clkctrl; 319 u32 prm_rstctrl; 320 u32 prm_rstst; 321 u32 prm_rsttime; 322 u32 prm_io_pmctrl; 323 u32 prm_vc_val_bypass; 324 u32 prm_vc_cfg_i2c_mode; 325 u32 prm_vc_cfg_i2c_clk; 326 u32 prm_abbldo_mpu_setup; 327 u32 prm_abbldo_mpu_ctrl; 328 u32 prm_abbldo_mm_setup; 329 u32 prm_abbldo_mm_ctrl; 330 u32 prm_abbldo_iva_setup; 331 u32 prm_abbldo_iva_ctrl; 332 u32 prm_abbldo_eve_setup; 333 u32 prm_abbldo_eve_ctrl; 334 u32 prm_abbldo_gpu_setup; 335 u32 prm_abbldo_gpu_ctrl; 336 337 u32 cm_div_m4_dpll_core; 338 u32 cm_div_m5_dpll_core; 339 u32 cm_div_m6_dpll_core; 340 u32 cm_div_m7_dpll_core; 341 u32 cm_div_m4_dpll_iva; 342 u32 cm_div_m5_dpll_iva; 343 u32 cm_div_m4_dpll_ddrphy; 344 u32 cm_div_m5_dpll_ddrphy; 345 u32 cm_div_m6_dpll_ddrphy; 346 u32 cm_div_m4_dpll_per; 347 u32 cm_div_m5_dpll_per; 348 u32 cm_div_m6_dpll_per; 349 u32 cm_div_m7_dpll_per; 350 u32 cm_l3instr_intrconn_wp1_clkct; 351 u32 cm_l3init_usbphy_clkctrl; 352 u32 cm_l4per_mcbsp4_clkctrl; 353 u32 prm_vc_cfg_channel; 354 355 /* SCRM stuff, used by some boards */ 356 u32 scrm_auxclk0; 357 u32 scrm_auxclk1; 358 359 /* GMAC Clk Ctrl */ 360 u32 cm_gmac_gmac_clkctrl; 361 u32 cm_gmac_clkstctrl; 362 363 /* IPU */ 364 u32 cm_ipu_clkstctrl; 365 u32 cm_ipu_i2c5_clkctrl; 366 u32 cm_ipu1_clkstctrl; 367 u32 cm_ipu1_ipu1_clkctrl; 368 u32 cm_ipu2_clkstctrl; 369 u32 cm_ipu2_ipu2_clkctrl; 370 371 /*l3main1 edma*/ 372 u32 cm_l3main1_tptc1_clkctrl; 373 u32 cm_l3main1_tptc2_clkctrl; 374}; 375 376struct omap_sys_ctrl_regs { 377 u32 control_status; 378 u32 control_core_mac_id_0_lo; 379 u32 control_core_mac_id_0_hi; 380 u32 control_core_mac_id_1_lo; 381 u32 control_core_mac_id_1_hi; 382 u32 control_phy_power_usb; 383 u32 control_core_mmr_lock1; 384 u32 control_core_mmr_lock2; 385 u32 control_core_mmr_lock3; 386 u32 control_core_mmr_lock4; 387 u32 control_core_mmr_lock5; 388 u32 control_core_control_io1; 389 u32 control_core_control_io2; 390 u32 control_id_code; 391 u32 control_std_fuse_die_id_0; 392 u32 control_std_fuse_die_id_1; 393 u32 control_std_fuse_die_id_2; 394 u32 control_std_fuse_die_id_3; 395 u32 control_std_fuse_opp_bgap; 396 u32 control_ldosram_iva_voltage_ctrl; 397 u32 control_ldosram_mpu_voltage_ctrl; 398 u32 control_ldosram_core_voltage_ctrl; 399 u32 control_usbotghs_ctrl; 400 u32 control_phy_power_sata; 401 u32 control_padconf_core_base; 402 u32 control_paconf_global; 403 u32 control_paconf_mode; 404 u32 control_smart1io_padconf_0; 405 u32 control_smart1io_padconf_1; 406 u32 control_smart1io_padconf_2; 407 u32 control_smart2io_padconf_0; 408 u32 control_smart2io_padconf_1; 409 u32 control_smart2io_padconf_2; 410 u32 control_smart3io_padconf_0; 411 u32 control_smart3io_padconf_1; 412 u32 control_pbias; 413 u32 control_i2c_0; 414 u32 control_camera_rx; 415 u32 control_hdmi_tx_phy; 416 u32 control_uniportm; 417 u32 control_dsiphy; 418 u32 control_mcbsplp; 419 u32 control_usb2phycore; 420 u32 control_hdmi_1; 421 u32 control_hsi; 422 u32 control_ddr3ch1_0; 423 u32 control_ddr3ch2_0; 424 u32 control_ddrch1_0; 425 u32 control_ddrch1_1; 426 u32 control_ddrch2_0; 427 u32 control_ddrch2_1; 428 u32 control_lpddr2ch1_0; 429 u32 control_lpddr2ch1_1; 430 u32 control_ddrio_0; 431 u32 control_ddrio_1; 432 u32 control_ddrio_2; 433 u32 control_ddr_control_ext_0; 434 u32 control_lpddr2io1_0; 435 u32 control_lpddr2io1_1; 436 u32 control_lpddr2io1_2; 437 u32 control_lpddr2io1_3; 438 u32 control_lpddr2io2_0; 439 u32 control_lpddr2io2_1; 440 u32 control_lpddr2io2_2; 441 u32 control_lpddr2io2_3; 442 u32 control_hyst_1; 443 u32 control_usbb_hsic_control; 444 u32 control_c2c; 445 u32 control_core_control_spare_rw; 446 u32 control_core_control_spare_r; 447 u32 control_core_control_spare_r_c0; 448 u32 control_srcomp_north_side; 449 u32 control_srcomp_south_side; 450 u32 control_srcomp_east_side; 451 u32 control_srcomp_west_side; 452 u32 control_srcomp_code_latch; 453 u32 control_pbiaslite; 454 u32 control_port_emif1_sdram_config; 455 u32 control_port_emif1_lpddr2_nvm_config; 456 u32 control_port_emif2_sdram_config; 457 u32 control_emif1_sdram_config_ext; 458 u32 control_emif2_sdram_config_ext; 459 u32 control_wkup_ldovbb_mpu_voltage_ctrl; 460 u32 control_wkup_ldovbb_mm_voltage_ctrl; 461 u32 control_wkup_ldovbb_iva_voltage_ctrl; 462 u32 control_wkup_ldovbb_eve_voltage_ctrl; 463 u32 control_wkup_ldovbb_gpu_voltage_ctrl; 464 u32 control_smart1nopmio_padconf_0; 465 u32 control_smart1nopmio_padconf_1; 466 u32 control_padconf_mode; 467 u32 control_xtal_oscillator; 468 u32 control_i2c_2; 469 u32 control_ckobuffer; 470 u32 control_wkup_control_spare_rw; 471 u32 control_wkup_control_spare_r; 472 u32 control_wkup_control_spare_r_c0; 473 u32 control_srcomp_east_side_wkup; 474 u32 control_efuse_1; 475 u32 control_efuse_2; 476 u32 control_efuse_3; 477 u32 control_efuse_4; 478 u32 control_efuse_5; 479 u32 control_efuse_6; 480 u32 control_efuse_7; 481 u32 control_efuse_8; 482 u32 control_efuse_9; 483 u32 control_efuse_10; 484 u32 control_efuse_11; 485 u32 control_efuse_12; 486 u32 control_efuse_13; 487 u32 control_padconf_wkup_base; 488 u32 iodelay_config_base; 489 u32 ctrl_core_sma_sw_0; 490 u32 ctrl_core_sma_sw_1; 491}; 492 493#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) 494struct dpll_params { 495 u32 m; 496 u32 n; 497 s8 m2; 498 s8 m3; 499 s8 m4_h11; 500 s8 m5_h12; 501 s8 m6_h13; 502 s8 m7_h14; 503 s8 h21; 504 s8 h22; 505 s8 h23; 506 s8 h24; 507}; 508 509struct dpll_regs { 510 u32 cm_clkmode_dpll; 511 u32 cm_idlest_dpll; 512 u32 cm_autoidle_dpll; 513 u32 cm_clksel_dpll; 514 u32 cm_div_m2_dpll; 515 u32 cm_div_m3_dpll; 516 u32 cm_div_m4_h11_dpll; 517 u32 cm_div_m5_h12_dpll; 518 u32 cm_div_m6_h13_dpll; 519 u32 cm_div_m7_h14_dpll; 520 u32 reserved[2]; 521 u32 cm_div_h21_dpll; 522 u32 cm_div_h22_dpll; 523 u32 cm_div_h23_dpll; 524 u32 cm_div_h24_dpll; 525}; 526#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ 527 528struct dplls { 529 const struct dpll_params *mpu; 530 const struct dpll_params *core; 531 const struct dpll_params *per; 532 const struct dpll_params *abe; 533 const struct dpll_params *iva; 534 const struct dpll_params *usb; 535 const struct dpll_params *ddr; 536 const struct dpll_params *gmac; 537}; 538 539struct pmic_data { 540 u32 base_offset; 541 u32 step; 542 u32 start_code; 543 unsigned gpio; 544 int gpio_en; 545 u32 i2c_slave_addr; 546 void (*pmic_bus_init)(void); 547 int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); 548}; 549 550#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) 551enum { 552 OPP_LOW, 553 OPP_NOM, 554 OPP_OD, 555 OPP_HIGH, 556 NUM_OPPS, 557}; 558 559/** 560 * struct volts_efuse_data - efuse definition for voltage 561 * @reg: register address for efuse 562 * @reg_bits: Number of bits in a register address, mandatory. 563 */ 564struct volts_efuse_data { 565 u32 reg[NUM_OPPS]; 566 u8 reg_bits; 567}; 568 569struct volts { 570 u32 value[NUM_OPPS]; 571 u32 addr; 572 struct volts_efuse_data efuse; 573 struct pmic_data *pmic; 574 575 u32 abb_tx_done_mask; 576}; 577 578enum { 579 VOLT_MPU, 580 VOLT_CORE, 581 VOLT_MM, 582 VOLT_GPU, 583 VOLT_EVE, 584 VOLT_IVA, 585 NUM_VOLT_RAILS, 586}; 587 588struct vcores_data { 589 struct volts mpu; 590 struct volts core; 591 struct volts mm; 592 struct volts gpu; 593 struct volts eve; 594 struct volts iva; 595}; 596#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ 597 598extern struct prcm_regs const **prcm; 599extern struct prcm_regs const omap5_es1_prcm; 600extern struct prcm_regs const omap5_es2_prcm; 601extern struct prcm_regs const omap4_prcm; 602extern struct prcm_regs const dra7xx_prcm; 603extern struct dplls const **dplls_data; 604extern struct dplls dra7xx_dplls; 605extern struct dplls dra72x_dplls; 606extern struct dplls dra76x_dplls; 607extern struct vcores_data const **omap_vcores; 608extern const u32 sys_clk_array[8]; 609extern struct omap_sys_ctrl_regs const **ctrl; 610extern struct omap_sys_ctrl_regs const am33xx_ctrl; 611extern struct omap_sys_ctrl_regs const omap3_ctrl; 612extern struct omap_sys_ctrl_regs const omap4_ctrl; 613extern struct omap_sys_ctrl_regs const omap5_ctrl; 614extern struct omap_sys_ctrl_regs const dra7xx_ctrl; 615 616extern struct pmic_data tps659038; 617extern struct pmic_data lp8733; 618extern struct pmic_data lp87565; 619 620void hw_data_init(void); 621 622const struct dpll_params *get_mpu_dpll_params(struct dplls const *); 623const struct dpll_params *get_core_dpll_params(struct dplls const *); 624const struct dpll_params *get_per_dpll_params(struct dplls const *); 625const struct dpll_params *get_iva_dpll_params(struct dplls const *); 626const struct dpll_params *get_usb_dpll_params(struct dplls const *); 627const struct dpll_params *get_abe_dpll_params(struct dplls const *); 628 629#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) 630void do_enable_clocks(u32 const *clk_domains, 631 u32 const *clk_modules_hw_auto, 632 u32 const *clk_modules_explicit_en, 633 u8 wait_for_enable); 634 635void do_disable_clocks(u32 const *clk_domains, 636 u32 const *clk_modules_disable, 637 u8 wait_for_disable); 638#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ 639 640void do_enable_ipu_clocks(u32 const *clk_domains, 641 u32 const *clk_modules_hw_auto, 642 u32 const *clk_modules_explicit_en, 643 u8 wait_for_enable); 644void enable_ipu1_clocks(void); 645void enable_ipu2_clocks(void); 646void setup_post_dividers(u32 const base, 647 const struct dpll_params *params); 648u32 omap_ddr_clk(void); 649u32 get_sys_clk_index(void); 650void enable_basic_clocks(void); 651void enable_basic_uboot_clocks(void); 652 653void enable_usb_clocks(int index); 654void disable_usb_clocks(int index); 655 656#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) 657void scale_vcores(struct vcores_data const *); 658#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ 659int get_voltrail_opp(int rail_offset); 660u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); 661void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); 662void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, 663 u32 txdone, u32 txdone_mask, u32 opp); 664s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); 665 666struct tag_serialnr; 667 668void omap_die_id_serial(void); 669void omap_die_id_get_board_serial(struct tag_serialnr *serialnr); 670void omap_die_id_usbethaddr(void); 671void omap_die_id_display(void); 672 673#ifdef CONFIG_FASTBOOT_FLASH 674void omap_set_fastboot_vars(void); 675#else 676static inline void omap_set_fastboot_vars(void) { } 677#endif 678 679void recalibrate_iodelay(void); 680 681void omap_smc1(u32 service, u32 val); 682 683/* 684 * Low-level helper function used when performing secure ROM calls on high- 685 * security (HS) device variants by doing a specially-formed smc entry. 686 */ 687u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params); 688u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params); 689 690void enable_edma3_clocks(void); 691void disable_edma3_clocks(void); 692 693void omap_die_id(unsigned int *die_id); 694 695/* Initialize general purpose I2C(0) on the SoC */ 696void gpi2c_init(void); 697 698/* Common FDT Fixups */ 699int ft_hs_disable_rng(void *fdt, struct bd_info *bd); 700int ft_hs_fixup_dram(void *fdt, struct bd_info *bd); 701int ft_hs_add_tee(void *fdt, struct bd_info *bd); 702 703/* ABB */ 704#define OMAP_ABB_NOMINAL_OPP 0 705#define OMAP_ABB_FAST_OPP 1 706#define OMAP_ABB_SLOW_OPP 3 707#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0) 708#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1) 709#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2) 710#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6) 711#define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0) 712#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2) 713#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1) 714#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8) 715 716static inline u32 omap_revision(void) 717{ 718 extern u32 *const omap_si_rev; 719 return *omap_si_rev; 720} 721 722#define OMAP44xx 0x44000000 723 724static inline u8 is_omap44xx(void) 725{ 726 extern u32 *const omap_si_rev; 727 return (*omap_si_rev & 0xFF000000) == OMAP44xx; 728}; 729 730#define OMAP54xx 0x54000000 731 732static inline u8 is_omap54xx(void) 733{ 734 extern u32 *const omap_si_rev; 735 return ((*omap_si_rev & 0xFF000000) == OMAP54xx); 736} 737 738#define DRA7XX 0x07000000 739#define DRA72X 0x07200000 740#define DRA76X 0x07600000 741 742static inline u8 is_dra7xx(void) 743{ 744 extern u32 *const omap_si_rev; 745 return ((*omap_si_rev & 0xFF000000) == DRA7XX); 746} 747 748static inline u8 is_dra72x(void) 749{ 750 extern u32 *const omap_si_rev; 751 return (*omap_si_rev & 0xFFF00000) == DRA72X; 752} 753 754static inline u8 is_dra76x(void) 755{ 756 extern u32 *const omap_si_rev; 757 return (*omap_si_rev & 0xFFF00000) == DRA76X; 758} 759 760static inline u8 is_dra76x_abz(void) 761{ 762 extern u32 *const omap_si_rev; 763 return (*omap_si_rev & 0xF) == 2; 764} 765 766static inline u8 is_dra76x_acd(void) 767{ 768 extern u32 *const omap_si_rev; 769 return (*omap_si_rev & 0xF) == 3; 770} 771#endif 772 773/* 774 * silicon revisions. 775 * Moving this to common, so that most of code can be moved to common, 776 * directories. 777 */ 778 779/* omap4 */ 780#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF 781#define OMAP4430_ES1_0 0x44300100 782#define OMAP4430_ES2_0 0x44300200 783#define OMAP4430_ES2_1 0x44300210 784#define OMAP4430_ES2_2 0x44300220 785#define OMAP4430_ES2_3 0x44300230 786#define OMAP4460_ES1_0 0x44600100 787#define OMAP4460_ES1_1 0x44600110 788#define OMAP4470_ES1_0 0x44700100 789 790/* omap5 */ 791#define OMAP5430_SILICON_ID_INVALID 0 792#define OMAP5430_ES1_0 0x54300100 793#define OMAP5432_ES1_0 0x54320100 794#define OMAP5430_ES2_0 0x54300200 795#define OMAP5432_ES2_0 0x54320200 796 797/* DRA7XX */ 798#define DRA762_ES1_0 0x07620100 799#define DRA752_ES1_0 0x07520100 800#define DRA752_ES1_1 0x07520110 801#define DRA752_ES2_0 0x07520200 802#define DRA722_ES1_0 0x07220100 803#define DRA722_ES2_0 0x07220200 804#define DRA722_ES2_1 0x07220210 805 806#define DRA762_ABZ_ES1_0 0x07620102 807#define DRA762_ACD_ES1_0 0x07620103 808/* 809 * silicon device type 810 * Moving to common from cpu.h, since it is shared by various omap devices 811 */ 812#define TST_DEVICE 0x0 813#define EMU_DEVICE 0x1 814#define HS_DEVICE 0x2 815#define GP_DEVICE 0x3 816 817 818/* 819 * SRAM scratch space entries 820 */ 821#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR 822#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) 823#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) 824#define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) 825#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) 826#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) 827#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) 828#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) 829#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) 830#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START 831#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28) 832#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) 833#endif 834#define OMAP_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) 835 836/* Boot parameters */ 837#define DEVICE_DATA_OFFSET 0x18 838#define BOOT_MODE_OFFSET 0x8 839 840#define CH_FLAGS_CHSETTINGS (1 << 0) 841#define CH_FLAGS_CHRAM (1 << 1) 842#define CH_FLAGS_CHFLASH (1 << 2) 843#define CH_FLAGS_CHMMCSD (1 << 3) 844 845#ifndef __ASSEMBLY__ 846u32 omap_sys_boot_device(void); 847#endif 848 849#endif /* _OMAP_COMMON_H_ */ 850