1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2002-2010 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7#ifndef __ASM_GBL_DATA_H 8#define __ASM_GBL_DATA_H 9 10#ifndef __ASSEMBLY__ 11 12#include <config.h> 13 14#include <linux/types.h> 15 16/* Architecture-specific global data */ 17struct arch_global_data { 18#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX) 19 u32 sdhc_clk; 20#endif 21#if CONFIG_IS_ENABLED(ACPI) 22 ulong table_start; /* Start address of ACPI tables */ 23 ulong table_end; /* End address of ACPI tables */ 24 ulong table_start_high; /* Start address of high ACPI tables */ 25 ulong table_end_high; /* End address of high ACPI tables */ 26#endif 27#if defined(CONFIG_FSL_ESDHC) 28 u32 sdhc_per_clk; 29#endif 30 31#if defined(CONFIG_U_QE) 32 u32 qe_clk; 33 u32 brg_clk; 34 uint mp_alloc_base; 35 uint mp_alloc_top; 36#endif /* CONFIG_U_QE */ 37 38#ifdef CONFIG_AT91FAMILY 39 /* "static data" needed by at91's clock.c */ 40 unsigned long cpu_clk_rate_hz; 41 unsigned long main_clk_rate_hz; 42 unsigned long mck_rate_hz; 43 unsigned long plla_rate_hz; 44 unsigned long pllb_rate_hz; 45 unsigned long at91_pllb_usb_init; 46#endif 47 /* "static data" needed by most of timer.c on ARM platforms */ 48 unsigned long timer_rate_hz; 49 unsigned int tbu; 50 unsigned int tbl; 51 unsigned long lastinc; 52 unsigned long long timer_reset_value; 53#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) 54 unsigned long tlb_addr; 55 unsigned long tlb_size; 56#if defined(CONFIG_ARM64) 57 unsigned long tlb_fillptr; 58 unsigned long tlb_emerg; 59#endif 60#endif 61#ifdef CFG_SYS_MEM_RESERVE_SECURE 62#define MEM_RESERVE_SECURE_SECURED 0x1 63#define MEM_RESERVE_SECURE_MAINTAINED 0x2 64#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) 65 /* 66 * Secure memory addr 67 * This variable needs maintenance if the RAM base is not zero, 68 * or if RAM splits into non-consecutive banks. It also has a 69 * flag indicating the secure memory is marked as secure by MMU. 70 * Flags used: 0x1 secured 71 * 0x2 maintained 72 */ 73 phys_addr_t secure_ram; 74 unsigned long tlb_allocated; 75#endif 76#ifdef CONFIG_RESV_RAM 77 /* 78 * Reserved RAM for memory resident, eg. Management Complex (MC) 79 * driver which continues to run after U-Boot exits. 80 */ 81 phys_addr_t resv_ram; 82#endif 83 84#ifdef CONFIG_ARCH_OMAP2PLUS 85 u32 omap_boot_device; 86 u32 omap_boot_mode; 87 u8 omap_ch_flags; 88#endif 89#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) 90 unsigned long mem2_clk; 91#endif 92 93#ifdef CONFIG_ARCH_IMX8 94 struct udevice *scu_dev; 95#endif 96 97#ifdef CONFIG_IMX_ELE 98 struct udevice *ele_dev; 99 u32 soc_rev; 100 u32 lifecycle; 101 u32 uid[4]; 102#endif 103 104#ifdef CONFIG_ARCH_IMX8ULP 105 bool m33_handshake_done; 106#endif 107#ifdef CONFIG_SMBIOS 108 ulong smbios_start; /* Start address of SMBIOS table */ 109#endif 110}; 111 112#include <asm-generic/global_data.h> 113 114#if defined(__clang__) || defined(LTO_ENABLE) 115 116#define DECLARE_GLOBAL_DATA_PTR 117#define gd get_gd() 118 119static inline gd_t *get_gd(void) 120{ 121 gd_t *gd_ptr; 122 123#ifdef CONFIG_ARM64 124 __asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr)); 125#else 126 __asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr)); 127#endif 128 129 return gd_ptr; 130} 131 132#else 133 134#ifdef CONFIG_ARM64 135#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") 136#else 137#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") 138#endif 139#endif 140 141static inline void set_gd(volatile gd_t *gd_ptr) 142{ 143#ifdef CONFIG_ARM64 144 __asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr)); 145#elif __ARM_ARCH >= 7 146 __asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr)); 147#else 148 __asm__ volatile("mov r9, %0\n" : : "r"(gd_ptr)); 149#endif 150} 151 152#endif /* __ASSEMBLY__ */ 153 154#endif /* __ASM_GBL_DATA_H */ 155