1/* 2 * OMAP44xx EMIF header 3 * 4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 5 * 6 * Aneesh V <aneesh@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13#ifndef _EMIF_H_ 14#define _EMIF_H_ 15#include <asm/types.h> 16#include <asm/io.h> 17 18/* Base address */ 19#ifndef EMIF1_BASE 20#define EMIF1_BASE 0x4c000000 21#endif 22#define EMIF2_BASE 0x4d000000 23 24#define EMIF_4D 0x4 25#define EMIF_4D5 0x5 26 27/* Registers shifts, masks and values */ 28 29/* EMIF_MOD_ID_REV */ 30#define EMIF_REG_SCHEME_SHIFT 30 31#define EMIF_REG_SCHEME_MASK (0x3 << 30) 32#define EMIF_REG_MODULE_ID_SHIFT 16 33#define EMIF_REG_MODULE_ID_MASK (0xfff << 16) 34#define EMIF_REG_RTL_VERSION_SHIFT 11 35#define EMIF_REG_RTL_VERSION_MASK (0x1f << 11) 36#define EMIF_REG_MAJOR_REVISION_SHIFT 8 37#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8) 38#define EMIF_REG_MINOR_REVISION_SHIFT 0 39#define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0) 40 41/* STATUS */ 42#define EMIF_REG_BE_SHIFT 31 43#define EMIF_REG_BE_MASK (1 << 31) 44#define EMIF_REG_DUAL_CLK_MODE_SHIFT 30 45#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30) 46#define EMIF_REG_FAST_INIT_SHIFT 29 47#define EMIF_REG_FAST_INIT_MASK (1 << 29) 48#define EMIF_REG_LEVLING_TO_SHIFT 4 49#define EMIF_REG_LEVELING_TO_MASK (7 << 4) 50#define EMIF_REG_PHY_DLL_READY_SHIFT 2 51#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2) 52 53/* SDRAM_CONFIG */ 54#define EMIF_REG_SDRAM_TYPE_SHIFT 29 55#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29) 56#define EMIF_REG_SDRAM_TYPE_DDR1 0 57#define EMIF_REG_SDRAM_TYPE_LPDDR1 1 58#define EMIF_REG_SDRAM_TYPE_DDR2 2 59#define EMIF_REG_SDRAM_TYPE_DDR3 3 60#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4 61#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5 62#define EMIF_REG_IBANK_POS_SHIFT 27 63#define EMIF_REG_IBANK_POS_MASK (0x3 << 27) 64#define EMIF_REG_DDR_TERM_SHIFT 24 65#define EMIF_REG_DDR_TERM_MASK (0x7 << 24) 66#define EMIF_REG_DDR2_DDQS_SHIFT 23 67#define EMIF_REG_DDR2_DDQS_MASK (1 << 23) 68#define EMIF_REG_DYN_ODT_SHIFT 21 69#define EMIF_REG_DYN_ODT_MASK (0x3 << 21) 70#define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20 71#define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20) 72#define EMIF_REG_SDRAM_DRIVE_SHIFT 18 73#define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18) 74#define EMIF_REG_CWL_SHIFT 16 75#define EMIF_REG_CWL_MASK (0x3 << 16) 76#define EMIF_REG_NARROW_MODE_SHIFT 14 77#define EMIF_REG_NARROW_MODE_MASK (0x3 << 14) 78#define EMIF_REG_CL_SHIFT 10 79#define EMIF_REG_CL_MASK (0xf << 10) 80#define EMIF_REG_ROWSIZE_SHIFT 7 81#define EMIF_REG_ROWSIZE_MASK (0x7 << 7) 82#define EMIF_REG_IBANK_SHIFT 4 83#define EMIF_REG_IBANK_MASK (0x7 << 4) 84#define EMIF_REG_EBANK_SHIFT 3 85#define EMIF_REG_EBANK_MASK (1 << 3) 86#define EMIF_REG_PAGESIZE_SHIFT 0 87#define EMIF_REG_PAGESIZE_MASK (0x7 << 0) 88 89/* SDRAM_CONFIG_2 */ 90#define EMIF_REG_CS1NVMEN_SHIFT 30 91#define EMIF_REG_CS1NVMEN_MASK (1 << 30) 92#define EMIF_REG_EBANK_POS_SHIFT 27 93#define EMIF_REG_EBANK_POS_MASK (1 << 27) 94#define EMIF_REG_RDBNUM_SHIFT 4 95#define EMIF_REG_RDBNUM_MASK (0x3 << 4) 96#define EMIF_REG_RDBSIZE_SHIFT 0 97#define EMIF_REG_RDBSIZE_MASK (0x7 << 0) 98 99/* SDRAM_REF_CTRL */ 100#define EMIF_REG_INITREF_DIS_SHIFT 31 101#define EMIF_REG_INITREF_DIS_MASK (1 << 31) 102#define EMIF_REG_SRT_SHIFT 29 103#define EMIF_REG_SRT_MASK (1 << 29) 104#define EMIF_REG_ASR_SHIFT 28 105#define EMIF_REG_ASR_MASK (1 << 28) 106#define EMIF_REG_PASR_SHIFT 24 107#define EMIF_REG_PASR_MASK (0x7 << 24) 108#define EMIF_REG_REFRESH_RATE_SHIFT 0 109#define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0) 110 111/* SDRAM_REF_CTRL_SHDW */ 112#define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0 113#define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) 114 115/* SDRAM_TIM_1 */ 116#define EMIF_REG_T_RP_SHIFT 25 117#define EMIF_REG_T_RP_MASK (0xf << 25) 118#define EMIF_REG_T_RCD_SHIFT 21 119#define EMIF_REG_T_RCD_MASK (0xf << 21) 120#define EMIF_REG_T_WR_SHIFT 17 121#define EMIF_REG_T_WR_MASK (0xf << 17) 122#define EMIF_REG_T_RAS_SHIFT 12 123#define EMIF_REG_T_RAS_MASK (0x1f << 12) 124#define EMIF_REG_T_RC_SHIFT 6 125#define EMIF_REG_T_RC_MASK (0x3f << 6) 126#define EMIF_REG_T_RRD_SHIFT 3 127#define EMIF_REG_T_RRD_MASK (0x7 << 3) 128#define EMIF_REG_T_WTR_SHIFT 0 129#define EMIF_REG_T_WTR_MASK (0x7 << 0) 130 131/* SDRAM_TIM_1_SHDW */ 132#define EMIF_REG_T_RP_SHDW_SHIFT 25 133#define EMIF_REG_T_RP_SHDW_MASK (0xf << 25) 134#define EMIF_REG_T_RCD_SHDW_SHIFT 21 135#define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21) 136#define EMIF_REG_T_WR_SHDW_SHIFT 17 137#define EMIF_REG_T_WR_SHDW_MASK (0xf << 17) 138#define EMIF_REG_T_RAS_SHDW_SHIFT 12 139#define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12) 140#define EMIF_REG_T_RC_SHDW_SHIFT 6 141#define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6) 142#define EMIF_REG_T_RRD_SHDW_SHIFT 3 143#define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3) 144#define EMIF_REG_T_WTR_SHDW_SHIFT 0 145#define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0) 146 147/* SDRAM_TIM_2 */ 148#define EMIF_REG_T_XP_SHIFT 28 149#define EMIF_REG_T_XP_MASK (0x7 << 28) 150#define EMIF_REG_T_ODT_SHIFT 25 151#define EMIF_REG_T_ODT_MASK (0x7 << 25) 152#define EMIF_REG_T_XSNR_SHIFT 16 153#define EMIF_REG_T_XSNR_MASK (0x1ff << 16) 154#define EMIF_REG_T_XSRD_SHIFT 6 155#define EMIF_REG_T_XSRD_MASK (0x3ff << 6) 156#define EMIF_REG_T_RTP_SHIFT 3 157#define EMIF_REG_T_RTP_MASK (0x7 << 3) 158#define EMIF_REG_T_CKE_SHIFT 0 159#define EMIF_REG_T_CKE_MASK (0x7 << 0) 160 161/* SDRAM_TIM_2_SHDW */ 162#define EMIF_REG_T_XP_SHDW_SHIFT 28 163#define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28) 164#define EMIF_REG_T_ODT_SHDW_SHIFT 25 165#define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25) 166#define EMIF_REG_T_XSNR_SHDW_SHIFT 16 167#define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16) 168#define EMIF_REG_T_XSRD_SHDW_SHIFT 6 169#define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6) 170#define EMIF_REG_T_RTP_SHDW_SHIFT 3 171#define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3) 172#define EMIF_REG_T_CKE_SHDW_SHIFT 0 173#define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0) 174 175/* SDRAM_TIM_3 */ 176#define EMIF_REG_T_CKESR_SHIFT 21 177#define EMIF_REG_T_CKESR_MASK (0x7 << 21) 178#define EMIF_REG_ZQ_ZQCS_SHIFT 15 179#define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15) 180#define EMIF_REG_T_TDQSCKMAX_SHIFT 13 181#define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13) 182#define EMIF_REG_T_RFC_SHIFT 4 183#define EMIF_REG_T_RFC_MASK (0x1ff << 4) 184#define EMIF_REG_T_RAS_MAX_SHIFT 0 185#define EMIF_REG_T_RAS_MAX_MASK (0xf << 0) 186 187/* SDRAM_TIM_3_SHDW */ 188#define EMIF_REG_T_CKESR_SHDW_SHIFT 21 189#define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21) 190#define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15 191#define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) 192#define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13 193#define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) 194#define EMIF_REG_T_RFC_SHDW_SHIFT 4 195#define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4) 196#define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0 197#define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) 198 199/* LPDDR2_NVM_TIM */ 200#define EMIF_REG_NVM_T_XP_SHIFT 28 201#define EMIF_REG_NVM_T_XP_MASK (0x7 << 28) 202#define EMIF_REG_NVM_T_WTR_SHIFT 24 203#define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24) 204#define EMIF_REG_NVM_T_RP_SHIFT 20 205#define EMIF_REG_NVM_T_RP_MASK (0xf << 20) 206#define EMIF_REG_NVM_T_WRA_SHIFT 16 207#define EMIF_REG_NVM_T_WRA_MASK (0xf << 16) 208#define EMIF_REG_NVM_T_RRD_SHIFT 8 209#define EMIF_REG_NVM_T_RRD_MASK (0xff << 8) 210#define EMIF_REG_NVM_T_RCDMIN_SHIFT 0 211#define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0) 212 213/* LPDDR2_NVM_TIM_SHDW */ 214#define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28 215#define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) 216#define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24 217#define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) 218#define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20 219#define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20) 220#define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16 221#define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) 222#define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8 223#define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) 224#define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 225#define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) 226 227/* PWR_MGMT_CTRL */ 228#define EMIF_REG_IDLEMODE_SHIFT 30 229#define EMIF_REG_IDLEMODE_MASK (0x3 << 30) 230#define EMIF_REG_PD_TIM_SHIFT 12 231#define EMIF_REG_PD_TIM_MASK (0xf << 12) 232#define EMIF_REG_DPD_EN_SHIFT 11 233#define EMIF_REG_DPD_EN_MASK (1 << 11) 234#define EMIF_REG_LP_MODE_SHIFT 8 235#define EMIF_REG_LP_MODE_MASK (0x7 << 8) 236#define EMIF_REG_SR_TIM_SHIFT 4 237#define EMIF_REG_SR_TIM_MASK (0xf << 4) 238#define EMIF_REG_CS_TIM_SHIFT 0 239#define EMIF_REG_CS_TIM_MASK (0xf << 0) 240 241/* PWR_MGMT_CTRL_SHDW */ 242#define EMIF_REG_PD_TIM_SHDW_SHIFT 12 243#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12) 244#define EMIF_REG_SR_TIM_SHDW_SHIFT 4 245#define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4) 246#define EMIF_REG_CS_TIM_SHDW_SHIFT 0 247#define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0) 248 249/* LPDDR2_MODE_REG_DATA */ 250#define EMIF_REG_VALUE_0_SHIFT 0 251#define EMIF_REG_VALUE_0_MASK (0x7f << 0) 252 253/* LPDDR2_MODE_REG_CFG */ 254#define EMIF_REG_CS_SHIFT 31 255#define EMIF_REG_CS_MASK (1 << 31) 256#define EMIF_REG_REFRESH_EN_SHIFT 30 257#define EMIF_REG_REFRESH_EN_MASK (1 << 30) 258#define EMIF_REG_ADDRESS_SHIFT 0 259#define EMIF_REG_ADDRESS_MASK (0xff << 0) 260 261/* OCP_CONFIG */ 262#define EMIF_REG_SYS_THRESH_MAX_SHIFT 24 263#define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24) 264#define EMIF_REG_MPU_THRESH_MAX_SHIFT 20 265#define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20) 266#define EMIF_REG_LL_THRESH_MAX_SHIFT 16 267#define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16) 268#define EMIF_REG_PR_OLD_COUNT_SHIFT 0 269#define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0) 270 271/* OCP_CFG_VAL_1 */ 272#define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30 273#define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) 274#define EMIF_REG_LL_BUS_WIDTH_SHIFT 28 275#define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28) 276#define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8 277#define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8) 278#define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0 279#define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) 280 281/* OCP_CFG_VAL_2 */ 282#define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16 283#define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) 284#define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8 285#define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) 286#define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0 287#define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) 288 289/* IODFT_TLGC */ 290#define EMIF_REG_TLEC_SHIFT 16 291#define EMIF_REG_TLEC_MASK (0xffff << 16) 292#define EMIF_REG_MT_SHIFT 14 293#define EMIF_REG_MT_MASK (1 << 14) 294#define EMIF_REG_ACT_CAP_EN_SHIFT 13 295#define EMIF_REG_ACT_CAP_EN_MASK (1 << 13) 296#define EMIF_REG_OPG_LD_SHIFT 12 297#define EMIF_REG_OPG_LD_MASK (1 << 12) 298#define EMIF_REG_RESET_PHY_SHIFT 10 299#define EMIF_REG_RESET_PHY_MASK (1 << 10) 300#define EMIF_REG_MMS_SHIFT 8 301#define EMIF_REG_MMS_MASK (1 << 8) 302#define EMIF_REG_MC_SHIFT 4 303#define EMIF_REG_MC_MASK (0x3 << 4) 304#define EMIF_REG_PC_SHIFT 1 305#define EMIF_REG_PC_MASK (0x7 << 1) 306#define EMIF_REG_TM_SHIFT 0 307#define EMIF_REG_TM_MASK (1 << 0) 308 309/* IODFT_CTRL_MISR_RSLT */ 310#define EMIF_REG_DQM_TLMR_SHIFT 16 311#define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16) 312#define EMIF_REG_CTL_TLMR_SHIFT 0 313#define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0) 314 315/* IODFT_ADDR_MISR_RSLT */ 316#define EMIF_REG_ADDR_TLMR_SHIFT 0 317#define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0) 318 319/* IODFT_DATA_MISR_RSLT_1 */ 320#define EMIF_REG_DATA_TLMR_31_0_SHIFT 0 321#define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) 322 323/* IODFT_DATA_MISR_RSLT_2 */ 324#define EMIF_REG_DATA_TLMR_63_32_SHIFT 0 325#define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) 326 327/* IODFT_DATA_MISR_RSLT_3 */ 328#define EMIF_REG_DATA_TLMR_66_64_SHIFT 0 329#define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0) 330 331/* PERF_CNT_1 */ 332#define EMIF_REG_COUNTER1_SHIFT 0 333#define EMIF_REG_COUNTER1_MASK (0xffffffff << 0) 334 335/* PERF_CNT_2 */ 336#define EMIF_REG_COUNTER2_SHIFT 0 337#define EMIF_REG_COUNTER2_MASK (0xffffffff << 0) 338 339/* PERF_CNT_CFG */ 340#define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31 341#define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31) 342#define EMIF_REG_CNTR2_REGION_EN_SHIFT 30 343#define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30) 344#define EMIF_REG_CNTR2_CFG_SHIFT 16 345#define EMIF_REG_CNTR2_CFG_MASK (0xf << 16) 346#define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15 347#define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15) 348#define EMIF_REG_CNTR1_REGION_EN_SHIFT 14 349#define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14) 350#define EMIF_REG_CNTR1_CFG_SHIFT 0 351#define EMIF_REG_CNTR1_CFG_MASK (0xf << 0) 352 353/* PERF_CNT_SEL */ 354#define EMIF_REG_MCONNID2_SHIFT 24 355#define EMIF_REG_MCONNID2_MASK (0xff << 24) 356#define EMIF_REG_REGION_SEL2_SHIFT 16 357#define EMIF_REG_REGION_SEL2_MASK (0x3 << 16) 358#define EMIF_REG_MCONNID1_SHIFT 8 359#define EMIF_REG_MCONNID1_MASK (0xff << 8) 360#define EMIF_REG_REGION_SEL1_SHIFT 0 361#define EMIF_REG_REGION_SEL1_MASK (0x3 << 0) 362 363/* PERF_CNT_TIM */ 364#define EMIF_REG_TOTAL_TIME_SHIFT 0 365#define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0) 366 367/* READ_IDLE_CTRL */ 368#define EMIF_REG_READ_IDLE_LEN_SHIFT 16 369#define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16) 370#define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0 371#define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) 372 373/* READ_IDLE_CTRL_SHDW */ 374#define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16 375#define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) 376#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 377#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) 378 379/* IRQ_EOI */ 380#define EMIF_REG_EOI_SHIFT 0 381#define EMIF_REG_EOI_MASK (1 << 0) 382 383/* IRQSTATUS_RAW_SYS */ 384#define EMIF_REG_DNV_SYS_SHIFT 2 385#define EMIF_REG_DNV_SYS_MASK (1 << 2) 386#define EMIF_REG_TA_SYS_SHIFT 1 387#define EMIF_REG_TA_SYS_MASK (1 << 1) 388#define EMIF_REG_ERR_SYS_SHIFT 0 389#define EMIF_REG_ERR_SYS_MASK (1 << 0) 390 391/* IRQSTATUS_RAW_LL */ 392#define EMIF_REG_DNV_LL_SHIFT 2 393#define EMIF_REG_DNV_LL_MASK (1 << 2) 394#define EMIF_REG_TA_LL_SHIFT 1 395#define EMIF_REG_TA_LL_MASK (1 << 1) 396#define EMIF_REG_ERR_LL_SHIFT 0 397#define EMIF_REG_ERR_LL_MASK (1 << 0) 398 399/* IRQSTATUS_SYS */ 400 401/* IRQSTATUS_LL */ 402 403/* IRQENABLE_SET_SYS */ 404#define EMIF_REG_EN_DNV_SYS_SHIFT 2 405#define EMIF_REG_EN_DNV_SYS_MASK (1 << 2) 406#define EMIF_REG_EN_TA_SYS_SHIFT 1 407#define EMIF_REG_EN_TA_SYS_MASK (1 << 1) 408#define EMIF_REG_EN_ERR_SYS_SHIFT 0 409#define EMIF_REG_EN_ERR_SYS_MASK (1 << 0) 410 411/* IRQENABLE_SET_LL */ 412#define EMIF_REG_EN_DNV_LL_SHIFT 2 413#define EMIF_REG_EN_DNV_LL_MASK (1 << 2) 414#define EMIF_REG_EN_TA_LL_SHIFT 1 415#define EMIF_REG_EN_TA_LL_MASK (1 << 1) 416#define EMIF_REG_EN_ERR_LL_SHIFT 0 417#define EMIF_REG_EN_ERR_LL_MASK (1 << 0) 418 419/* IRQENABLE_CLR_SYS */ 420 421/* IRQENABLE_CLR_LL */ 422 423/* ZQ_CONFIG */ 424#define EMIF_REG_ZQ_CS1EN_SHIFT 31 425#define EMIF_REG_ZQ_CS1EN_MASK (1 << 31) 426#define EMIF_REG_ZQ_CS0EN_SHIFT 30 427#define EMIF_REG_ZQ_CS0EN_MASK (1 << 30) 428#define EMIF_REG_ZQ_DUALCALEN_SHIFT 29 429#define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29) 430#define EMIF_REG_ZQ_SFEXITEN_SHIFT 28 431#define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28) 432#define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18 433#define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) 434#define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16 435#define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) 436#define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0 437#define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) 438 439/* TEMP_ALERT_CONFIG */ 440#define EMIF_REG_TA_CS1EN_SHIFT 31 441#define EMIF_REG_TA_CS1EN_MASK (1 << 31) 442#define EMIF_REG_TA_CS0EN_SHIFT 30 443#define EMIF_REG_TA_CS0EN_MASK (1 << 30) 444#define EMIF_REG_TA_SFEXITEN_SHIFT 28 445#define EMIF_REG_TA_SFEXITEN_MASK (1 << 28) 446#define EMIF_REG_TA_DEVWDT_SHIFT 26 447#define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26) 448#define EMIF_REG_TA_DEVCNT_SHIFT 24 449#define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24) 450#define EMIF_REG_TA_REFINTERVAL_SHIFT 0 451#define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) 452 453/* OCP_ERR_LOG */ 454#define EMIF_REG_MADDRSPACE_SHIFT 14 455#define EMIF_REG_MADDRSPACE_MASK (0x3 << 14) 456#define EMIF_REG_MBURSTSEQ_SHIFT 11 457#define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11) 458#define EMIF_REG_MCMD_SHIFT 8 459#define EMIF_REG_MCMD_MASK (0x7 << 8) 460#define EMIF_REG_MCONNID_SHIFT 0 461#define EMIF_REG_MCONNID_MASK (0xff << 0) 462 463/* DDR_PHY_CTRL_1 */ 464#define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4 465#define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) 466#define EMIF_REG_READ_LATENCY_SHIFT 0 467#define EMIF_REG_READ_LATENCY_MASK (0xf << 0) 468#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 469#define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) 470#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 471#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) 472 473/* DDR_PHY_CTRL_1_SHDW */ 474#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 475#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) 476#define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0 477#define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0) 478#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 479#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) 480#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 481#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) 482#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT 25 483#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK (1 << 25) 484#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT 26 485#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK (1 << 26) 486#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT 27 487#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK (1 << 27) 488 489/* DDR_PHY_CTRL_2 */ 490#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 491#define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) 492 493/*EMIF_READ_WRITE_LEVELING_CONTROL*/ 494#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 495#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) 496#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 497#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) 498#define EMIF_REG_RDLVLINC_INT_SHIFT 16 499#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) 500#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 501#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) 502#define EMIF_REG_WRLVLINC_INT_SHIFT 0 503#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) 504 505/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ 506#define EMIF_REG_RDWRLVL_EN_SHIFT 31 507#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) 508#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 509#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) 510#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 511#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) 512#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 513#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) 514#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 515#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) 516 517/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ 518#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 519#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) 520 521/* EMIF_PHY_CTRL_36 */ 522#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR (1 << 8) 523 524#define PHY_RDDQS_RATIO_REGS 5 525#define PHY_FIFO_WE_SLAVE_RATIO_REGS 5 526#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS 10 527 528/*Leveling Fields */ 529#define DDR3_WR_LVL_INT 0x73 530#define DDR3_RD_LVL_INT 0x33 531#define DDR3_RD_LVL_GATE_INT 0x59 532#define RD_RW_LVL_INC_PRE 0x0 533#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) 534 535#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ 536 | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ 537 | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ 538 | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) 539 540#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 541#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 542#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7 543 544/* DMM */ 545#define DMM_BASE 0x4E000040 546 547/* Memory Adapter */ 548#define MA_BASE 0x482AF040 549#define MA_PRIORITY 0x482A2000 550#define MA_HIMEM_INTERLEAVE_UN_SHIFT 8 551#define MA_HIMEM_INTERLEAVE_UN_MASK (1 << 8) 552 553/* DMM_LISA_MAP */ 554#define EMIF_SYS_ADDR_SHIFT 24 555#define EMIF_SYS_ADDR_MASK (0xff << 24) 556#define EMIF_SYS_SIZE_SHIFT 20 557#define EMIF_SYS_SIZE_MASK (0x7 << 20) 558#define EMIF_SDRC_INTL_SHIFT 18 559#define EMIF_SDRC_INTL_MASK (0x3 << 18) 560#define EMIF_SDRC_ADDRSPC_SHIFT 16 561#define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16) 562#define EMIF_SDRC_MAP_SHIFT 8 563#define EMIF_SDRC_MAP_MASK (0x3 << 8) 564#define EMIF_SDRC_ADDR_SHIFT 0 565#define EMIF_SDRC_ADDR_MASK (0xff << 0) 566 567/* DMM_LISA_MAP fields */ 568#define DMM_SDRC_MAP_UNMAPPED 0 569#define DMM_SDRC_MAP_EMIF1_ONLY 1 570#define DMM_SDRC_MAP_EMIF2_ONLY 2 571#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 572 573#define DMM_SDRC_INTL_NONE 0 574#define DMM_SDRC_INTL_128B 1 575#define DMM_SDRC_INTL_256B 2 576#define DMM_SDRC_INTL_512 3 577 578#define DMM_SDRC_ADDR_SPC_SDRAM 0 579#define DMM_SDRC_ADDR_SPC_NVM 1 580#define DMM_SDRC_ADDR_SPC_INVALID 2 581 582#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ 583 (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ 584 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ 585 (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ 586 (CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) 587 588#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ 589 (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ 590 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ 591 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) 592 593#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ 594 (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\ 595 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ 596 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) 597 598/* Trap for invalid TILER PAT entries */ 599#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ 600 (0 << EMIF_SDRC_ADDR_SHIFT) |\ 601 (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ 602 (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\ 603 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\ 604 (0xFF << EMIF_SYS_ADDR_SHIFT)) 605 606#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 607 608/* EMIF ECC CTRL reg */ 609#define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT 31 610#define EMIF_ECC_CTRL_REG_ECC_EN_MASK (1 << 31) 611#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT 30 612#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK (1 << 30) 613#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT 29 614#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK (1 << 29) 615#define EMIF_ECC_REG_RMW_EN_SHIFT 28 616#define EMIF_ECC_REG_RMW_EN_MASK (1 << 28) 617#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT 1 618#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK (1 << 1) 619#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT 0 620#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK (1 << 0) 621 622/* EMIF ECC ADDRESS RANGE */ 623#define EMIF_ECC_REG_ECC_END_ADDR_SHIFT 16 624#define EMIF_ECC_REG_ECC_END_ADDR_MASK (0xffff << 16) 625#define EMIF_ECC_REG_ECC_START_ADDR_SHIFT 0 626#define EMIF_ECC_REG_ECC_START_ADDR_MASK (0xffff << 0) 627 628/* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */ 629#define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT 5 630#define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK (1 << 5) 631#define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT 4 632#define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK (1 << 4) 633#define EMIF_INT_WR_ECC_ERR_SYS_SHIFT 3 634#define EMIF_INT_WR_ECC_ERR_SYS_MASK (1 << 3) 635 636/* Reg mapping structure */ 637struct emif_reg_struct { 638 u32 emif_mod_id_rev; 639 u32 emif_status; 640 u32 emif_sdram_config; 641 u32 emif_lpddr2_nvm_config; 642 u32 emif_sdram_ref_ctrl; 643 u32 emif_sdram_ref_ctrl_shdw; 644 u32 emif_sdram_tim_1; 645 u32 emif_sdram_tim_1_shdw; 646 u32 emif_sdram_tim_2; 647 u32 emif_sdram_tim_2_shdw; 648 u32 emif_sdram_tim_3; 649 u32 emif_sdram_tim_3_shdw; 650 u32 emif_lpddr2_nvm_tim; 651 u32 emif_lpddr2_nvm_tim_shdw; 652 u32 emif_pwr_mgmt_ctrl; 653 u32 emif_pwr_mgmt_ctrl_shdw; 654 u32 emif_lpddr2_mode_reg_data; 655 u32 padding1[1]; 656 u32 emif_lpddr2_mode_reg_data_es2; 657 u32 padding11[1]; 658 u32 emif_lpddr2_mode_reg_cfg; 659 u32 emif_l3_config; 660 u32 emif_l3_cfg_val_1; 661 u32 emif_l3_cfg_val_2; 662 u32 emif_iodft_tlgc; 663 u32 padding2[7]; 664 u32 emif_perf_cnt_1; 665 u32 emif_perf_cnt_2; 666 u32 emif_perf_cnt_cfg; 667 u32 emif_perf_cnt_sel; 668 u32 emif_perf_cnt_tim; 669 u32 padding3; 670 u32 emif_read_idlectrl; 671 u32 emif_read_idlectrl_shdw; 672 u32 padding4; 673 u32 emif_irqstatus_raw_sys; 674 u32 emif_irqstatus_raw_ll; 675 u32 emif_irqstatus_sys; 676 u32 emif_irqstatus_ll; 677 u32 emif_irqenable_set_sys; 678 u32 emif_irqenable_set_ll; 679 u32 emif_irqenable_clr_sys; 680 u32 emif_irqenable_clr_ll; 681 u32 padding5; 682 u32 emif_zq_config; 683 u32 emif_temp_alert_config; 684 u32 emif_l3_err_log; 685 u32 emif_rd_wr_lvl_rmp_win; 686 u32 emif_rd_wr_lvl_rmp_ctl; 687 u32 emif_rd_wr_lvl_ctl; 688 u32 padding6[1]; 689 u32 emif_ddr_phy_ctrl_1; 690 u32 emif_ddr_phy_ctrl_1_shdw; 691 u32 emif_ddr_phy_ctrl_2; 692 u32 padding7[4]; 693 u32 emif_prio_class_serv_map; 694 u32 emif_connect_id_serv_1_map; 695 u32 emif_connect_id_serv_2_map; 696 u32 padding8; 697 u32 emif_ecc_ctrl_reg; 698 u32 emif_ecc_address_range_1; 699 u32 emif_ecc_address_range_2; 700 u32 padding8_1; 701 u32 emif_rd_wr_exec_thresh; 702 u32 emif_cos_config; 703#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE) 704 u32 padding9[2]; 705 u32 emif_1b_ecc_err_cnt; 706 u32 emif_1b_ecc_err_thrush; 707 u32 emif_1b_ecc_err_dist_1; 708 u32 emif_1b_ecc_err_addr_log; 709 u32 emif_2b_ecc_err_addr_log; 710 u32 emif_ddr_phy_status[28]; 711 u32 padding10[19]; 712#else 713 u32 padding9[6]; 714 u32 emif_ddr_phy_status[28]; 715 u32 padding10[20]; 716#endif 717 u32 emif_ddr_ext_phy_ctrl_1; 718 u32 emif_ddr_ext_phy_ctrl_1_shdw; 719 u32 emif_ddr_ext_phy_ctrl_2; 720 u32 emif_ddr_ext_phy_ctrl_2_shdw; 721 u32 emif_ddr_ext_phy_ctrl_3; 722 u32 emif_ddr_ext_phy_ctrl_3_shdw; 723 u32 emif_ddr_ext_phy_ctrl_4; 724 u32 emif_ddr_ext_phy_ctrl_4_shdw; 725 u32 emif_ddr_ext_phy_ctrl_5; 726 u32 emif_ddr_ext_phy_ctrl_5_shdw; 727 u32 emif_ddr_ext_phy_ctrl_6; 728 u32 emif_ddr_ext_phy_ctrl_6_shdw; 729 u32 emif_ddr_ext_phy_ctrl_7; 730 u32 emif_ddr_ext_phy_ctrl_7_shdw; 731 u32 emif_ddr_ext_phy_ctrl_8; 732 u32 emif_ddr_ext_phy_ctrl_8_shdw; 733 u32 emif_ddr_ext_phy_ctrl_9; 734 u32 emif_ddr_ext_phy_ctrl_9_shdw; 735 u32 emif_ddr_ext_phy_ctrl_10; 736 u32 emif_ddr_ext_phy_ctrl_10_shdw; 737 u32 emif_ddr_ext_phy_ctrl_11; 738 u32 emif_ddr_ext_phy_ctrl_11_shdw; 739 u32 emif_ddr_ext_phy_ctrl_12; 740 u32 emif_ddr_ext_phy_ctrl_12_shdw; 741 u32 emif_ddr_ext_phy_ctrl_13; 742 u32 emif_ddr_ext_phy_ctrl_13_shdw; 743 u32 emif_ddr_ext_phy_ctrl_14; 744 u32 emif_ddr_ext_phy_ctrl_14_shdw; 745 u32 emif_ddr_ext_phy_ctrl_15; 746 u32 emif_ddr_ext_phy_ctrl_15_shdw; 747 u32 emif_ddr_ext_phy_ctrl_16; 748 u32 emif_ddr_ext_phy_ctrl_16_shdw; 749 u32 emif_ddr_ext_phy_ctrl_17; 750 u32 emif_ddr_ext_phy_ctrl_17_shdw; 751 u32 emif_ddr_ext_phy_ctrl_18; 752 u32 emif_ddr_ext_phy_ctrl_18_shdw; 753 u32 emif_ddr_ext_phy_ctrl_19; 754 u32 emif_ddr_ext_phy_ctrl_19_shdw; 755 u32 emif_ddr_ext_phy_ctrl_20; 756 u32 emif_ddr_ext_phy_ctrl_20_shdw; 757 u32 emif_ddr_ext_phy_ctrl_21; 758 u32 emif_ddr_ext_phy_ctrl_21_shdw; 759 u32 emif_ddr_ext_phy_ctrl_22; 760 u32 emif_ddr_ext_phy_ctrl_22_shdw; 761 u32 emif_ddr_ext_phy_ctrl_23; 762 u32 emif_ddr_ext_phy_ctrl_23_shdw; 763 u32 emif_ddr_ext_phy_ctrl_24; 764 u32 emif_ddr_ext_phy_ctrl_24_shdw; 765 u32 emif_ddr_ext_phy_ctrl_25; 766 u32 emif_ddr_ext_phy_ctrl_25_shdw; 767 u32 emif_ddr_ext_phy_ctrl_26; 768 u32 emif_ddr_ext_phy_ctrl_26_shdw; 769 u32 emif_ddr_ext_phy_ctrl_27; 770 u32 emif_ddr_ext_phy_ctrl_27_shdw; 771 u32 emif_ddr_ext_phy_ctrl_28; 772 u32 emif_ddr_ext_phy_ctrl_28_shdw; 773 u32 emif_ddr_ext_phy_ctrl_29; 774 u32 emif_ddr_ext_phy_ctrl_29_shdw; 775 u32 emif_ddr_ext_phy_ctrl_30; 776 u32 emif_ddr_ext_phy_ctrl_30_shdw; 777 u32 emif_ddr_ext_phy_ctrl_31; 778 u32 emif_ddr_ext_phy_ctrl_31_shdw; 779 u32 emif_ddr_ext_phy_ctrl_32; 780 u32 emif_ddr_ext_phy_ctrl_32_shdw; 781 u32 emif_ddr_ext_phy_ctrl_33; 782 u32 emif_ddr_ext_phy_ctrl_33_shdw; 783 u32 emif_ddr_ext_phy_ctrl_34; 784 u32 emif_ddr_ext_phy_ctrl_34_shdw; 785 u32 emif_ddr_ext_phy_ctrl_35; 786 u32 emif_ddr_ext_phy_ctrl_35_shdw; 787 union { 788 u32 emif_ddr_ext_phy_ctrl_36; 789 u32 emif_ddr_fifo_misaligned_clear_1; 790 }; 791 union { 792 u32 emif_ddr_ext_phy_ctrl_36_shdw; 793 u32 emif_ddr_fifo_misaligned_clear_2; 794 }; 795}; 796 797struct dmm_lisa_map_regs { 798 u32 dmm_lisa_map_0; 799 u32 dmm_lisa_map_1; 800 u32 dmm_lisa_map_2; 801 u32 dmm_lisa_map_3; 802 u8 is_ma_present; 803}; 804 805#define CS0 0 806#define CS1 1 807/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ 808#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ 809 810/* 811 * The period of DDR clk is represented as numerator and denominator for 812 * better accuracy in integer based calculations. However, if the numerator 813 * and denominator are very huge there may be chances of overflow in 814 * calculations. So, as a trade-off keep denominator(and consequently 815 * numerator) within a limit sacrificing some accuracy - but not much 816 * If denominator and numerator are already small (such as at 400 MHz) 817 * no adjustment is needed 818 */ 819#define EMIF_PERIOD_DEN_LIMIT 1000 820/* 821 * Maximum number of different frequencies supported by EMIF driver 822 * Determines the number of entries in the pointer array for register 823 * cache 824 */ 825#define EMIF_MAX_NUM_FREQUENCIES 6 826/* 827 * Indices into the Addressing Table array. 828 * One entry each for all the different types of devices with different 829 * addressing schemes 830 */ 831#define ADDR_TABLE_INDEX64M 0 832#define ADDR_TABLE_INDEX128M 1 833#define ADDR_TABLE_INDEX256M 2 834#define ADDR_TABLE_INDEX512M 3 835#define ADDR_TABLE_INDEX1GS4 4 836#define ADDR_TABLE_INDEX2GS4 5 837#define ADDR_TABLE_INDEX4G 6 838#define ADDR_TABLE_INDEX8G 7 839#define ADDR_TABLE_INDEX1GS2 8 840#define ADDR_TABLE_INDEX2GS2 9 841#define ADDR_TABLE_INDEXMAX 10 842 843/* Number of Row bits */ 844#define ROW_9 0 845#define ROW_10 1 846#define ROW_11 2 847#define ROW_12 3 848#define ROW_13 4 849#define ROW_14 5 850#define ROW_15 6 851#define ROW_16 7 852 853/* Number of Column bits */ 854#define COL_8 0 855#define COL_9 1 856#define COL_10 2 857#define COL_11 3 858#define COL_7 4 /*Not supported by OMAP included for completeness */ 859 860/* Number of Banks*/ 861#define BANKS1 0 862#define BANKS2 1 863#define BANKS4 2 864#define BANKS8 3 865 866/* Refresh rate in micro seconds x 10 */ 867#define T_REFI_15_6 156 868#define T_REFI_7_8 78 869#define T_REFI_3_9 39 870 871#define EBANK_CS1_DIS 0 872#define EBANK_CS1_EN 1 873 874/* Read Latency used by the device at reset */ 875#define RL_BOOT 3 876/* Read Latency for the highest frequency you want to use */ 877#ifdef CONFIG_OMAP54XX 878#define RL_FINAL 8 879#else 880#define RL_FINAL 6 881#endif 882 883 884/* Interleaving policies at EMIF level- between banks and Chip Selects */ 885#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 886#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 887 888/* 889 * Interleaving policy to be used 890 * Currently set to MAX interleaving for better performance 891 */ 892#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 893 894/* State of the core voltage: 895 * This is important for some parameters such as read idle control and 896 * ZQ calibration timings. Timings are much stricter when voltage ramp 897 * is happening compared to when the voltage is stable. 898 * We need to calculate two sets of values for these parameters and use 899 * them accordingly 900 */ 901#define LPDDR2_VOLTAGE_STABLE 0 902#define LPDDR2_VOLTAGE_RAMPING 1 903 904/* Length of the forced read idle period in terms of cycles */ 905#define EMIF_REG_READ_IDLE_LEN_VAL 5 906 907/* Interval between forced 'read idles' */ 908/* To be used when voltage is changed for DPS/DVFS - 1us */ 909#define READ_IDLE_INTERVAL_DVFS (1*1000) 910/* 911 * To be used when voltage is not scaled except by Smart Reflex 912 * 50us - or maximum value will do 913 */ 914#define READ_IDLE_INTERVAL_NORMAL (50*1000) 915 916 917/* 918 * Unless voltage is changing due to DVFS one ZQCS command every 50ms should 919 * be enough. This shoule be enough also in the case when voltage is changing 920 * due to smart-reflex. 921 */ 922#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) 923/* 924 * If voltage is changing due to DVFS ZQCS should be performed more 925 * often(every 50us) 926 */ 927#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 928 929/* The interval between ZQCL commands as a multiple of ZQCS interval */ 930#define REG_ZQ_ZQCL_MULT 4 931/* The interval between ZQINIT commands as a multiple of ZQCL interval */ 932#define REG_ZQ_ZQINIT_MULT 3 933/* Enable ZQ Calibration on exiting Self-refresh */ 934#define REG_ZQ_SFEXITEN_ENABLE 1 935/* 936 * ZQ Calibration simultaneously on both chip-selects: 937 * Needs one calibration resistor per CS 938 * None of the boards that we know of have this capability 939 * So disabled by default 940 */ 941#define REG_ZQ_DUALCALEN_DISABLE 0 942/* 943 * Enable ZQ Calibration by default on CS0. If we are asked to program 944 * the EMIF there will be something connected to CS0 for sure 945 */ 946#define REG_ZQ_CS0EN_ENABLE 1 947 948/* EMIF_PWR_MGMT_CTRL register */ 949/* Low power modes */ 950#define LP_MODE_DISABLE 0 951#define LP_MODE_CLOCK_STOP 1 952#define LP_MODE_SELF_REFRESH 2 953#define LP_MODE_PWR_DN 3 954 955/* REG_DPD_EN */ 956#define DPD_DISABLE 0 957#define DPD_ENABLE 1 958 959/* Maximum delay before Low Power Modes */ 960#define REG_CS_TIM 0x0 961#define REG_SR_TIM 0xF 962#define REG_PD_TIM 0xF 963 964 965/* EMIF_PWR_MGMT_CTRL register */ 966#define EMIF_PWR_MGMT_CTRL (\ 967 ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ 968 ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\ 969 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ 970 ((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)\ 971 & EMIF_REG_LP_MODE_MASK) |\ 972 ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\ 973 & EMIF_REG_DPD_EN_MASK))\ 974 975#define EMIF_PWR_MGMT_CTRL_SHDW (\ 976 ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\ 977 & EMIF_REG_CS_TIM_SHDW_MASK) |\ 978 ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\ 979 & EMIF_REG_SR_TIM_SHDW_MASK) |\ 980 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ 981 & EMIF_REG_PD_TIM_SHDW_MASK)) 982 983/* EMIF_L3_CONFIG register value */ 984#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF 985#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 986#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A500000 987 988/* 989 * Value of bits 12:31 of DDR_PHY_CTRL_1 register: 990 * All these fields have magic values dependent on frequency and 991 * determined by PHY and DLL integration with EMIF. Setting the magic 992 * values suggested by hw team. 993 */ 994#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF 995#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 996#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 997#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF 998 999/* 1000* MR1 value: 1001* Burst length : 8 1002* Burst type : sequential 1003* Wrap : enabled 1004* nWR : 3(default). EMIF does not do pre-charge. 1005* : So nWR is don't care 1006*/ 1007#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 1008#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8 0xc3 1009 1010/* MR2 */ 1011#define MR2_RL3_WL1 1 1012#define MR2_RL4_WL2 2 1013#define MR2_RL5_WL2 3 1014#define MR2_RL6_WL3 4 1015 1016/* MR10: ZQ calibration codes */ 1017#define MR10_ZQ_ZQCS 0x56 1018#define MR10_ZQ_ZQCL 0xAB 1019#define MR10_ZQ_ZQINIT 0xFF 1020#define MR10_ZQ_ZQRESET 0xC3 1021 1022/* TEMP_ALERT_CONFIG */ 1023#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ 1024#define TEMP_ALERT_CONFIG_DEVCT_1 0 1025#define TEMP_ALERT_CONFIG_DEVWDT_32 2 1026 1027/* MR16 value: refresh full array(no partial array self refresh) */ 1028#define MR16_REF_FULL_ARRAY 0 1029 1030/* 1031 * Maximum number of entries we keep in our array of timing tables 1032 * We need not keep all the speed bins supported by the device 1033 * We need to keep timing tables for only the speed bins that we 1034 * are interested in 1035 */ 1036#define MAX_NUM_SPEEDBINS 4 1037 1038/* LPDDR2 Densities */ 1039#define LPDDR2_DENSITY_64Mb 0 1040#define LPDDR2_DENSITY_128Mb 1 1041#define LPDDR2_DENSITY_256Mb 2 1042#define LPDDR2_DENSITY_512Mb 3 1043#define LPDDR2_DENSITY_1Gb 4 1044#define LPDDR2_DENSITY_2Gb 5 1045#define LPDDR2_DENSITY_4Gb 6 1046#define LPDDR2_DENSITY_8Gb 7 1047#define LPDDR2_DENSITY_16Gb 8 1048#define LPDDR2_DENSITY_32Gb 9 1049 1050/* LPDDR2 type */ 1051#define LPDDR2_TYPE_S4 0 1052#define LPDDR2_TYPE_S2 1 1053#define LPDDR2_TYPE_NVM 2 1054 1055/* LPDDR2 IO width */ 1056#define LPDDR2_IO_WIDTH_32 0 1057#define LPDDR2_IO_WIDTH_16 1 1058#define LPDDR2_IO_WIDTH_8 2 1059 1060/* Mode register numbers */ 1061#define LPDDR2_MR0 0 1062#define LPDDR2_MR1 1 1063#define LPDDR2_MR2 2 1064#define LPDDR2_MR3 3 1065#define LPDDR2_MR4 4 1066#define LPDDR2_MR5 5 1067#define LPDDR2_MR6 6 1068#define LPDDR2_MR7 7 1069#define LPDDR2_MR8 8 1070#define LPDDR2_MR9 9 1071#define LPDDR2_MR10 10 1072#define LPDDR2_MR11 11 1073#define LPDDR2_MR16 16 1074#define LPDDR2_MR17 17 1075#define LPDDR2_MR18 18 1076 1077/* MR0 */ 1078#define LPDDR2_MR0_DAI_SHIFT 0 1079#define LPDDR2_MR0_DAI_MASK 1 1080#define LPDDR2_MR0_DI_SHIFT 1 1081#define LPDDR2_MR0_DI_MASK (1 << 1) 1082#define LPDDR2_MR0_DNVI_SHIFT 2 1083#define LPDDR2_MR0_DNVI_MASK (1 << 2) 1084 1085/* MR4 */ 1086#define MR4_SDRAM_REF_RATE_SHIFT 0 1087#define MR4_SDRAM_REF_RATE_MASK 7 1088#define MR4_TUF_SHIFT 7 1089#define MR4_TUF_MASK (1 << 7) 1090 1091/* MR4 SDRAM Refresh Rate field values */ 1092#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 1093#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 1094#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 1095#define SDRAM_TEMP_NOMINAL 0x3 1096#define SDRAM_TEMP_RESERVED_4 0x4 1097#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 1098#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 1099#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 1100 1101#define LPDDR2_MANUFACTURER_SAMSUNG 1 1102#define LPDDR2_MANUFACTURER_QIMONDA 2 1103#define LPDDR2_MANUFACTURER_ELPIDA 3 1104#define LPDDR2_MANUFACTURER_ETRON 4 1105#define LPDDR2_MANUFACTURER_NANYA 5 1106#define LPDDR2_MANUFACTURER_HYNIX 6 1107#define LPDDR2_MANUFACTURER_MOSEL 7 1108#define LPDDR2_MANUFACTURER_WINBOND 8 1109#define LPDDR2_MANUFACTURER_ESMT 9 1110#define LPDDR2_MANUFACTURER_SPANSION 11 1111#define LPDDR2_MANUFACTURER_SST 12 1112#define LPDDR2_MANUFACTURER_ZMOS 13 1113#define LPDDR2_MANUFACTURER_INTEL 14 1114#define LPDDR2_MANUFACTURER_NUMONYX 254 1115#define LPDDR2_MANUFACTURER_MICRON 255 1116 1117/* MR8 register fields */ 1118#define MR8_TYPE_SHIFT 0x0 1119#define MR8_TYPE_MASK 0x3 1120#define MR8_DENSITY_SHIFT 0x2 1121#define MR8_DENSITY_MASK (0xF << 0x2) 1122#define MR8_IO_WIDTH_SHIFT 0x6 1123#define MR8_IO_WIDTH_MASK (0x3 << 0x6) 1124 1125/* SDRAM TYPE */ 1126#define EMIF_SDRAM_TYPE_DDR2 0x2 1127#define EMIF_SDRAM_TYPE_DDR3 0x3 1128#define EMIF_SDRAM_TYPE_LPDDR2 0x4 1129 1130struct lpddr2_addressing { 1131 u8 num_banks; 1132 u8 t_REFI_us_x10; 1133 u8 row_sz[2]; /* One entry each for x32 and x16 */ 1134 u8 col_sz[2]; /* One entry each for x32 and x16 */ 1135}; 1136 1137/* Structure for timings from the DDR datasheet */ 1138struct lpddr2_ac_timings { 1139 u32 max_freq; 1140 u8 RL; 1141 u8 tRPab; 1142 u8 tRCD; 1143 u8 tWR; 1144 u8 tRASmin; 1145 u8 tRRD; 1146 u8 tWTRx2; 1147 u8 tXSR; 1148 u8 tXPx2; 1149 u8 tRFCab; 1150 u8 tRTPx2; 1151 u8 tCKE; 1152 u8 tCKESR; 1153 u8 tZQCS; 1154 u32 tZQCL; 1155 u32 tZQINIT; 1156 u8 tDQSCKMAXx2; 1157 u8 tRASmax; 1158 u8 tFAW; 1159 1160}; 1161 1162/* 1163 * Min tCK values for some of the parameters: 1164 * If the calculated clock cycles for the respective parameter is 1165 * less than the corresponding min tCK value, we need to set the min 1166 * tCK value. This may happen at lower frequencies. 1167 */ 1168struct lpddr2_min_tck { 1169 u32 tRL; 1170 u32 tRP_AB; 1171 u32 tRCD; 1172 u32 tWR; 1173 u32 tRAS_MIN; 1174 u32 tRRD; 1175 u32 tWTR; 1176 u32 tXP; 1177 u32 tRTP; 1178 u8 tCKE; 1179 u32 tCKESR; 1180 u32 tFAW; 1181}; 1182 1183struct lpddr2_device_details { 1184 u8 type; 1185 u8 density; 1186 u8 io_width; 1187 u8 manufacturer; 1188}; 1189 1190struct lpddr2_device_timings { 1191 const struct lpddr2_ac_timings **ac_timings; 1192 const struct lpddr2_min_tck *min_tck; 1193}; 1194 1195/* Details of the devices connected to each chip-select of an EMIF instance */ 1196struct emif_device_details { 1197 const struct lpddr2_device_details *cs0_device_details; 1198 const struct lpddr2_device_details *cs1_device_details; 1199 const struct lpddr2_device_timings *cs0_device_timings; 1200 const struct lpddr2_device_timings *cs1_device_timings; 1201}; 1202 1203/* 1204 * Structure containing shadow of important registers in EMIF 1205 * The calculation function fills in this structure to be later used for 1206 * initialization and DVFS 1207 */ 1208struct emif_regs { 1209 u32 freq; 1210 u32 sdram_config_init; 1211 u32 sdram_config; 1212 u32 sdram_config2; 1213 u32 ref_ctrl; 1214 u32 ref_ctrl_final; 1215 u32 sdram_tim1; 1216 u32 sdram_tim2; 1217 u32 sdram_tim3; 1218 u32 ocp_config; 1219 u32 read_idle_ctrl; 1220 u32 zq_config; 1221 u32 temp_alert_config; 1222 u32 emif_ddr_phy_ctlr_1_init; 1223 u32 emif_ddr_phy_ctlr_1; 1224 u32 emif_ddr_ext_phy_ctrl_1; 1225 u32 emif_ddr_ext_phy_ctrl_2; 1226 u32 emif_ddr_ext_phy_ctrl_3; 1227 u32 emif_ddr_ext_phy_ctrl_4; 1228 u32 emif_ddr_ext_phy_ctrl_5; 1229 u32 emif_rd_wr_lvl_rmp_win; 1230 u32 emif_rd_wr_lvl_rmp_ctl; 1231 u32 emif_rd_wr_lvl_ctl; 1232 u32 emif_rd_wr_exec_thresh; 1233 u32 emif_prio_class_serv_map; 1234 u32 emif_connect_id_serv_1_map; 1235 u32 emif_connect_id_serv_2_map; 1236 u32 emif_cos_config; 1237 u32 emif_ecc_ctrl_reg; 1238 u32 emif_ecc_address_range_1; 1239 u32 emif_ecc_address_range_2; 1240}; 1241 1242struct lpddr2_mr_regs { 1243 s8 mr1; 1244 s8 mr2; 1245 s8 mr3; 1246 s8 mr10; 1247 s8 mr16; 1248}; 1249 1250struct read_write_regs { 1251 u32 read_reg; 1252 u32 write_reg; 1253}; 1254 1255static inline u32 get_emif_rev(u32 base) 1256{ 1257 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; 1258 1259 return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK) 1260 >> EMIF_REG_MAJOR_REVISION_SHIFT; 1261} 1262 1263/* 1264 * Get SDRAM type connected to EMIF. 1265 * Assuming similar SDRAM parts are connected to both EMIF's 1266 * which is typically the case. So it is sufficient to get 1267 * SDRAM type from EMIF1. 1268 */ 1269static inline u32 emif_sdram_type(u32 sdram_config) 1270{ 1271 return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK) 1272 >> EMIF_REG_SDRAM_TYPE_SHIFT; 1273} 1274 1275/* assert macros */ 1276#if defined(DEBUG) 1277#define emif_assert(c) ({ if (!(c)) for (;;); }) 1278#else 1279#define emif_assert(c) ({ if (0) hang(); }) 1280#endif 1281 1282#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 1283void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs); 1284void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); 1285#else 1286struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, 1287 struct lpddr2_device_details *lpddr2_dev_details); 1288void emif_get_device_timings(u32 emif_nr, 1289 const struct lpddr2_device_timings **cs0_device_timings, 1290 const struct lpddr2_device_timings **cs1_device_timings); 1291#endif 1292 1293void do_ext_phy_settings(u32 base, const struct emif_regs *regs); 1294void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs); 1295 1296#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 1297extern u32 *const T_num; 1298extern u32 *const T_den; 1299#endif 1300 1301void config_data_eye_leveling_samples(u32 emif_base); 1302const struct read_write_regs *get_bug_regs(u32 *iterations); 1303#endif 1304