1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7/* Tegra210 clock control definitions */
8
9#ifndef _TEGRA210_CLOCK_H_
10#define _TEGRA210_CLOCK_H_
11
12#include <asm/arch-tegra/clock.h>
13
14/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
15#define OSC_FREQ_SHIFT          28
16#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
17
18/* PLL bits that differ from generic clk_rst.h */
19#define PLLC_RESET		30
20#define PLLC_IDDQ		27
21#define PLLD_ENABLE_CLK		21
22#define PLLD_EN_LCKDET		28
23
24int tegra_plle_enable(void);
25
26#endif	/* _TEGRA210_CLOCK_H_ */
27