1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  (C) Copyright 2010,2011
4 *  NVIDIA Corporation <www.nvidia.com>
5 */
6
7#ifndef _UART_H_
8#define _UART_H_
9
10/* UART registers */
11struct uart_ctlr {
12	uint uart_thr_dlab_0;		/* UART_THR_DLAB_0_0, offset 00 */
13	uint uart_ier_dlab_0;		/* UART_IER_DLAB_0_0, offset 04 */
14	uint uart_iir_fcr;		/* UART_IIR_FCR_0, offset 08 */
15	uint uart_lcr;			/* UART_LCR_0, offset 0C */
16	uint uart_mcr;			/* UART_MCR_0, offset 10 */
17	uint uart_lsr;			/* UART_LSR_0, offset 14 */
18	uint uart_msr;			/* UART_MSR_0, offset 18 */
19	uint uart_spr;			/* UART_SPR_0, offset 1C */
20	uint uart_irda_csr;		/* UART_IRDA_CSR_0, offset 20 */
21	uint uart_reserved[6];		/* Reserved, unused, offset 24-38*/
22	uint uart_asr;			/* UART_ASR_0, offset 3C */
23};
24
25#define NVRM_PLLP_FIXED_FREQ_KHZ	216000
26#define NV_DEFAULT_DEBUG_BAUD		115200
27
28#define UART_FCR_TRIGGER_3	0x30	/* Mask for trigger set at 3 */
29
30#endif	/* UART_H */
31