1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7#ifndef _TEGRA_H_
8#define _TEGRA_H_
9
10#define NV_PA_ARM_PERIPHBASE	0x50040000
11#define NV_PA_PG_UP_BASE	0x60000000
12#define NV_PA_TMRUS_BASE	0x60005010
13#define NV_PA_CLK_RST_BASE	0x60006000
14#define NV_PA_FLOW_BASE		0x60007000
15#define NV_PA_GPIO_BASE		0x6000D000
16#define NV_PA_EVP_BASE		0x6000F000
17#define NV_PA_APB_MISC_BASE	0x70000000
18#define NV_PA_APB_MISC_GP_BASE	(NV_PA_APB_MISC_BASE + 0x0800)
19#define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
20#define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
21#define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
22#define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
23#define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
24#define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
25#define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
26#define NV_PA_SLINK1_BASE	(NV_PA_APB_MISC_BASE + 0xD400)
27#define NV_PA_SLINK2_BASE	(NV_PA_APB_MISC_BASE + 0xD600)
28#define NV_PA_SLINK3_BASE	(NV_PA_APB_MISC_BASE + 0xD800)
29#define NV_PA_SLINK4_BASE	(NV_PA_APB_MISC_BASE + 0xDA00)
30#define NV_PA_SLINK5_BASE	(NV_PA_APB_MISC_BASE + 0xDC00)
31#define NV_PA_SLINK6_BASE	(NV_PA_APB_MISC_BASE + 0xDE00)
32#define TEGRA_DVC_BASE		(NV_PA_APB_MISC_BASE + 0xD000)
33#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
34	defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124) || \
35	defined(CONFIG_TEGRA132) || defined(CONFIG_TEGRA210)
36#define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
37#else
38#define NV_PA_PMC_BASE		0xc360000
39#endif
40#define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
41#define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
42#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
43	defined(CONFIG_TEGRA114)
44#define NV_PA_CSITE_BASE	0x70040000
45#else
46#define NV_PA_CSITE_BASE	0x70800000
47#endif
48#define TEGRA_USB_ADDR_MASK	0xFFFFC000
49
50#define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
51#define LOW_LEVEL_SRAM_STACK	0x4000FFFC
52#define EARLY_AVP_STACK		(NV_PA_SDRAM_BASE + 0x20000)
53#define EARLY_CPU_STACK		(EARLY_AVP_STACK - 4096)
54#define PG_UP_TAG_AVP		0xAAAAAAAA
55
56#ifndef __ASSEMBLY__
57struct timerus {
58	unsigned int cntr_1us;
59};
60
61/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
62#define NV_WB_RUN_ADDRESS	0x40020000
63
64#define NVBOOTTYPE_RECOVERY	2	/* BR entered RCM */
65#define NVBOOTINFOTABLE_BOOTTYPE 0xC	/* Boot type in BIT in IRAM */
66#define NVBOOTINFOTABLE_BCTSIZE	0x38	/* BCT size in BIT in IRAM */
67#define NVBOOTINFOTABLE_BCTPTR	0x3C	/* BCT pointer in BIT in IRAM */
68
69/* These are the available SKUs (product types) for Tegra */
70enum {
71	SKU_ID_T20_7		= 0x7,
72	SKU_ID_T20		= 0x8,
73	SKU_ID_T25SE		= 0x14,
74	SKU_ID_AP25		= 0x17,
75	SKU_ID_T25		= 0x18,
76	SKU_ID_AP25E		= 0x1b,
77	SKU_ID_T25E		= 0x1c,
78	SKU_ID_T33		= 0x80,
79	SKU_ID_T30		= 0x81, /* Cardhu value */
80	SKU_ID_TM30MQS_P_A3	= 0xb1,
81	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
82	SKU_ID_T114_1		= 0x01,
83	SKU_ID_T124_ENG		= 0x00, /* Venice2 value, unfused */
84	SKU_ID_T210_ENG		= 0x00, /* unfused value TBD */
85};
86
87/*
88 * These are used to distinguish SOC types for setting up clocks. Mostly
89 * we can tell the clocking required by looking at the SOC sku_id, but
90 * for T30 it is a user option as to whether to run PLLP in fast or slow
91 * mode, so we have two options there.
92 */
93enum {
94	TEGRA_SOC_T20,
95	TEGRA_SOC_T25,
96	TEGRA_SOC_T30,
97	TEGRA_SOC_T114,
98	TEGRA_SOC_T124,
99	TEGRA_SOC_T210,
100
101	TEGRA_SOC_CNT,
102	TEGRA_SOC_UNKNOWN	= -1,
103};
104
105/* Tegra system controller (SYSCON) devices */
106enum {
107	TEGRA_SYSCON_PMC,
108};
109
110#else  /* __ASSEMBLY__ */
111#define PRM_RSTCTRL		NV_PA_PMC_BASE
112#endif
113
114#endif	/* TEGRA_H */
115