1/* SPDX-License-Identifier:     GPL-2.0+ */
2/*
3 * Copyright (C) 2020 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef _ASM_ARCH_SDRAM_RK1126_PHY_H
7#define _ASM_ARCH_SDRAM_RK1126_PHY_H
8
9/* PHY_REG0 */
10#define DIGITAL_DERESET			BIT(3)
11#define ANALOG_DERESET			BIT(2)
12#define DIGITAL_RESET			(0 << 3)
13#define ANALOG_RESET			(0 << 2)
14
15/* PHY_REG1 */
16#define PHY_DDR2			(0)
17#define PHY_LPDDR2			(1)
18#define PHY_DDR3			(2)
19#define PHY_LPDDR3			(3)
20#define PHY_DDR4			(4)
21#define PHY_DDR5			(5)
22#define PHY_BL_4			(0 << 3)
23#define PHY_BL_8_OR_16			BIT(3)
24
25/* PHY_REG2 */
26#define PHY_DTT_EN			BIT(0)
27#define PHY_DTT_DISB			(0 << 0)
28#define PHY_WRITE_LEVELING_EN		BIT(2)
29#define PHY_WRITE_LEVELING_DISB		(0 << 2)
30#define PHY_SELECT_CS0			(2)
31#define PHY_SELECT_CS1			(1)
32#define PHY_SELECT_CS0_1		(0)
33#define PHY_WRITE_LEVELING_SELECTCS(n)	((n) << 6)
34#define PHY_DATA_TRAINING_SELECTCS(n)	((n) << 4)
35
36/* PHY_REGf */
37#define PHY_DQ_WIDTH_MASK		(0xf)
38
39/* PHY_REG51 */
40#define PHY_PBDIV_BIT9_MASK		BIT(0)
41#define PHY_PBDIV_BIT9_SHIFT	(0)
42#define PHY_POSTDIV_EN_MASK		BIT(7)
43#define PHY_POSTDIV_EN_SHIFT	(7)
44
45/* PHY_REG52 */
46#define PHY_PREDIV_MASK			(0x1F)
47#define PHY_PREDIV_SHIFT		(0)
48
49/* PHY_REG53*/
50#define PHY_POSTDIV_MASK		(0x7)
51#define PHY_POSTDIV_SHIFT		(5)
52#define PHY_PD_DISB			BIT(3)
53
54/* PHY_REG90 */
55#define PHY_PLL_LOCK			BIT(2)
56
57struct ca_skew {
58	u32 a0_a3_a3_cke1_a_de_skew;
59	u32 a1_ba1_null_cke0_b_de_skew;
60	u32 a2_a9_a9_a4_a_de_skew;
61	u32 a3_a15_null_a5_b_de_skew;
62	u32 a4_a6_a6_ck_a_de_skew;
63	u32 a5_a12_null_odt0_b_de_skew;
64	u32 a6_ba2_null_a0_a_de_skew;
65	u32 a7_a4_a4_odt0_a_de_skew;
66	u32 a8_a1_a1_cke0_a_de_skew;
67	u32 a9_a5_a5_a5_a_de_skew;
68	u32 a10_a8_a8_clkb_a_de_skew;
69	u32 a11_a7_a7_ca2_a_de_skew;
70	u32 a12_rasn_null_ca1_a_de_skew;
71	u32 a13_a13_null_ca3_a_de_skew;
72	u32 a14_a14_null_csb1_b_de_skew;
73	u32 a15_a10_null_ca0_b_de_skew;
74	u32 a16_a11_null_csb0_b_de_skew;
75	u32 a17_null_null_null_de_skew;
76	u32 ba0_csb1_csb1_csb0_a_de_skew;
77	u32 ba1_wen_null_cke1_b_de_skew;
78	u32 bg0_odt1_odt1_csb1_a_de_skew;
79	u32 bg1_a2_a2_odt1_a_de_skew;
80	u32 cke0_casb_null_ca1_b_de_skew;
81	u32 ck_ck_ck_ck_b_de_skew;
82	u32 ckb_ckb_ckb_ckb_b_de_skew;
83	u32 csb0_odt0_odt0_ca2_b_de_skew;
84	u32 odt0_csb0_csb0_ca4_b_de_skew;
85	u32 resetn_resetn_null_resetn_de_skew;
86	u32 actn_cke_cke_ca3_b_de_skew;
87	u32 null_null_null_null_de_skew;
88	u32 csb1_ba0_null_null_de_skew;
89	u32 odt1_a0_a0_odt1_b_de_skew;
90};
91
92#define PHY_REG(base, n)		((base) + 4 * (n))
93#endif /* _ASM_ARCH_SDRAM_RK1126_PHY_H */
94