1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6#ifndef _ASM_ARCH_SDRAM_PCTL_PX30_H 7#define _ASM_ARCH_SDRAM_PCTL_PX30_H 8#include <asm/arch-rockchip/sdram_common.h> 9 10#ifndef __ASSEMBLY__ 11#include <linux/bitops.h> 12#endif 13 14struct ddr_pctl_regs { 15 u32 pctl[35][2]; 16}; 17 18/* ddr pctl registers define */ 19#define DDR_PCTL2_MSTR 0x0 20#define DDR_PCTL2_STAT 0x4 21#define DDR_PCTL2_MSTR1 0x8 22#define DDR_PCTL2_MRCTRL0 0x10 23#define DDR_PCTL2_MRCTRL1 0x14 24#define DDR_PCTL2_MRSTAT 0x18 25#define DDR_PCTL2_MRCTRL2 0x1c 26#define DDR_PCTL2_DERATEEN 0x20 27#define DDR_PCTL2_DERATEINT 0x24 28#define DDR_PCTL2_MSTR2 0x28 29#define DDR_PCTL2_PWRCTL 0x30 30#define DDR_PCTL2_PWRTMG 0x34 31#define DDR_PCTL2_HWLPCTL 0x38 32#define DDR_PCTL2_RFSHCTL0 0x50 33#define DDR_PCTL2_RFSHCTL1 0x54 34#define DDR_PCTL2_RFSHCTL2 0x58 35#define DDR_PCTL2_RFSHCTL4 0x5c 36#define DDR_PCTL2_RFSHCTL3 0x60 37#define DDR_PCTL2_RFSHTMG 0x64 38#define DDR_PCTL2_RFSHTMG1 0x68 39#define DDR_PCTL2_RFSHCTL5 0x6c 40#define DDR_PCTL2_INIT0 0xd0 41#define DDR_PCTL2_INIT1 0xd4 42#define DDR_PCTL2_INIT2 0xd8 43#define DDR_PCTL2_INIT3 0xdc 44#define DDR_PCTL2_INIT4 0xe0 45#define DDR_PCTL2_INIT5 0xe4 46#define DDR_PCTL2_INIT6 0xe8 47#define DDR_PCTL2_INIT7 0xec 48#define DDR_PCTL2_DIMMCTL 0xf0 49#define DDR_PCTL2_RANKCTL 0xf4 50#define DDR_PCTL2_CHCTL 0xfc 51#define DDR_PCTL2_DRAMTMG0 0x100 52#define DDR_PCTL2_DRAMTMG1 0x104 53#define DDR_PCTL2_DRAMTMG2 0x108 54#define DDR_PCTL2_DRAMTMG3 0x10c 55#define DDR_PCTL2_DRAMTMG4 0x110 56#define DDR_PCTL2_DRAMTMG5 0x114 57#define DDR_PCTL2_DRAMTMG6 0x118 58#define DDR_PCTL2_DRAMTMG7 0x11c 59#define DDR_PCTL2_DRAMTMG8 0x120 60#define DDR_PCTL2_DRAMTMG9 0x124 61#define DDR_PCTL2_DRAMTMG10 0x128 62#define DDR_PCTL2_DRAMTMG11 0x12c 63#define DDR_PCTL2_DRAMTMG12 0x130 64#define DDR_PCTL2_DRAMTMG13 0x134 65#define DDR_PCTL2_DRAMTMG14 0x138 66#define DDR_PCTL2_DRAMTMG15 0x13c 67#define DDR_PCTL2_DRAMTMG16 0x140 68#define DDR_PCTL2_ZQCTL0 0x180 69#define DDR_PCTL2_ZQCTL1 0x184 70#define DDR_PCTL2_ZQCTL2 0x188 71#define DDR_PCTL2_ZQSTAT 0x18c 72#define DDR_PCTL2_DFITMG0 0x190 73#define DDR_PCTL2_DFITMG1 0x194 74#define DDR_PCTL2_DFILPCFG0 0x198 75#define DDR_PCTL2_DFILPCFG1 0x19c 76#define DDR_PCTL2_DFIUPD0 0x1a0 77#define DDR_PCTL2_DFIUPD1 0x1a4 78#define DDR_PCTL2_DFIUPD2 0x1a8 79#define DDR_PCTL2_DFIMISC 0x1b0 80#define DDR_PCTL2_DFITMG2 0x1b4 81#define DDR_PCTL2_DFITMG3 0x1b8 82#define DDR_PCTL2_DFISTAT 0x1bc 83#define DDR_PCTL2_DBICTL 0x1c0 84#define DDR_PCTL2_ADDRMAP0 0x200 85#define DDR_PCTL2_ADDRMAP1 0x204 86#define DDR_PCTL2_ADDRMAP2 0x208 87#define DDR_PCTL2_ADDRMAP3 0x20c 88#define DDR_PCTL2_ADDRMAP4 0x210 89#define DDR_PCTL2_ADDRMAP5 0x214 90#define DDR_PCTL2_ADDRMAP6 0x218 91#define DDR_PCTL2_ADDRMAP7 0x21c 92#define DDR_PCTL2_ADDRMAP8 0x220 93#define DDR_PCTL2_ADDRMAP9 0x224 94#define DDR_PCTL2_ADDRMAP10 0x228 95#define DDR_PCTL2_ADDRMAP11 0x22c 96#define DDR_PCTL2_ODTCFG 0x240 97#define DDR_PCTL2_ODTMAP 0x244 98#define DDR_PCTL2_SCHED 0x250 99#define DDR_PCTL2_SCHED1 0x254 100#define DDR_PCTL2_PERFHPR1 0x25c 101#define DDR_PCTL2_PERFLPR1 0x264 102#define DDR_PCTL2_PERFWR1 0x26c 103#define DDR_PCTL2_DQMAP0 0x280 104#define DDR_PCTL2_DQMAP1 0x284 105#define DDR_PCTL2_DQMAP2 0x288 106#define DDR_PCTL2_DQMAP3 0x28c 107#define DDR_PCTL2_DQMAP4 0x290 108#define DDR_PCTL2_DQMAP5 0x294 109#define DDR_PCTL2_DBG0 0x300 110#define DDR_PCTL2_DBG1 0x304 111#define DDR_PCTL2_DBGCAM 0x308 112#define DDR_PCTL2_DBGCMD 0x30c 113#define DDR_PCTL2_DBGSTAT 0x310 114#define DDR_PCTL2_SWCTL 0x320 115#define DDR_PCTL2_SWSTAT 0x324 116#define DDR_PCTL2_POISONCFG 0x36c 117#define DDR_PCTL2_POISONSTAT 0x370 118#define DDR_PCTL2_ADVECCINDEX 0x374 119#define DDR_PCTL2_ADVECCSTAT 0x378 120#define DDR_PCTL2_PSTAT 0x3fc 121#define DDR_PCTL2_PCCFG 0x400 122#define DDR_PCTL2_PCFGR_n 0x404 123#define DDR_PCTL2_PCFGW_n 0x408 124#define DDR_PCTL2_PCTRL_n 0x490 125 126#define UMCTL2_REGS_FREQ(n) \ 127 ((0x1000 * (n) + (((n) > 0) ? 0x1000 : 0))) 128 129/* PCTL2_MSTR */ 130#define PCTL2_FREQUENCY_MODE_MASK (1) 131#define PCTL2_FREQUENCY_MODE_SHIFT (29) 132#define PCTL2_DLL_OFF_MODE BIT(15) 133/* PCTL2_STAT */ 134#define PCTL2_SELFREF_TYPE_MASK (3 << 4) 135#define PCTL2_SELFREF_TYPE_SR_NOT_AUTO (2 << 4) 136#define PCTL2_OPERATING_MODE_MASK (7) 137#define PCTL2_OPERATING_MODE_INIT (0) 138#define PCTL2_OPERATING_MODE_NORMAL (1) 139#define PCTL2_OPERATING_MODE_PD (2) 140#define PCTL2_OPERATING_MODE_SR (3) 141/* PCTL2_MRCTRL0 */ 142#define PCTL2_MR_WR BIT(31) 143#define PCTL2_MR_ADDR_SHIFT (12) 144#define PCTL2_MR_RANK_SHIFT (4) 145#define PCTL2_MR_TYPE_WR (0) 146#define PCTL2_MR_TYPE_RD (1) 147/* PCTL2_MRCTRL1 */ 148#define PCTL2_MR_ADDRESS_SHIFT (8) 149#define PCTL2_MR_DATA_MASK (0xff) 150/* PCTL2_MRSTAT */ 151#define PCTL2_MR_WR_BUSY BIT(0) 152/* PCTL2_DERATEEN */ 153#define PCTL2_DERATE_ENABLE (1) 154/* PCTL2_PWRCTL */ 155#define PCTL2_SELFREF_SW BIT(5) 156#define PCTL2_POWERDOWN_EN BIT(1) 157#define PCTL2_SELFREF_EN (1) 158/* PCTL2_PWRTMG */ 159#define PCTL2_SELFREF_TO_X32_MASK (0xFF) 160#define PCTL2_SELFREF_TO_X32_SHIFT (16) 161#define PCTL2_POWERDOWN_TO_X32_MASK (0x1F) 162/* PCTL2_INIT3 */ 163#define PCTL2_DDR34_MR0_SHIFT (16) 164#define PCTL2_LPDDR234_MR1_SHIFT (16) 165#define PCTL2_DDR34_MR1_SHIFT (0) 166#define PCTL2_LPDDR234_MR2_SHIFT (0) 167/* PCTL2_INIT4 */ 168#define PCTL2_DDR34_MR2_SHIFT (16) 169#define PCTL2_LPDDR234_MR3_SHIFT (16) 170#define PCTL2_DDR34_MR3_SHIFT (0) 171#define PCTL2_LPDDR4_MR13_SHIFT (0) 172 173/* PCTL2_INIT6 */ 174#define PCTL2_DDR4_MR4_SHIFT (16) 175#define PCTL2_LPDDR4_MR11_SHIFT (16) 176#define PCTL2_DDR4_MR5_SHIFT (0) 177#define PCTL2_LPDDR4_MR12_SHIFT (0) 178 179/* PCTL2_INIT7 */ 180#define PCTL2_LPDDR4_MR22_SHIFT (16) 181#define PCTL2_DDR4_MR6_SHIFT (0) 182#define PCTL2_LPDDR4_MR14_SHIFT (0) 183 184#define PCTL2_MR_MASK (0xffff) 185 186/* PCTL2_RFSHCTL3 */ 187#define PCTL2_DIS_AUTO_REFRESH (1) 188/* PCTL2_ZQCTL0 */ 189#define PCTL2_DIS_AUTO_ZQ BIT(31) 190#define PCTL2_DIS_SRX_ZQCL BIT(30) 191/* PCTL2_DFILPCFG0 */ 192#define PCTL2_DFI_LP_EN_SR BIT(8) 193#define PCTL2_DFI_LP_EN_SR_MASK BIT(8) 194#define PCTL2_DFI_LP_EN_SR_SHIFT (8) 195/* PCTL2_DFIMISC */ 196#define PCTL2_DFI_INIT_COMPLETE_EN (1) 197/* PCTL2_DFISTAT */ 198#define PCTL2_DFI_LP_ACK BIT(1) 199#define PCTL2_DFI_INIT_COMPLETE (1) 200/* PCTL2_DBG1 */ 201#define PCTL2_DIS_HIF BIT(1) 202/* PCTL2_DBGCAM */ 203#define PCTL2_DBG_WR_Q_EMPTY BIT(26) 204#define PCTL2_DBG_RD_Q_EMPTY BIT(25) 205#define PCTL2_DBG_LPR_Q_DEPTH_MASK (0xffff << 8) 206#define PCTL2_DBG_LPR_Q_DEPTH_EMPTY (0x0 << 8) 207/* PCTL2_DBGCMD */ 208#define PCTL2_RANK1_REFRESH BIT(1) 209#define PCTL2_RANK0_REFRESH (1) 210/* PCTL2_DBGSTAT */ 211#define PCTL2_RANK1_REFRESH_BUSY BIT(1) 212#define PCTL2_RANK0_REFRESH_BUSY (1) 213/* PCTL2_SWCTL */ 214#define PCTL2_SW_DONE (1) 215#define PCTL2_SW_DONE_CLEAR (0) 216/* PCTL2_SWSTAT */ 217#define PCTL2_SW_DONE_ACK (1) 218/* PCTL2_PSTAT */ 219#define PCTL2_WR_PORT_BUSY_0 BIT(16) 220#define PCTL2_RD_PORT_BUSY_0 (1) 221/* PCTL2_PCTRLn */ 222#define PCTL2_PORT_EN (1) 223 224void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num); 225int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, 226 u32 dramtype); 227int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate, 228 u32 dramtype); 229 230u32 pctl_dis_zqcs_aref(void __iomem *pctl_base); 231void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq); 232 233u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs, 234 struct sdram_cap_info *cap_info, 235 u32 dram_type); 236int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs, 237 u32 sr_idle, u32 pd_idle); 238 239#endif 240