1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2020 Rockchip Electronics Co., Ltd 4 */ 5 6#ifndef __ROCKCHIP_DRAM_SPEC_TIMING_H__ 7#define __ROCKCHIP_DRAM_SPEC_TIMING_H__ 8 9enum ddr3_speed_rate { 10 /* 5-5-5 */ 11 DDR3_800D = 0, 12 /* 6-6-6 */ 13 DDR3_800E = 1, 14 /* 6-6-6 */ 15 DDR3_1066E = 2, 16 /* 7-7-7 */ 17 DDR3_1066F = 3, 18 /* 8-8-8 */ 19 DDR3_1066G = 4, 20 /* 7-7-7 */ 21 DDR3_1333F = 5, 22 /* 8-8-8 */ 23 DDR3_1333G = 6, 24 /* 9-9-9 */ 25 DDR3_1333H = 7, 26 /* 10-10-10 */ 27 DDR3_1333J = 8, 28 /* 8-8-8 */ 29 DDR3_1600G = 9, 30 /* 9-9-9 */ 31 DDR3_1600H = 10, 32 /* 10-10-10 */ 33 DDR3_1600J = 11, 34 /* 11-11-11 */ 35 DDR3_1600K = 12, 36 /* 10-10-10 */ 37 DDR3_1866J = 13, 38 /* 11-11-11 */ 39 DDR3_1866K = 14, 40 /* 12-12-12 */ 41 DDR3_1866L = 15, 42 /* 13-13-13 */ 43 DDR3_1866M = 16, 44 /* 11-11-11 */ 45 DDR3_2133K = 17, 46 /* 12-12-12 */ 47 DDR3_2133L = 18, 48 /* 13-13-13 */ 49 DDR3_2133M = 19, 50 /* 14-14-14 */ 51 DDR3_2133N = 20, 52 DDR3_DEFAULT = 21, 53}; 54 55enum ddr4_speed_rate { 56 /* DDR4_1600J (10-10-10) */ 57 DDR4_1600J = 0, 58 /* DDR4_1600K (11-11-11) */ 59 DDR4_1600K = 1, 60 /* DDR4_1600L (12-12-12) */ 61 DDR4_1600L = 2, 62 /* DDR4_1800L (12-12-12) */ 63 DDR4_1866L = 3, 64 /* DDR4_1800M (13-13-13) */ 65 DDR4_1866M = 4, 66 /* DDR4_1800N (14-14-14) */ 67 DDR4_1866N = 5, 68 /* DDR4_2133N (14-14-14) */ 69 DDR4_2133N = 6, 70 /* DDR4_2133P (15-15-15) */ 71 DDR4_2133P = 7, 72 /* DDR4_2133R (16-16-16) */ 73 DDR4_2133R = 8, 74 /* DDR4_2400P (15-15-15) */ 75 DDR4_2400P = 9, 76 /* DDR4_2400R (16-16-16) */ 77 DDR4_2400R = 10, 78 /* DDR4_2400U (18-18-18) */ 79 DDR4_2400U = 11, 80 /* DEFAULT */ 81 DDR4_DEFAULT = 12, 82}; 83 84/* mr0 for ddr3 */ 85#define DDR3_BL8 (0) 86#define DDR3_BC4_8 (1) 87#define DDR3_BC4 (2) 88#define DDR3_CL(n) (((((n) - 4) & 0x7) << 4)\ 89 | ((((n) - 4) & 0x8) >> 1)) 90#define DDR3_WR(n) (((n) & 0x7) << 9) 91#define DDR3_DLL_RESET (1 << 8) 92#define DDR3_DLL_DERESET (0 << 8) 93 94/* mr1 for ddr3 */ 95#define DDR3_DLL_ENABLE (0) 96#define DDR3_DLL_DISABLE (1) 97#define DDR3_MR1_AL(n) (((n) & 0x3) << 3) 98 99#define DDR3_DS_40 (0) 100#define DDR3_DS_34 BIT(1) 101#define DDR3_DS_MASK ((1 << 1) | (1 << 5)) 102#define DDR3_RTT_NOM_MASK ((1 << 2) | (1 << 6) | (1 << 9)) 103#define DDR3_RTT_NOM_DIS (0) 104#define DDR3_RTT_NOM_60 BIT(2) 105#define DDR3_RTT_NOM_120 BIT(6) 106#define DDR3_RTT_NOM_40 ((1 << 2) | (1 << 6)) 107#define DDR3_TDQS BIT(11) 108 109/* mr2 for ddr3 */ 110#define DDR3_MR2_CWL(n) ((((n) - 5) & 0x7) << 3) 111#define DDR3_RTT_WR_DIS (0) 112#define DDR3_RTT_WR_60 (1 << 9) 113#define DDR3_RTT_WR_120 (2 << 9) 114 115/* 116 * MR0 (Device Information) 117 * 0:DAI complete, 1:DAI still in progress 118 */ 119#define LPDDR2_DAI (0x1) 120/* 0:S2 or S4 SDRAM, 1:NVM */ 121#define LPDDR2_DI (0x1 << 1) 122/* 0:DNV not supported, 1:DNV supported */ 123#define LPDDR2_DNVI (0x1 << 2) 124#define LPDDR2_RZQI (0x3 << 3) 125 126/* 127 * 00:RZQ self test not supported, 128 * 01:ZQ-pin may connect to VDDCA or float 129 * 10:ZQ-pin may short to GND. 130 * 11:ZQ-pin self test completed, no error condition detected. 131 */ 132 133/* MR1 (Device Feature) */ 134#define LPDDR2_BL4 (0x2) 135#define LPDDR2_BL8 (0x3) 136#define LPDDR2_BL16 (0x4) 137#define LPDDR2_N_WR(n) (((n) - 2) << 5) 138 139/* MR2 (Device Feature 2) */ 140#define LPDDR2_RL3_WL1 (0x1) 141#define LPDDR2_RL4_WL2 (0x2) 142#define LPDDR2_RL5_WL2 (0x3) 143#define LPDDR2_RL6_WL3 (0x4) 144#define LPDDR2_RL7_WL4 (0x5) 145#define LPDDR2_RL8_WL4 (0x6) 146 147/* MR3 (IO Configuration 1) */ 148#define LPDDR2_DS_34 (0x1) 149#define LPDDR2_DS_40 (0x2) 150#define LPDDR2_DS_48 (0x3) 151#define LPDDR2_DS_60 (0x4) 152#define LPDDR2_DS_80 (0x6) 153/* optional */ 154#define LPDDR2_DS_120 (0x7) 155 156/* MR4 (Device Temperature) */ 157#define LPDDR2_TREF_MASK (0x7) 158#define LPDDR2_4_TREF (0x1) 159#define LPDDR2_2_TREF (0x2) 160#define LPDDR2_1_TREF (0x3) 161#define LPDDR2_025_TREF (0x5) 162#define LPDDR2_025_TREF_DERATE (0x6) 163 164#define LPDDR2_TUF (0x1 << 7) 165 166/* MR8 (Basic configuration 4) */ 167#define LPDDR2_S4 (0x0) 168#define LPDDR2_S2 (0x1) 169#define LPDDR2_N (0x2) 170/* Unit:MB */ 171#define LPDDR2_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) 172#define LPDDR2_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) 173 174/* MR10 (Calibration) */ 175#define LPDDR2_ZQINIT (0xff) 176#define LPDDR2_ZQCL (0xab) 177#define LPDDR2_ZQCS (0x56) 178#define LPDDR2_ZQRESET (0xc3) 179 180/* MR16 (PASR Bank Mask), S2 SDRAM Only */ 181#define LPDDR2_PASR_FULL (0x0) 182#define LPDDR2_PASR_1_2 (0x1) 183#define LPDDR2_PASR_1_4 (0x2) 184#define LPDDR2_PASR_1_8 (0x3) 185 186/* 187 * MR0 (Device Information) 188 * 0:DAI complete, 189 * 1:DAI still in progress 190 */ 191#define LPDDR3_DAI (0x1) 192/* 193 * 00:RZQ self test not supported, 194 * 01:ZQ-pin may connect to VDDCA or float 195 * 10:ZQ-pin may short to GND. 196 * 11:ZQ-pin self test completed, no error condition detected. 197 */ 198#define LPDDR3_RZQI (0x3 << 3) 199/* 200 * 0:DRAM does not support WL(Set B), 201 * 1:DRAM support WL(Set B) 202 */ 203#define LPDDR3_WL_SUPOT BIT(6) 204/* 205 * 0:DRAM does not support RL=3,nWR=3,WL=1; 206 * 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166 207 */ 208#define LPDDR3_RL3_SUPOT BIT(7) 209 210/* MR1 (Device Feature) */ 211#define LPDDR3_BL8 (0x3) 212#define LPDDR3_N_WR(n) ((n) << 5) 213 214/* MR2 (Device Feature 2), WL Set A,default */ 215/* <=166MHz,optional*/ 216#define LPDDR3_RL3_WL1 (0x1) 217/* <=400MHz*/ 218#define LPDDR3_RL6_WL3 (0x4) 219/* <=533MHz*/ 220#define LPDDR3_RL8_WL4 (0x6) 221/* <=600MHz*/ 222#define LPDDR3_RL9_WL5 (0x7) 223/* <=667MHz,default*/ 224#define LPDDR3_RL10_WL6 (0x8) 225/* <=733MHz*/ 226#define LPDDR3_RL11_WL6 (0x9) 227/* <=800MHz*/ 228#define LPDDR3_RL12_WL6 (0xa) 229/* <=933MHz*/ 230#define LPDDR3_RL14_WL8 (0xc) 231/* <=1066MHz*/ 232#define LPDDR3_RL16_WL8 (0xe) 233 234/* WL Set B, optional */ 235/* <=667MHz,default*/ 236#define LPDDR3_RL10_WL8 (0x8) 237/* <=733MHz*/ 238#define LPDDR3_RL11_WL9 (0x9) 239/* <=800MHz*/ 240#define LPDDR3_RL12_WL9 (0xa) 241/* <=933MHz*/ 242#define LPDDR3_RL14_WL11 (0xc) 243/* <=1066MHz*/ 244#define LPDDR3_RL16_WL13 (0xe) 245 246/* 1:enable nWR programming > 9(default)*/ 247#define LPDDR3_N_WRE BIT(4) 248/* 1:Select WL Set B*/ 249#define LPDDR3_WL_S BIT(6) 250/* 1:enable*/ 251#define LPDDR3_WR_LEVEL BIT(7) 252 253/* MR3 (IO Configuration 1) */ 254#define LPDDR3_DS_34 (0x1) 255#define LPDDR3_DS_40 (0x2) 256#define LPDDR3_DS_48 (0x3) 257#define LPDDR3_DS_60 (0x4) 258#define LPDDR3_DS_80 (0x6) 259#define LPDDR3_DS_34D_40U (0x9) 260#define LPDDR3_DS_40D_48U (0xa) 261#define LPDDR3_DS_34D_48U (0xb) 262 263/* MR4 (Device Temperature) */ 264#define LPDDR3_TREF_MASK (0x7) 265/* SDRAM Low temperature operating limit exceeded */ 266#define LPDDR3_LT_EXED (0x0) 267#define LPDDR3_4_TREF (0x1) 268#define LPDDR3_2_TREF (0x2) 269#define LPDDR3_1_TREF (0x3) 270#define LPDDR3_05_TREF (0x4) 271#define LPDDR3_025_TREF (0x5) 272#define LPDDR3_025_TREF_DERATE (0x6) 273/* SDRAM High temperature operating limit exceeded */ 274#define LPDDR3_HT_EXED (0x7) 275 276/* 1:value has changed since last read of MR4 */ 277#define LPDDR3_TUF (0x1 << 7) 278 279/* MR8 (Basic configuration 4) */ 280#define LPDDR3_S8 (0x3) 281#define LPDDR3_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) 282#define LPDDR3_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) 283 284/* MR10 (Calibration) */ 285#define LPDDR3_ZQINIT (0xff) 286#define LPDDR3_ZQCL (0xab) 287#define LPDDR3_ZQCS (0x56) 288#define LPDDR3_ZQRESET (0xc3) 289 290/* MR11 (ODT Control) */ 291#define LPDDR3_ODT_60 (1) 292#define LPDDR3_ODT_120 (2) 293#define LPDDR3_ODT_240 (3) 294#define LPDDR3_ODT_DIS (0) 295 296/* MR2 (Device Feature 2) */ 297/* RL & nRTP for DBI-RD Disabled */ 298#define LPDDR4_RL6_NRTP8 (0x0) 299#define LPDDR4_RL10_NRTP8 (0x1) 300#define LPDDR4_RL14_NRTP8 (0x2) 301#define LPDDR4_RL20_NRTP8 (0x3) 302#define LPDDR4_RL24_NRTP10 (0x4) 303#define LPDDR4_RL28_NRTP12 (0x5) 304#define LPDDR4_RL32_NRTP14 (0x6) 305#define LPDDR4_RL36_NRTP16 (0x7) 306/* RL & nRTP for DBI-RD Disabled */ 307#define LPDDR4_RL12_NRTP8 (0x1) 308#define LPDDR4_RL16_NRTP8 (0x2) 309#define LPDDR4_RL22_NRTP8 (0x3) 310#define LPDDR4_RL28_NRTP10 (0x4) 311#define LPDDR4_RL32_NRTP12 (0x5) 312#define LPDDR4_RL36_NRTP14 (0x6) 313#define LPDDR4_RL40_NRTP16 (0x7) 314/* WL Set A,default */ 315#define LPDDR4_A_WL4 (0x0 << 3) 316#define LPDDR4_A_WL6 (0x1 << 3) 317#define LPDDR4_A_WL8 (0x2 << 3) 318#define LPDDR4_A_WL10 (0x3 << 3) 319#define LPDDR4_A_WL12 (0x4 << 3) 320#define LPDDR4_A_WL14 (0x5 << 3) 321#define LPDDR4_A_WL16 (0x6 << 3) 322#define LPDDR4_A_WL18 (0x7 << 3) 323/* WL Set B, optional */ 324#define LPDDR4_B_WL4 (0x0 << 3) 325#define LPDDR4_B_WL8 (0x1 << 3) 326#define LPDDR4_B_WL12 (0x2 << 3) 327#define LPDDR4_B_WL18 (0x3 << 3) 328#define LPDDR4_B_WL22 (0x4 << 3) 329#define LPDDR4_B_WL26 (0x5 << 3) 330#define LPDDR4_B_WL30 (0x6 << 3) 331#define LPDDR4_B_WL34 (0x7 << 3) 332/* 1:Select WL Set B*/ 333#define LPDDR4_WL_B BIT(6) 334/* 1:enable*/ 335#define LPDDR4_WR_LEVEL BIT(7) 336 337/* MR3 */ 338#define LPDDR4_VDDQ_2_5 (0) 339#define LPDDR4_VDDQ_3 (1) 340#define LPDDR4_PU_CAL_MASK (1) 341#define LPDDR4_WRPST_0_5_TCK (0 << 1) 342#define LPDDR4_WRPST_1_5_TCK (1 << 1) 343#define LPDDR4_PPR_EN (1 << 2) 344/* PDDS */ 345#define LPDDR4_PDDS_MASK (0x7 << 3) 346#define LPDDR4_PDDS_SHIFT (3) 347#define LPDDR4_PDDS_240 (0x1 << 3) 348#define LPDDR4_PDDS_120 (0x2 << 3) 349#define LPDDR4_PDDS_80 (0x3 << 3) 350#define LPDDR4_PDDS_60 (0x4 << 3) 351#define LPDDR4_PDDS_48 (0x5 << 3) 352#define LPDDR4_PDDS_40 (0x6 << 3) 353#define LPDDR4_DBI_RD_EN BIT(6) 354#define LPDDR4_DBI_WR_EN BIT(7) 355 356/* MR11 (ODT Control) */ 357#define LPDDR4_DQODT_MASK (0x7) 358#define LPDDR4_DQODT_SHIFT (0x0) 359#define LPDDR4_DQODT_240 (1) 360#define LPDDR4_DQODT_120 (2) 361#define LPDDR4_DQODT_80 (3) 362#define LPDDR4_DQODT_60 (4) 363#define LPDDR4_DQODT_48 (5) 364#define LPDDR4_DQODT_40 (6) 365#define LPDDR4_DQODT_DIS (0) 366#define LPDDR4_CAODT_MASK (0x7 << 4) 367#define LPDDR4_CAODT_SHIFT (4) 368#define LPDDR4_CAODT_240 (1 << 4) 369#define LPDDR4_CAODT_120 (2 << 4) 370#define LPDDR4_CAODT_80 (3 << 4) 371#define LPDDR4_CAODT_60 (4 << 4) 372#define LPDDR4_CAODT_48 (5 << 4) 373#define LPDDR4_CAODT_40 (6 << 4) 374#define LPDDR4_CAODT_DIS (0 << 4) 375 376/* MR22 */ 377#define LPDDR4_ODTE_CK_SHIFT (3) 378#define LPDDR4_ODTE_CS_SHIFT (4) 379#define LPDDR4_ODTD_CA_SHIFT (5) 380#define LPDDR4_SOC_ODT_MASK (0x7) 381#define LPDDR4_SOC_ODT_SHIFT (0) 382#define LPDDR4_SOC_ODT_240 (1) 383#define LPDDR4_SOC_ODT_120 (2) 384#define LPDDR4_SOC_ODT_80 (3) 385#define LPDDR4_SOC_ODT_60 (4) 386#define LPDDR4_SOC_ODT_48 (5) 387#define LPDDR4_SOC_ODT_40 (6) 388#define LPDDR4_SOC_ODT_DIS (0) 389 390/* LPDDR4x */ 391/* MR3 */ 392#define LPDDR4X_VDDQ_0_6 (0) 393#define LPDDR4X_VDDQ_0_5 (1) 394 395/* mr0 for ddr4 */ 396#define DDR4_BL8 (0) 397#define DDR4_BC4_8 (1) 398#define DDR4_BC4 (2) 399#define DDR4_WR_RTP(n) ((n) << 9) 400#define DDR4_CL(n) ((((n) & 0xe) << 3) | ((n) & 1) << 2) 401#define DDR4_DLL_RESET(n) ((n) << 8) 402#define DDR4_DLL_ON BIT(0) 403#define DDR4_DLL_OFF (0 << 0) 404 405/* mr1 for ddr4 */ 406#define DDR4_AL ((n) << 3) 407#define DDR4_DS_34 (0) 408#define DDR4_DS_48 BIT(1) 409#define DDR4_DS_MASK (0x3 << 1) 410#define DDR4_RTT_NOM_MASK (0x7 << 8) 411#define DDR4_RTT_NOM_DIS (0) 412#define DDR4_RTT_NOM_60 BIT(8) 413#define DDR4_RTT_NOM_120 (2 << 8) 414#define DDR4_RTT_NOM_40 (0x3 << 8) 415#define DDR4_RTT_NOM_240 (0x4 << 8) 416#define DDR4_RTT_NOM_48 (0x5 << 8) 417#define DDR4_RTT_NOM_80 (0x6 << 8) 418#define DDR4_RTT_NOM_34 (0x7 << 8) 419 420/* mr2 for ddr4 */ 421#define DDR4_MR2_CWL(n) ((n) << 3) 422#define DDR4_RTT_WR_DIS (0) 423#define DDR4_RTT_WR_120 BIT(9) 424#define DDR4_RTT_WR_240 (2 << 9) 425 426/* mr4 for ddr4 */ 427#define DDR4_READ_PREAMBLE(n) ((n) << 11) 428#define DDR4_WRITE_PREAMBLE(n) ((n) << 12) 429#define DDR4_READ_PREAMBLE_TRAIN(n) ((n) << 10) 430 431/* mr5 for ddr4 */ 432#define DDR4_RD_DBI(n) ((n) << 12) 433#define DDR4_WR_DBI(n) ((n) << 11) 434#define DDR4_DM(n) ((n) << 10) 435#define DDR4_RTT_PARK_DIS (0 << 6) 436#define DDR4_RTT_PARK_60 (1 << 6) 437#define DDR4_RTT_PARK_120 (2 << 6) 438#define DDR4_RTT_PARK_40 (3 << 6) 439#define DDR4_RTT_PARK_240 (4 << 6) 440#define DDR4_RTT_PARK_48 (5 << 6) 441#define DDR4_RTT_PARK_80 (6 << 6) 442#define DDR4_RTT_PARK_34 (7 << 6) 443#define DIS_ODT_PD (1 << 5) 444#define EN_ODT_PD (0 << 5) 445 446/* mr6 for ddr4 */ 447#define DDR4_TCCD_L(n) (((n) - 4) << 10) 448 449#define PS_2_CLK(freq, ps) (((uint64_t)(ps) / 100 * (uint64_t)(freq) +\ 450 9999) / 10000) 451 452#endif /* __ROCKCHIP_DRAM_SPEC_TIMING_H__ */ 453