1/* SPDX-License-Identifier: GPL-2.0+ */
2
3#ifndef __ASM_ARCH_BOOT0_H__
4#define __ASM_ARCH_BOOT0_H__
5
6#include <asm/arch-rockchip/boot_mode.h>
7
8/*
9 * Execution starts on the instruction following this 4-byte header
10 * (containing the magic 'RK30'). This magic constant will be written into
11 * the final image by the rkimage tool, but we need to reserve space for it here.
12 */
13#ifdef CONFIG_SPL_BUILD
14	b	1f  /* if overwritten, entry-address is at the next word */
151:
16#endif
17
18#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
19/*
20 * Keep track of the re-entries with help of the lr register.
21 * This binary can be re-used and called from various BROM functions.
22 * Only when it's called from the part that handles SPI, NAND or EMMC
23 * hardware it needs to early return to BROM ones.
24 * In download mode when it handles data on USB OTG and UART0
25 * this section must be skipped.
26 */
27	ldr	r3, =CONFIG_ROCKCHIP_BOOT_LR_REG
28	cmp	lr, r3          /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG)        */
29	bne	reset           /*     goto reset;                               */
30/*
31 * Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
32 * support to enter download mode on return to BROM. This binary must check
33 * the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
34 * It then returns to BROM to the end of the function that reads boot blocks.
35 * From there the BROM code goes into a download mode and waits for data
36 * on USB OTG and UART0.
37 */
38	ldr	r2, =BOOT_BROM_DOWNLOAD
39	ldr	r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG
40	ldr	r0, [r3]        /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) !=   */
41	cmp	r0, r2          /*     BOOT_BROM_DOWNLOAD) {                     */
42	bne	early_return    /*     goto early_return;                        */
43				/* } else {                                      */
44	mov	r0, #0
45	str	r0, [r3]        /*     writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); */
46
47	ldr	r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG
48	bx	r3              /*     return to CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/
49				/* }                                             */
50early_return:
51	bx	lr              /* return to LR in BROM                          */
52
53SAVE_SP_ADDR:
54	.word 0
55
56	.globl save_boot_params
57save_boot_params:
58	push	{r1-r12, lr}
59	ldr	r0, =SAVE_SP_ADDR
60	str	sp, [r0]
61	b	save_boot_params_ret
62
63	.globl back_to_bootrom
64back_to_bootrom:
65	ldr	r0, =SAVE_SP_ADDR
66	ldr	sp, [r0]
67	mov	r0, #0
68	pop	{r1-r12, pc}
69#endif
70
71#if (defined(CONFIG_SPL_BUILD))
72/* U-Boot proper of armv7 does not need this */
73	b reset
74#endif
75
76/*
77 * For armv7, the addr '_start' will be used as vector start address
78 * and is written to the VBAR register, which needs to aligned to 0x20.
79 */
80	.align(5), 0x0
81_start:
82	ARM_VECTORS
83#endif
84