1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2015 4 * Texas Instruments Incorporated 5 * 6 * Lokesh Vutla <lokeshvutla@ti.com> 7 */ 8 9#ifndef _DRA7_IODELAY_H_ 10#define _DRA7_IODELAY_H_ 11 12#include <asm/arch/sys_proto.h> 13 14/* CFG REG_0 */ 15#define CFG_REG_0_OFFSET 0xC 16#define CFG_REG_ROM_READ_SHIFT 1 17#define CFG_REG_ROM_READ_MASK (1 << 1) 18#define CFG_REG_CALIB_STRT_SHIFT 0 19#define CFG_REG_CALIB_STRT_MASK (1 << 0) 20#define CFG_REG_CALIB_STRT 1 21#define CFG_REG_CALIB_END 0 22#define CFG_REG_ROM_READ_START (1 << 1) 23#define CFG_REG_ROM_READ_END (0 << 1) 24 25/* CFG REG_2 */ 26#define CFG_REG_2_OFFSET 0x14 27#define CFG_REG_REFCLK_PERIOD_SHIFT 0 28#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0) 29#define CFG_REG_REFCLK_PERIOD 0x2EF 30 31/* CFG REG_8 */ 32#define CFG_REG_8_OFFSET 0x2C 33#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA 34#define CFG_IODELAY_LOCK_KEY 0x0000AAAB 35 36/* CFG REG_3/4 */ 37#define CFG_REG_3_OFFSET 0x18 38#define CFG_REG_4_OFFSET 0x1C 39#define CFG_REG_DLY_CNT_SHIFT 16 40#define CFG_REG_DLY_CNT_MASK (0xFFFF << 16) 41#define CFG_REG_REF_CNT_SHIFT 0 42#define CFG_REG_REF_CNT_MASK (0xFFFF << 0) 43 44/* CTRL_CORE_SMA_SW_0 */ 45#define CTRL_ISOLATE_SHIFT 2 46#define CTRL_ISOLATE_MASK (1 << 2) 47#define ISOLATE_IO 1 48#define DEISOLATE_IO 0 49 50/* CTRL_CORE_SMA_SW_1 */ 51#define RGMII2_ID_MODE_N_MASK (1 << 26) 52#define RGMII1_ID_MODE_N_MASK (1 << 25) 53 54/* PRM_IO_PMCTRL */ 55#define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0 56#define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0) 57#define PMCTRL_ISOCLK_STATUS_SHIFT 1 58#define PMCTRL_ISOCLK_STATUS_MASK (1 << 1) 59#define PMCTRL_ISOCLK_OVERRIDE_CTRL 1 60#define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL 0 61 62#define ERR_CALIBRATE_IODELAY 0x1 63#define ERR_DEISOLATE_IO 0x2 64#define ERR_ISOLATE_IO 0x4 65#define ERR_UPDATE_DELAY 0x8 66#define ERR_CPDE 0x3 67#define ERR_FPDE 0x5 68 69/* CFG_XXX */ 70#define CFG_X_SIGNATURE_SHIFT 12 71#define CFG_X_SIGNATURE_MASK (0x3F << 12) 72#define CFG_X_LOCK_SHIFT 10 73#define CFG_X_LOCK_MASK (0x1 << 10) 74#define CFG_X_COARSE_DLY_SHIFT 5 75#define CFG_X_COARSE_DLY_MASK (0x1F << 5) 76#define CFG_X_FINE_DLY_SHIFT 0 77#define CFG_X_FINE_DLY_MASK (0x1F << 0) 78#define CFG_X_SIGNATURE 0x29 79#define CFG_X_LOCK 1 80 81void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, 82 struct iodelay_cfg_entry const *iodelay, 83 int niodelays); 84void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, 85 struct iodelay_cfg_entry const *iodelay, 86 int niodelays); 87int __recalibrate_iodelay_start(void); 88void __recalibrate_iodelay_end(int ret); 89 90int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, 91 int niodelays); 92#endif 93