1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * https://spdx.org/licenses 6 */ 7#ifndef __CSRS_NIX_H__ 8#define __CSRS_NIX_H__ 9 10/** 11 * @file 12 * 13 * Configuration and status register (CSR) address and type definitions for 14 * NIX. 15 * 16 * This file is auto generated. Do not edit. 17 * 18 */ 19 20/** 21 * Enumeration nix_af_int_vec_e 22 * 23 * NIX Admin Function Interrupt Vector Enumeration Enumerates the NIX AF 24 * MSI-X interrupt vectors. 25 */ 26#define NIX_AF_INT_VEC_E_AF_ERR (3) 27#define NIX_AF_INT_VEC_E_AQ_DONE (2) 28#define NIX_AF_INT_VEC_E_GEN (1) 29#define NIX_AF_INT_VEC_E_POISON (4) 30#define NIX_AF_INT_VEC_E_RVU (0) 31 32/** 33 * Enumeration nix_aq_comp_e 34 * 35 * NIX Completion Enumeration Enumerates the values of 36 * NIX_AQ_RES_S[COMPCODE]. 37 */ 38#define NIX_AQ_COMP_E_CTX_FAULT (4) 39#define NIX_AQ_COMP_E_CTX_POISON (3) 40#define NIX_AQ_COMP_E_GOOD (1) 41#define NIX_AQ_COMP_E_LOCKERR (5) 42#define NIX_AQ_COMP_E_NOTDONE (0) 43#define NIX_AQ_COMP_E_SQB_ALLOC_FAIL (6) 44#define NIX_AQ_COMP_E_SWERR (2) 45 46/** 47 * Enumeration nix_aq_ctype_e 48 * 49 * NIX Context Type Enumeration Enumerates NIX_AQ_INST_S[CTYPE] values. 50 */ 51#define NIX_AQ_CTYPE_E_CQ (2) 52#define NIX_AQ_CTYPE_E_DYNO (5) 53#define NIX_AQ_CTYPE_E_MCE (3) 54#define NIX_AQ_CTYPE_E_RQ (0) 55#define NIX_AQ_CTYPE_E_RSS (4) 56#define NIX_AQ_CTYPE_E_SQ (1) 57 58/** 59 * Enumeration nix_aq_instop_e 60 * 61 * NIX Admin Queue Opcode Enumeration Enumerates NIX_AQ_INST_S[OP] 62 * values. 63 */ 64#define NIX_AQ_INSTOP_E_INIT (1) 65#define NIX_AQ_INSTOP_E_LOCK (4) 66#define NIX_AQ_INSTOP_E_NOP (0) 67#define NIX_AQ_INSTOP_E_READ (3) 68#define NIX_AQ_INSTOP_E_UNLOCK (5) 69#define NIX_AQ_INSTOP_E_WRITE (2) 70 71/** 72 * Enumeration nix_chan_e 73 * 74 * NIX Channel Number Enumeration Enumerates the receive and transmit 75 * channels, and values of NIX_RX_PARSE_S[CHAN], 76 * NIX_SQ_CTX_S[DEFAULT_CHAN]. CNXXXX implements a subset of these 77 * channels. Specifically, only channels for links enumerated by 78 * NIX_LINK_E are implemented. Internal: P2X/X2P channel enumeration for 79 * t9x. 80 */ 81#define NIX_CHAN_E_CGXX_LMACX_CHX(a, b, c) \ 82 (0x800 + 0x100 * (a) + 0x10 * (b) + (c)) 83#define NIX_CHAN_E_LBKX_CHX(a, b) (0 + 0x100 * (a) + (b)) 84#define NIX_CHAN_E_RX(a) (0 + 0x100 * (a)) 85#define NIX_CHAN_E_SDP_CHX(a) (0x700 + (a)) 86 87/** 88 * Enumeration nix_colorresult_e 89 * 90 * NIX Color Result Enumeration Enumerates the values of 91 * NIX_MEM_RESULT_S[COLOR], NIX_AF_TL1()_MD_DEBUG1[COLOR] and 92 * NIX_AF_TL1()_MD_DEBUG1[COLOR]. 93 */ 94#define NIX_COLORRESULT_E_GREEN (0) 95#define NIX_COLORRESULT_E_RED_DROP (3) 96#define NIX_COLORRESULT_E_RED_SEND (2) 97#define NIX_COLORRESULT_E_YELLOW (1) 98 99/** 100 * Enumeration nix_cqerrint_e 101 * 102 * NIX Completion Queue Interrupt Enumeration Enumerates the bit index of 103 * NIX_CQ_CTX_S[CQ_ERR_INT,CQ_ERR_INT_ENA]. 104 */ 105#define NIX_CQERRINT_E_CQE_FAULT (2) 106#define NIX_CQERRINT_E_DOOR_ERR (0) 107#define NIX_CQERRINT_E_WR_FULL (1) 108 109/** 110 * Enumeration nix_intf_e 111 * 112 * NIX Interface Number Enumeration Enumerates the bit index of 113 * NIX_AF_STATUS[CALIBRATE_STATUS]. 114 */ 115#define NIX_INTF_E_CGXX(a) (0 + (a)) 116#define NIX_INTF_E_LBKX(a) (3 + (a)) 117#define NIX_INTF_E_SDP (4) 118 119/** 120 * Enumeration nix_lf_int_vec_e 121 * 122 * NIX Local Function Interrupt Vector Enumeration Enumerates the NIX 123 * MSI-X interrupt vectors per LF. 124 */ 125#define NIX_LF_INT_VEC_E_CINTX(a) (0x40 + (a)) 126#define NIX_LF_INT_VEC_E_ERR_INT (0x81) 127#define NIX_LF_INT_VEC_E_GINT (0x80) 128#define NIX_LF_INT_VEC_E_POISON (0x82) 129#define NIX_LF_INT_VEC_E_QINTX(a) (0 + (a)) 130 131/** 132 * Enumeration nix_link_e 133 * 134 * NIX Link Number Enumeration Enumerates the receive and transmit links, 135 * and LINK index of NIX_AF_RX_LINK()_CFG, NIX_AF_RX_LINK()_WRR_CFG, 136 * NIX_AF_TX_LINK()_NORM_CREDIT, NIX_AF_TX_LINK()_HW_XOFF and 137 * NIX_AF_TL3_TL2()_LINK()_CFG. 138 */ 139#define NIX_LINK_E_CGXX_LMACX(a, b) (0 + 4 * (a) + (b)) 140#define NIX_LINK_E_LBKX(a) (0xc + (a)) 141#define NIX_LINK_E_MC (0xe) 142#define NIX_LINK_E_SDP (0xd) 143 144/** 145 * Enumeration nix_lsoalg_e 146 * 147 * NIX Large Send Offload Algorithm Enumeration Enumerates 148 * NIX_AF_LSO_FORMAT()_FIELD()[ALG] values. Specifies algorithm for 149 * modifying the associated LSO packet field. 150 */ 151#define NIX_LSOALG_E_ADD_OFFSET (3) 152#define NIX_LSOALG_E_ADD_PAYLEN (2) 153#define NIX_LSOALG_E_ADD_SEGNUM (1) 154#define NIX_LSOALG_E_NOP (0) 155#define NIX_LSOALG_E_TCP_FLAGS (4) 156 157/** 158 * Enumeration nix_maxsqesz_e 159 * 160 * NIX Maximum SQE Size Enumeration Enumerates the values of 161 * NIX_SQ_CTX_S[MAX_SQE_SIZE]. 162 */ 163#define NIX_MAXSQESZ_E_W16 (0) 164#define NIX_MAXSQESZ_E_W8 (1) 165 166/** 167 * Enumeration nix_mdtype_e 168 * 169 * NIX Meta Descriptor Type Enumeration Enumerates values of 170 * NIX_AF_MDQ()_MD_DEBUG[MD_TYPE]. 171 */ 172#define NIX_MDTYPE_E_FLUSH (1) 173#define NIX_MDTYPE_E_PMD (2) 174#define NIX_MDTYPE_E_RSVD (0) 175 176/** 177 * Enumeration nix_mnqerr_e 178 * 179 * NIX Meta-Descriptor Enqueue Error Enumeration Enumerates 180 * NIX_LF_MNQ_ERR_DBG[ERRCODE] values. 181 */ 182#define NIX_MNQERR_E_CQ_QUERY_ERR (6) 183#define NIX_MNQERR_E_LSO_ERR (5) 184#define NIX_MNQERR_E_MAXLEN_ERR (8) 185#define NIX_MNQERR_E_MAX_SQE_SIZE_ERR (7) 186#define NIX_MNQERR_E_SQB_FAULT (2) 187#define NIX_MNQERR_E_SQB_POISON (3) 188#define NIX_MNQERR_E_SQE_SIZEM1_ZERO (9) 189#define NIX_MNQERR_E_SQ_CTX_FAULT (0) 190#define NIX_MNQERR_E_SQ_CTX_POISON (1) 191#define NIX_MNQERR_E_TOTAL_ERR (4) 192 193/** 194 * Enumeration nix_ndc_rx_port_e 195 * 196 * NIX Receive NDC Port Enumeration Enumerates NIX receive NDC 197 * (NDC_IDX_E::NIX()_RX) ports and the PORT index of 198 * NDC_AF_PORT()_RT()_RW()_REQ_PC and NDC_AF_PORT()_RT()_RW()_LAT_PC. 199 */ 200#define NIX_NDC_RX_PORT_E_AQ (0) 201#define NIX_NDC_RX_PORT_E_CINT (2) 202#define NIX_NDC_RX_PORT_E_CQ (1) 203#define NIX_NDC_RX_PORT_E_MC (3) 204#define NIX_NDC_RX_PORT_E_PKT (4) 205#define NIX_NDC_RX_PORT_E_RQ (5) 206 207/** 208 * Enumeration nix_ndc_tx_port_e 209 * 210 * NIX Transmit NDC Port Enumeration Enumerates NIX transmit NDC 211 * (NDC_IDX_E::NIX()_TX) ports and the PORT index of 212 * NDC_AF_PORT()_RT()_RW()_REQ_PC and NDC_AF_PORT()_RT()_RW()_LAT_PC. 213 */ 214#define NIX_NDC_TX_PORT_E_DEQ (3) 215#define NIX_NDC_TX_PORT_E_DMA (4) 216#define NIX_NDC_TX_PORT_E_ENQ (1) 217#define NIX_NDC_TX_PORT_E_LMT (0) 218#define NIX_NDC_TX_PORT_E_MNQ (2) 219#define NIX_NDC_TX_PORT_E_XQE (5) 220 221/** 222 * Enumeration nix_re_opcode_e 223 * 224 * NIX Receive Error Opcode Enumeration Enumerates 225 * NIX_RX_PARSE_S[ERRCODE] values when NIX_RX_PARSE_S[ERRLEV] = 226 * NPC_ERRLEV_E::RE. 227 */ 228#define NIX_RE_OPCODE_E_OL2_LENMISM (0x12) 229#define NIX_RE_OPCODE_E_OVERSIZE (0x11) 230#define NIX_RE_OPCODE_E_RE_DMAPKT (0xf) 231#define NIX_RE_OPCODE_E_RE_FCS (7) 232#define NIX_RE_OPCODE_E_RE_FCS_RCV (8) 233#define NIX_RE_OPCODE_E_RE_JABBER (2) 234#define NIX_RE_OPCODE_E_RE_NONE (0) 235#define NIX_RE_OPCODE_E_RE_PARTIAL (1) 236#define NIX_RE_OPCODE_E_RE_RX_CTL (0xb) 237#define NIX_RE_OPCODE_E_RE_SKIP (0xc) 238#define NIX_RE_OPCODE_E_RE_TERMINATE (9) 239#define NIX_RE_OPCODE_E_UNDERSIZE (0x10) 240 241/** 242 * Enumeration nix_redalg_e 243 * 244 * NIX Red Algorithm Enumeration Enumerates the different algorithms of 245 * NIX_SEND_EXT_S[SHP_RA]. 246 */ 247#define NIX_REDALG_E_DISCARD (3) 248#define NIX_REDALG_E_SEND (1) 249#define NIX_REDALG_E_STALL (2) 250#define NIX_REDALG_E_STD (0) 251 252/** 253 * Enumeration nix_rqint_e 254 * 255 * NIX Receive Queue Interrupt Enumeration Enumerates the bit index of 256 * NIX_RQ_CTX_S[RQ_INT,RQ_INT_ENA]. 257 */ 258#define NIX_RQINT_E_DROP (0) 259#define NIX_RQINT_E_RX(a) (0 + (a)) 260#define NIX_RQINT_E_RED (1) 261 262/** 263 * Enumeration nix_rx_actionop_e 264 * 265 * NIX Receive Action Opcode Enumeration Enumerates the values of 266 * NIX_RX_ACTION_S[OP]. 267 */ 268#define NIX_RX_ACTIONOP_E_DROP (0) 269#define NIX_RX_ACTIONOP_E_MCAST (3) 270#define NIX_RX_ACTIONOP_E_MIRROR (6) 271#define NIX_RX_ACTIONOP_E_PF_FUNC_DROP (5) 272#define NIX_RX_ACTIONOP_E_RSS (4) 273#define NIX_RX_ACTIONOP_E_UCAST (1) 274#define NIX_RX_ACTIONOP_E_UCAST_IPSEC (2) 275 276/** 277 * Enumeration nix_rx_mcop_e 278 * 279 * NIX Receive Multicast/Mirror Opcode Enumeration Enumerates the values 280 * of NIX_RX_MCE_S[OP]. 281 */ 282#define NIX_RX_MCOP_E_RQ (0) 283#define NIX_RX_MCOP_E_RSS (1) 284 285/** 286 * Enumeration nix_rx_perrcode_e 287 * 288 * NIX Receive Protocol Error Code Enumeration Enumerates 289 * NIX_RX_PARSE_S[ERRCODE] values when NIX_RX_PARSE_S[ERRLEV] = 290 * NPC_ERRLEV_E::NIX. 291 */ 292#define NIX_RX_PERRCODE_E_BUFS_OFLOW (0xa) 293#define NIX_RX_PERRCODE_E_DATA_FAULT (8) 294#define NIX_RX_PERRCODE_E_IL3_LEN (0x20) 295#define NIX_RX_PERRCODE_E_IL4_CHK (0x22) 296#define NIX_RX_PERRCODE_E_IL4_LEN (0x21) 297#define NIX_RX_PERRCODE_E_IL4_PORT (0x23) 298#define NIX_RX_PERRCODE_E_MCAST_FAULT (4) 299#define NIX_RX_PERRCODE_E_MCAST_POISON (6) 300#define NIX_RX_PERRCODE_E_MEMOUT (9) 301#define NIX_RX_PERRCODE_E_MIRROR_FAULT (5) 302#define NIX_RX_PERRCODE_E_MIRROR_POISON (7) 303#define NIX_RX_PERRCODE_E_NPC_RESULT_ERR (2) 304#define NIX_RX_PERRCODE_E_OL3_LEN (0x10) 305#define NIX_RX_PERRCODE_E_OL4_CHK (0x12) 306#define NIX_RX_PERRCODE_E_OL4_LEN (0x11) 307#define NIX_RX_PERRCODE_E_OL4_PORT (0x13) 308 309/** 310 * Enumeration nix_send_status_e 311 * 312 * NIX Send Completion Status Enumeration Enumerates values of 313 * NIX_SEND_COMP_S[STATUS] and NIX_LF_SEND_ERR_DBG[ERRCODE]. 314 */ 315#define NIX_SEND_STATUS_E_DATA_FAULT (0x16) 316#define NIX_SEND_STATUS_E_DATA_POISON (0x17) 317#define NIX_SEND_STATUS_E_GOOD (0) 318#define NIX_SEND_STATUS_E_INVALID_SUBDC (0x14) 319#define NIX_SEND_STATUS_E_JUMP_FAULT (7) 320#define NIX_SEND_STATUS_E_JUMP_POISON (8) 321#define NIX_SEND_STATUS_E_LOCK_VIOL (0x21) 322#define NIX_SEND_STATUS_E_NPC_DROP_ACTION (0x20) 323#define NIX_SEND_STATUS_E_NPC_MCAST_ABORT (0x24) 324#define NIX_SEND_STATUS_E_NPC_MCAST_CHAN_ERR (0x23) 325#define NIX_SEND_STATUS_E_NPC_UCAST_CHAN_ERR (0x22) 326#define NIX_SEND_STATUS_E_NPC_VTAG_PTR_ERR (0x25) 327#define NIX_SEND_STATUS_E_NPC_VTAG_SIZE_ERR (0x26) 328#define NIX_SEND_STATUS_E_SEND_CRC_ERR (0x10) 329#define NIX_SEND_STATUS_E_SEND_EXT_ERR (6) 330#define NIX_SEND_STATUS_E_SEND_HDR_ERR (5) 331#define NIX_SEND_STATUS_E_SEND_IMM_ERR (0x11) 332#define NIX_SEND_STATUS_E_SEND_MEM_ERR (0x13) 333#define NIX_SEND_STATUS_E_SEND_MEM_FAULT (0x27) 334#define NIX_SEND_STATUS_E_SEND_SG_ERR (0x12) 335#define NIX_SEND_STATUS_E_SQB_FAULT (3) 336#define NIX_SEND_STATUS_E_SQB_POISON (4) 337#define NIX_SEND_STATUS_E_SQ_CTX_FAULT (1) 338#define NIX_SEND_STATUS_E_SQ_CTX_POISON (2) 339#define NIX_SEND_STATUS_E_SUBDC_ORDER_ERR (0x15) 340 341/** 342 * Enumeration nix_sendcrcalg_e 343 * 344 * NIX Send CRC Algorithm Enumeration Enumerates the CRC algorithm used, 345 * see NIX_SEND_CRC_S[ALG]. 346 */ 347#define NIX_SENDCRCALG_E_CRC32 (0) 348#define NIX_SENDCRCALG_E_CRC32C (1) 349#define NIX_SENDCRCALG_E_ONES16 (2) 350 351/** 352 * Enumeration nix_sendl3type_e 353 * 354 * NIX Send Layer 3 Header Type Enumeration Enumerates values of 355 * NIX_SEND_HDR_S[OL3TYPE], NIX_SEND_HDR_S[IL3TYPE]. Internal: Encoding 356 * matches DPDK TX IP types: \<pre\> PKT_TX_IP_CKSUM (1ULL \<\< 54) 357 * PKT_TX_IPV4 (1ULL \<\< 55) PKT_TX_IPV6 (1ULL \<\< 358 * 56) PKT_TX_OUTER_IP_CKSUM(1ULL \<\< 58) PKT_TX_OUTER_IPV4 (1ULL 359 * \<\< 59) PKT_TX_OUTER_IPV6 (1ULL \<\< 60) \</pre\> 360 */ 361#define NIX_SENDL3TYPE_E_IP4 (2) 362#define NIX_SENDL3TYPE_E_IP4_CKSUM (3) 363#define NIX_SENDL3TYPE_E_IP6 (4) 364#define NIX_SENDL3TYPE_E_NONE (0) 365 366/** 367 * Enumeration nix_sendl4type_e 368 * 369 * NIX Send Layer 4 Header Type Enumeration Enumerates values of 370 * NIX_SEND_HDR_S[OL4TYPE], NIX_SEND_HDR_S[IL4TYPE]. Internal: Encoding 371 * matches DPDK TX L4 types. \<pre\> PKT_TX_L4_NO_CKSUM (0ULL \<\< 52) 372 * // Disable L4 cksum of TX pkt. PKT_TX_TCP_CKSUM (1ULL \<\< 52) // 373 * TCP cksum of TX pkt. computed by nic. PKT_TX_SCTP_CKSUM (2ULL \<\< 374 * 52) // SCTP cksum of TX pkt. computed by nic. PKT_TX_UDP_CKSUM 375 * (3ULL \<\< 52) // UDP cksum of TX pkt. computed by nic. \</pre\> 376 */ 377#define NIX_SENDL4TYPE_E_NONE (0) 378#define NIX_SENDL4TYPE_E_SCTP_CKSUM (2) 379#define NIX_SENDL4TYPE_E_TCP_CKSUM (1) 380#define NIX_SENDL4TYPE_E_UDP_CKSUM (3) 381 382/** 383 * Enumeration nix_sendldtype_e 384 * 385 * NIX Send Load Type Enumeration Enumerates the load transaction types 386 * for reading segment bytes specified by NIX_SEND_SG_S[LD_TYPE] and 387 * NIX_SEND_JUMP_S[LD_TYPE]. Internal: The hardware implementation 388 * treats undefined encodings as LDD load type. 389 */ 390#define NIX_SENDLDTYPE_E_LDD (0) 391#define NIX_SENDLDTYPE_E_LDT (1) 392#define NIX_SENDLDTYPE_E_LDWB (2) 393 394/** 395 * Enumeration nix_sendmemalg_e 396 * 397 * NIX Memory Modify Algorithm Enumeration Enumerates the different 398 * algorithms for modifying memory; see NIX_SEND_MEM_S[ALG]. mbufs_freed 399 * is the number of gather buffers freed to NPA for the send descriptor. 400 * See NIX_SEND_HDR_S[DF] and NIX_SEND_SG_S[I*]. 401 */ 402#define NIX_SENDMEMALG_E_ADD (8) 403#define NIX_SENDMEMALG_E_ADDLEN (0xa) 404#define NIX_SENDMEMALG_E_ADDMBUF (0xc) 405#define NIX_SENDMEMALG_E_SET (0) 406#define NIX_SENDMEMALG_E_SETRSLT (2) 407#define NIX_SENDMEMALG_E_SETTSTMP (1) 408#define NIX_SENDMEMALG_E_SUB (9) 409#define NIX_SENDMEMALG_E_SUBLEN (0xb) 410#define NIX_SENDMEMALG_E_SUBMBUF (0xd) 411 412/** 413 * Enumeration nix_sendmemdsz_e 414 * 415 * NIX Memory Data Size Enumeration Enumerates the datum size for 416 * modifying memory; see NIX_SEND_MEM_S[DSZ]. 417 */ 418#define NIX_SENDMEMDSZ_E_B16 (2) 419#define NIX_SENDMEMDSZ_E_B32 (1) 420#define NIX_SENDMEMDSZ_E_B64 (0) 421#define NIX_SENDMEMDSZ_E_B8 (3) 422 423/** 424 * Enumeration nix_sqint_e 425 * 426 * NIX Send Queue Interrupt Enumeration Enumerates the bit index of 427 * NIX_SQ_CTX_S[SQ_INT,SQ_INT_ENA]. 428 */ 429#define NIX_SQINT_E_LMT_ERR (0) 430#define NIX_SQINT_E_MNQ_ERR (1) 431#define NIX_SQINT_E_SEND_ERR (2) 432#define NIX_SQINT_E_SQB_ALLOC_FAIL (3) 433 434/** 435 * Enumeration nix_sqoperr_e 436 * 437 * NIX SQ Operation Error Enumeration Enumerates 438 * NIX_LF_SQ_OP_ERR_DBG[ERRCODE] values. 439 */ 440#define NIX_SQOPERR_E_MAX_SQE_SIZE_ERR (4) 441#define NIX_SQOPERR_E_SQB_FAULT (7) 442#define NIX_SQOPERR_E_SQB_NULL (6) 443#define NIX_SQOPERR_E_SQE_OFLOW (5) 444#define NIX_SQOPERR_E_SQE_SIZEM1_ZERO (8) 445#define NIX_SQOPERR_E_SQ_CTX_FAULT (1) 446#define NIX_SQOPERR_E_SQ_CTX_POISON (2) 447#define NIX_SQOPERR_E_SQ_DISABLED (3) 448#define NIX_SQOPERR_E_SQ_OOR (0) 449 450/** 451 * Enumeration nix_stat_lf_rx_e 452 * 453 * NIX Local Function Receive Statistics Enumeration Enumerates the last 454 * index of NIX_AF_LF()_RX_STAT() and NIX_LF_RX_STAT(). 455 */ 456#define NIX_STAT_LF_RX_E_RX_BCAST (2) 457#define NIX_STAT_LF_RX_E_RX_DROP (4) 458#define NIX_STAT_LF_RX_E_RX_DROP_OCTS (5) 459#define NIX_STAT_LF_RX_E_RX_DRP_BCAST (8) 460#define NIX_STAT_LF_RX_E_RX_DRP_L3BCAST (0xa) 461#define NIX_STAT_LF_RX_E_RX_DRP_L3MCAST (0xb) 462#define NIX_STAT_LF_RX_E_RX_DRP_MCAST (9) 463#define NIX_STAT_LF_RX_E_RX_ERR (7) 464#define NIX_STAT_LF_RX_E_RX_FCS (6) 465#define NIX_STAT_LF_RX_E_RX_MCAST (3) 466#define NIX_STAT_LF_RX_E_RX_OCTS (0) 467#define NIX_STAT_LF_RX_E_RX_UCAST (1) 468 469/** 470 * Enumeration nix_stat_lf_tx_e 471 * 472 * NIX Local Function Transmit Statistics Enumeration Enumerates the 473 * index of NIX_AF_LF()_TX_STAT() and NIX_LF_TX_STAT(). These statistics 474 * do not account for packet replication due to NIX_TX_ACTION_S[OP] = 475 * NIX_TX_ACTIONOP_E::MCAST. 476 */ 477#define NIX_STAT_LF_TX_E_TX_BCAST (1) 478#define NIX_STAT_LF_TX_E_TX_DROP (3) 479#define NIX_STAT_LF_TX_E_TX_MCAST (2) 480#define NIX_STAT_LF_TX_E_TX_OCTS (4) 481#define NIX_STAT_LF_TX_E_TX_UCAST (0) 482 483/** 484 * Enumeration nix_stype_e 485 * 486 * NIX SQB Caching Type Enumeration Enumerates the values of 487 * NIX_SQ_CTX_S[SQE_STYPE]. 488 */ 489#define NIX_STYPE_E_STF (0) 490#define NIX_STYPE_E_STP (2) 491#define NIX_STYPE_E_STT (1) 492 493/** 494 * Enumeration nix_subdc_e 495 * 496 * NIX Subdescriptor Operation Enumeration Enumerates send and receive 497 * subdescriptor codes. The codes differentiate subdescriptors within a 498 * NIX send or receive descriptor, excluding NIX_SEND_HDR_S for send and 499 * NIX_CQE_HDR_S/NIX_WQE_HDR_S for receive, which are determined by their 500 * position as the first subdescriptor, and NIX_RX_PARSE_S, which is 501 * determined by its position as the second subdescriptor. 502 */ 503#define NIX_SUBDC_E_CRC (2) 504#define NIX_SUBDC_E_EXT (1) 505#define NIX_SUBDC_E_IMM (3) 506#define NIX_SUBDC_E_JUMP (6) 507#define NIX_SUBDC_E_MEM (5) 508#define NIX_SUBDC_E_NOP (0) 509#define NIX_SUBDC_E_SG (4) 510#define NIX_SUBDC_E_SOD (0xf) 511#define NIX_SUBDC_E_WORK (7) 512 513/** 514 * Enumeration nix_tx_actionop_e 515 * 516 * NIX Transmit Action Opcode Enumeration Enumerates the values of 517 * NIX_TX_ACTION_S[OP]. 518 */ 519#define NIX_TX_ACTIONOP_E_DROP (0) 520#define NIX_TX_ACTIONOP_E_DROP_VIOL (5) 521#define NIX_TX_ACTIONOP_E_MCAST (3) 522#define NIX_TX_ACTIONOP_E_UCAST_CHAN (2) 523#define NIX_TX_ACTIONOP_E_UCAST_DEFAULT (1) 524 525/** 526 * Enumeration nix_tx_vtagop_e 527 * 528 * NIX Transmit Vtag Opcode Enumeration Enumerates the values of 529 * NIX_TX_VTAG_ACTION_S[VTAG0_OP,VTAG1_OP]. 530 */ 531#define NIX_TX_VTAGOP_E_INSERT (1) 532#define NIX_TX_VTAGOP_E_NOP (0) 533#define NIX_TX_VTAGOP_E_REPLACE (2) 534 535/** 536 * Enumeration nix_txlayer_e 537 * 538 * NIX Transmit Layer Enumeration Enumerates the values of 539 * NIX_AF_LSO_FORMAT()_FIELD()[LAYER]. 540 */ 541#define NIX_TXLAYER_E_IL3 (2) 542#define NIX_TXLAYER_E_IL4 (3) 543#define NIX_TXLAYER_E_OL3 (0) 544#define NIX_TXLAYER_E_OL4 (1) 545 546/** 547 * Enumeration nix_vtagsize_e 548 * 549 * NIX Vtag Size Enumeration Enumerates the values of 550 * NIX_AF_TX_VTAG_DEF()_CTL[SIZE] and NIX_AF_LF()_RX_VTAG_TYPE()[SIZE]. 551 */ 552#define NIX_VTAGSIZE_E_T4 (0) 553#define NIX_VTAGSIZE_E_T8 (1) 554 555/** 556 * Enumeration nix_xqe_type_e 557 * 558 * NIX WQE/CQE Type Enumeration Enumerates the values of 559 * NIX_WQE_HDR_S[WQE_TYPE], NIX_CQE_HDR_S[CQE_TYPE]. 560 */ 561#define NIX_XQE_TYPE_E_INVALID (0) 562#define NIX_XQE_TYPE_E_RX (1) 563#define NIX_XQE_TYPE_E_RX_IPSECD (4) 564#define NIX_XQE_TYPE_E_RX_IPSECH (3) 565#define NIX_XQE_TYPE_E_RX_IPSECS (2) 566#define NIX_XQE_TYPE_E_SEND (8) 567 568/** 569 * Enumeration nix_xqesz_e 570 * 571 * NIX WQE/CQE Size Enumeration Enumerates the values of 572 * NIX_AF_LF()_CFG[XQE_SIZE]. 573 */ 574#define NIX_XQESZ_E_W16 (1) 575#define NIX_XQESZ_E_W64 (0) 576 577/** 578 * Structure nix_aq_inst_s 579 * 580 * NIX Admin Queue Instruction Structure This structure specifies the AQ 581 * instruction. Instructions and associated software structures are 582 * stored in memory as little-endian unless NIX_AF_CFG[AF_BE] is set. 583 * Hardware reads of NIX_AQ_INST_S do not allocate into LLC. Hardware 584 * reads and writes of the context structure selected by [CTYPE], [LF] 585 * and [CINDEX] use the NDC and LLC caching style configured for that 586 * context. For example: * When [CTYPE] = NIX_AQ_CTYPE_E::RQ: use 587 * NIX_AF_LF()_RSS_CFG[CACHING] and NIX_AF_LF()_RSS_CFG[WAY_MASK]. * When 588 * [CTYPE] = NIX_AQ_CTYPE_E::MCE: use NIX_AF_RX_MCAST_CFG[CACHING] and 589 * NIX_AF_RX_MCAST_CFG[WAY_MASK]. 590 */ 591union nix_aq_inst_s { 592 u64 u[2]; 593 struct nix_aq_inst_s_s { 594 u64 op : 4; 595 u64 ctype : 4; 596 u64 lf : 7; 597 u64 reserved_15_23 : 9; 598 u64 cindex : 20; 599 u64 reserved_44_62 : 19; 600 u64 doneint : 1; 601 u64 res_addr : 64; 602 } s; 603 /* struct nix_aq_inst_s_s cn; */ 604}; 605 606/** 607 * Structure nix_aq_res_s 608 * 609 * NIX Admin Queue Result Structure NIX writes this structure after it 610 * completes the NIX_AQ_INST_S instruction. The result structure is 611 * exactly 16 bytes, and each instruction completion produces exactly one 612 * result structure. Results and associated software structures are 613 * stored in memory as little-endian unless NIX_AF_CFG[AF_BE] is set. 614 * When [OP] = NIX_AQ_INSTOP_E::INIT, WRITE or READ, this structure is 615 * immediately followed by context read or write data. See 616 * NIX_AQ_INSTOP_E. Hardware writes of NIX_AQ_RES_S and context data 617 * always allocate into LLC. Hardware reads of context data do not 618 * allocate into LLC. 619 */ 620union nix_aq_res_s { 621 u64 u[2]; 622 struct nix_aq_res_s_s { 623 u64 op : 4; 624 u64 ctype : 4; 625 u64 compcode : 8; 626 u64 doneint : 1; 627 u64 reserved_17_63 : 47; 628 u64 reserved_64_127 : 64; 629 } s; 630 /* struct nix_aq_res_s_s cn; */ 631}; 632 633/** 634 * Structure nix_cint_hw_s 635 * 636 * NIX Completion Interrupt Context Hardware Structure This structure 637 * contains context state maintained by hardware for each completion 638 * interrupt (CINT) in NDC/LLC/DRAM. Software accesses this structure 639 * with the NIX_LF_CINT()* registers. Hardware maintains a table of 640 * NIX_AF_CONST2[CINTS] contiguous NIX_CINT_HW_S structures per LF 641 * starting at AF IOVA NIX_AF_LF()_CINTS_BASE. Always stored in byte 642 * invariant little-endian format (LE8). 643 */ 644union nix_cint_hw_s { 645 u64 u[2]; 646 struct nix_cint_hw_s_s { 647 u64 ecount : 32; 648 u64 qcount : 16; 649 u64 intr : 1; 650 u64 ena : 1; 651 u64 timer_idx : 8; 652 u64 reserved_58_63 : 6; 653 u64 ecount_wait : 32; 654 u64 qcount_wait : 16; 655 u64 time_wait : 8; 656 u64 reserved_120_127 : 8; 657 } s; 658 /* struct nix_cint_hw_s_s cn; */ 659}; 660 661/** 662 * Structure nix_cq_ctx_s 663 * 664 * NIX Completion Queue Context Structure This structure contains context 665 * state maintained by hardware for each CQ in NDC/LLC/DRAM. Software 666 * uses the same structure format to read and write an CQ context with 667 * the NIX admin queue. 668 */ 669union nix_cq_ctx_s { 670 u64 u[4]; 671 struct nix_cq_ctx_s_s { 672 u64 base : 64; 673 u64 reserved_64_67 : 4; 674 u64 bp_ena : 1; 675 u64 reserved_69_71 : 3; 676 u64 bpid : 9; 677 u64 reserved_81_83 : 3; 678 u64 qint_idx : 7; 679 u64 cq_err : 1; 680 u64 cint_idx : 7; 681 u64 avg_con : 9; 682 u64 wrptr : 20; 683 u64 tail : 20; 684 u64 head : 20; 685 u64 avg_level : 8; 686 u64 update_time : 16; 687 u64 bp : 8; 688 u64 drop : 8; 689 u64 drop_ena : 1; 690 u64 ena : 1; 691 u64 reserved_210_211 : 2; 692 u64 substream : 20; 693 u64 caching : 1; 694 u64 reserved_233_235 : 3; 695 u64 qsize : 4; 696 u64 cq_err_int : 8; 697 u64 cq_err_int_ena : 8; 698 } s; 699 /* struct nix_cq_ctx_s_s cn; */ 700}; 701 702/** 703 * Structure nix_cqe_hdr_s 704 * 705 * NIX Completion Queue Entry Header Structure This 64-bit structure 706 * defines the first word of every CQE. It is immediately followed by 707 * NIX_RX_PARSE_S in a receive CQE, and by NIX_SEND_COMP_S in a send 708 * completion CQE. Stored in memory as little-endian unless 709 * NIX_AF_LF()_CFG[BE] is set. 710 */ 711union nix_cqe_hdr_s { 712 u64 u; 713 struct nix_cqe_hdr_s_s { 714 u64 tag : 32; 715 u64 q : 20; 716 u64 reserved_52_57 : 6; 717 u64 node : 2; 718 u64 cqe_type : 4; 719 } s; 720 /* struct nix_cqe_hdr_s_s cn; */ 721}; 722 723/** 724 * Structure nix_inst_hdr_s 725 * 726 * NIX Instruction Header Structure This structure defines the 727 * instruction header that precedes the packet header supplied to NPC for 728 * packets to be transmitted by NIX. 729 */ 730union nix_inst_hdr_s { 731 u64 u; 732 struct nix_inst_hdr_s_s { 733 u64 pf_func : 16; 734 u64 sq : 20; 735 u64 reserved_36_63 : 28; 736 } s; 737 /* struct nix_inst_hdr_s_s cn; */ 738}; 739 740/** 741 * Structure nix_iova_s 742 * 743 * NIX I/O Virtual Address Structure 744 */ 745union nix_iova_s { 746 u64 u; 747 struct nix_iova_s_s { 748 u64 addr : 64; 749 } s; 750 /* struct nix_iova_s_s cn; */ 751}; 752 753/** 754 * Structure nix_ipsec_dyno_s 755 * 756 * INTERNAL: NIX IPSEC Dynamic Ordering Counter Structure Internal: Not 757 * used; no IPSEC fast-path. 758 */ 759union nix_ipsec_dyno_s { 760 u32 u; 761 struct nix_ipsec_dyno_s_s { 762 u32 count : 32; 763 } s; 764 /* struct nix_ipsec_dyno_s_s cn; */ 765}; 766 767/** 768 * Structure nix_mem_result_s 769 * 770 * NIX Memory Value Structure When 771 * NIX_SEND_MEM_S[ALG]=NIX_SENDMEMALG_E::SETRSLT, the value written to 772 * memory is formed with this structure. 773 */ 774union nix_mem_result_s { 775 u64 u; 776 struct nix_mem_result_s_s { 777 u64 v : 1; 778 u64 color : 2; 779 u64 reserved_3_63 : 61; 780 } s; 781 /* struct nix_mem_result_s_s cn; */ 782}; 783 784/** 785 * Structure nix_op_q_wdata_s 786 * 787 * NIX Statistics Operation Write Data Structure This structure specifies 788 * the write data format of an atomic 64-bit load-and-add of some 789 * NIX_LF_RQ_OP_*, NIX_LF_SQ_OP* and NIX_LF_CQ_OP* registers. 790 */ 791union nix_op_q_wdata_s { 792 u64 u; 793 struct nix_op_q_wdata_s_s { 794 u64 reserved_0_31 : 32; 795 u64 q : 20; 796 u64 reserved_52_63 : 12; 797 } s; 798 /* struct nix_op_q_wdata_s_s cn; */ 799}; 800 801/** 802 * Structure nix_qint_hw_s 803 * 804 * NIX Queue Interrupt Context Hardware Structure This structure contains 805 * context state maintained by hardware for each queue interrupt (QINT) 806 * in NDC/LLC/DRAM. Software accesses this structure with the 807 * NIX_LF_QINT()* registers. Hardware maintains a table of 808 * NIX_AF_CONST2[QINTS] contiguous NIX_QINT_HW_S structures per LF 809 * starting at IOVA NIX_AF_LF()_QINTS_BASE. Always stored in byte 810 * invariant little-endian format (LE8). 811 */ 812union nix_qint_hw_s { 813 u32 u; 814 struct nix_qint_hw_s_s { 815 u32 count : 22; 816 u32 reserved_22_30 : 9; 817 u32 ena : 1; 818 } s; 819 /* struct nix_qint_hw_s_s cn; */ 820}; 821 822/** 823 * Structure nix_rq_ctx_hw_s 824 * 825 * NIX Receive Queue Context Structure This structure contains context 826 * state maintained by hardware for each RQ in NDC/LLC/DRAM. Software 827 * uses the equivalent NIX_RQ_CTX_S structure format to read and write an 828 * RQ context with the NIX admin queue. Always stored in byte invariant 829 * little-endian format (LE8). 830 */ 831union nix_rq_ctx_hw_s { 832 u64 u[16]; 833 struct nix_rq_ctx_hw_s_s { 834 u64 ena : 1; 835 u64 sso_ena : 1; 836 u64 ipsech_ena : 1; 837 u64 ena_wqwd : 1; 838 u64 cq : 20; 839 u64 substream : 20; 840 u64 wqe_aura : 20; 841 u64 spb_aura : 20; 842 u64 lpb_aura : 20; 843 u64 sso_grp : 10; 844 u64 sso_tt : 2; 845 u64 pb_caching : 2; 846 u64 wqe_caching : 1; 847 u64 xqe_drop_ena : 1; 848 u64 spb_drop_ena : 1; 849 u64 lpb_drop_ena : 1; 850 u64 wqe_skip : 2; 851 u64 reserved_124_127 : 4; 852 u64 reserved_128_139 : 12; 853 u64 spb_sizem1 : 6; 854 u64 reserved_146_150 : 5; 855 u64 spb_ena : 1; 856 u64 lpb_sizem1 : 12; 857 u64 first_skip : 7; 858 u64 reserved_171 : 1; 859 u64 later_skip : 6; 860 u64 xqe_imm_size : 6; 861 u64 reserved_184_189 : 6; 862 u64 xqe_imm_copy : 1; 863 u64 xqe_hdr_split : 1; 864 u64 xqe_drop : 8; 865 u64 xqe_pass : 8; 866 u64 wqe_pool_drop : 8; 867 u64 wqe_pool_pass : 8; 868 u64 spb_aura_drop : 8; 869 u64 spb_aura_pass : 8; 870 u64 spb_pool_drop : 8; 871 u64 spb_pool_pass : 8; 872 u64 lpb_aura_drop : 8; 873 u64 lpb_aura_pass : 8; 874 u64 lpb_pool_drop : 8; 875 u64 lpb_pool_pass : 8; 876 u64 reserved_288_319 : 32; 877 u64 ltag : 24; 878 u64 good_utag : 8; 879 u64 bad_utag : 8; 880 u64 flow_tagw : 6; 881 u64 reserved_366_383 : 18; 882 u64 octs : 48; 883 u64 reserved_432_447 : 16; 884 u64 pkts : 48; 885 u64 reserved_496_511 : 16; 886 u64 drop_octs : 48; 887 u64 reserved_560_575 : 16; 888 u64 drop_pkts : 48; 889 u64 reserved_624_639 : 16; 890 u64 re_pkts : 48; 891 u64 reserved_688_702 : 15; 892 u64 ena_copy : 1; 893 u64 reserved_704_739 : 36; 894 u64 rq_int : 8; 895 u64 rq_int_ena : 8; 896 u64 qint_idx : 7; 897 u64 reserved_763_767 : 5; 898 u64 reserved_768_831 : 64; 899 u64 reserved_832_895 : 64; 900 u64 reserved_896_959 : 64; 901 u64 reserved_960_1023 : 64; 902 } s; 903 /* struct nix_rq_ctx_hw_s_s cn; */ 904}; 905 906/** 907 * Structure nix_rq_ctx_s 908 * 909 * NIX Receive Queue Context Structure This structure specifies the 910 * format used by software to read and write an RQ context with the NIX 911 * admin queue. 912 */ 913union nix_rq_ctx_s { 914 u64 u[16]; 915 struct nix_rq_ctx_s_s { 916 u64 ena : 1; 917 u64 sso_ena : 1; 918 u64 ipsech_ena : 1; 919 u64 ena_wqwd : 1; 920 u64 cq : 20; 921 u64 substream : 20; 922 u64 wqe_aura : 20; 923 u64 spb_aura : 20; 924 u64 lpb_aura : 20; 925 u64 sso_grp : 10; 926 u64 sso_tt : 2; 927 u64 pb_caching : 2; 928 u64 wqe_caching : 1; 929 u64 xqe_drop_ena : 1; 930 u64 spb_drop_ena : 1; 931 u64 lpb_drop_ena : 1; 932 u64 reserved_122_127 : 6; 933 u64 reserved_128_139 : 12; 934 u64 spb_sizem1 : 6; 935 u64 wqe_skip : 2; 936 u64 reserved_148_150 : 3; 937 u64 spb_ena : 1; 938 u64 lpb_sizem1 : 12; 939 u64 first_skip : 7; 940 u64 reserved_171 : 1; 941 u64 later_skip : 6; 942 u64 xqe_imm_size : 6; 943 u64 reserved_184_189 : 6; 944 u64 xqe_imm_copy : 1; 945 u64 xqe_hdr_split : 1; 946 u64 xqe_drop : 8; 947 u64 xqe_pass : 8; 948 u64 wqe_pool_drop : 8; 949 u64 wqe_pool_pass : 8; 950 u64 spb_aura_drop : 8; 951 u64 spb_aura_pass : 8; 952 u64 spb_pool_drop : 8; 953 u64 spb_pool_pass : 8; 954 u64 lpb_aura_drop : 8; 955 u64 lpb_aura_pass : 8; 956 u64 lpb_pool_drop : 8; 957 u64 lpb_pool_pass : 8; 958 u64 reserved_288_291 : 4; 959 u64 rq_int : 8; 960 u64 rq_int_ena : 8; 961 u64 qint_idx : 7; 962 u64 reserved_315_319 : 5; 963 u64 ltag : 24; 964 u64 good_utag : 8; 965 u64 bad_utag : 8; 966 u64 flow_tagw : 6; 967 u64 reserved_366_383 : 18; 968 u64 octs : 48; 969 u64 reserved_432_447 : 16; 970 u64 pkts : 48; 971 u64 reserved_496_511 : 16; 972 u64 drop_octs : 48; 973 u64 reserved_560_575 : 16; 974 u64 drop_pkts : 48; 975 u64 reserved_624_639 : 16; 976 u64 re_pkts : 48; 977 u64 reserved_688_703 : 16; 978 u64 reserved_704_767 : 64; 979 u64 reserved_768_831 : 64; 980 u64 reserved_832_895 : 64; 981 u64 reserved_896_959 : 64; 982 u64 reserved_960_1023 : 64; 983 } s; 984 /* struct nix_rq_ctx_s_s cn; */ 985}; 986 987/** 988 * Structure nix_rsse_s 989 * 990 * NIX Receive Side Scaling Entry Structure This structure specifies the 991 * format of each hardware entry in the NIX RSS tables in NDC/LLC/DRAM. 992 * See NIX_AF_LF()_RSS_BASE and NIX_AF_LF()_RSS_GRP(). Software uses the 993 * same structure format to read and write an RSS table entry with the 994 * NIX admin queue. 995 */ 996union nix_rsse_s { 997 u32 u; 998 struct nix_rsse_s_s { 999 u32 rq : 20; 1000 u32 reserved_20_31 : 12; 1001 } s; 1002 /* struct nix_rsse_s_s cn; */ 1003}; 1004 1005/** 1006 * Structure nix_rx_action_s 1007 * 1008 * NIX Receive Action Structure This structure defines the format of 1009 * NPC_RESULT_S[ACTION] for a receive packet. 1010 */ 1011union nix_rx_action_s { 1012 u64 u; 1013 struct nix_rx_action_s_s { 1014 u64 op : 4; 1015 u64 pf_func : 16; 1016 u64 index : 20; 1017 u64 match_id : 16; 1018 u64 flow_key_alg : 5; 1019 u64 reserved_61_63 : 3; 1020 } s; 1021 /* struct nix_rx_action_s_s cn; */ 1022}; 1023 1024/** 1025 * Structure nix_rx_imm_s 1026 * 1027 * NIX Receive Immediate Subdescriptor Structure The receive immediate 1028 * subdescriptor indicates that bytes immediately following this 1029 * NIX_RX_IMM_S (after skipping [APAD] bytes) were saved from the 1030 * received packet. The next subdescriptor following this NIX_RX_IMM_S 1031 * (when one exists) will follow the immediate bytes, after rounding up 1032 * the address to a multiple of 16 bytes. 1033 */ 1034union nix_rx_imm_s { 1035 u64 u; 1036 struct nix_rx_imm_s_s { 1037 u64 size : 16; 1038 u64 apad : 3; 1039 u64 reserved_19_59 : 41; 1040 u64 subdc : 4; 1041 } s; 1042 /* struct nix_rx_imm_s_s cn; */ 1043}; 1044 1045/** 1046 * Structure nix_rx_mce_s 1047 * 1048 * NIX Receive Multicast/Mirror Entry Structure This structure specifies 1049 * the format of entries in the NIX receive multicast/mirror table 1050 * maintained by hardware in NDC/LLC/DRAM. See NIX_AF_RX_MCAST_BASE and 1051 * NIX_AF_RX_MCAST_CFG. Note the table may contain both multicast and 1052 * mirror replication lists. Software uses the same structure format to 1053 * read and write a multicast/mirror table entry with the NIX admin 1054 * queue. 1055 */ 1056union nix_rx_mce_s { 1057 u64 u; 1058 struct nix_rx_mce_s_s { 1059 u64 op : 2; 1060 u64 reserved_2 : 1; 1061 u64 eol : 1; 1062 u64 index : 20; 1063 u64 reserved_24_31 : 8; 1064 u64 pf_func : 16; 1065 u64 next : 16; 1066 } s; 1067 /* struct nix_rx_mce_s_s cn; */ 1068}; 1069 1070/** 1071 * Structure nix_rx_parse_s 1072 * 1073 * NIX Receive Parse Structure This structure contains the receive packet 1074 * parse result. It immediately follows NIX_CQE_HDR_S in a receive CQE, 1075 * or NIX_WQE_HDR_S in a receive WQE. Stored in memory as little-endian 1076 * unless NIX_AF_LF()_CFG[BE] is set. Header layers are always 2-byte 1077 * aligned, so all header pointers in this structure ([EOH_PTR], [LAPTR] 1078 * through [LHPTR], [VTAG*_PTR]) are even. 1079 */ 1080union nix_rx_parse_s { 1081 u64 u[7]; 1082 struct nix_rx_parse_s_s { 1083 u64 chan : 12; 1084 u64 desc_sizem1 : 5; 1085 u64 imm_copy : 1; 1086 u64 express : 1; 1087 u64 wqwd : 1; 1088 u64 errlev : 4; 1089 u64 errcode : 8; 1090 u64 latype : 4; 1091 u64 lbtype : 4; 1092 u64 lctype : 4; 1093 u64 ldtype : 4; 1094 u64 letype : 4; 1095 u64 lftype : 4; 1096 u64 lgtype : 4; 1097 u64 lhtype : 4; 1098 u64 pkt_lenm1 : 16; 1099 u64 l2m : 1; 1100 u64 l2b : 1; 1101 u64 l3m : 1; 1102 u64 l3b : 1; 1103 u64 vtag0_valid : 1; 1104 u64 vtag0_gone : 1; 1105 u64 vtag1_valid : 1; 1106 u64 vtag1_gone : 1; 1107 u64 pkind : 6; 1108 u64 reserved_94_95 : 2; 1109 u64 vtag0_tci : 16; 1110 u64 vtag1_tci : 16; 1111 u64 laflags : 8; 1112 u64 lbflags : 8; 1113 u64 lcflags : 8; 1114 u64 ldflags : 8; 1115 u64 leflags : 8; 1116 u64 lfflags : 8; 1117 u64 lgflags : 8; 1118 u64 lhflags : 8; 1119 u64 eoh_ptr : 8; 1120 u64 wqe_aura : 20; 1121 u64 pb_aura : 20; 1122 u64 match_id : 16; 1123 u64 laptr : 8; 1124 u64 lbptr : 8; 1125 u64 lcptr : 8; 1126 u64 ldptr : 8; 1127 u64 leptr : 8; 1128 u64 lfptr : 8; 1129 u64 lgptr : 8; 1130 u64 lhptr : 8; 1131 u64 vtag0_ptr : 8; 1132 u64 vtag1_ptr : 8; 1133 u64 flow_key_alg : 5; 1134 u64 reserved_341_383 : 43; 1135 u64 reserved_384_447 : 64; 1136 } s; 1137 /* struct nix_rx_parse_s_s cn; */ 1138}; 1139 1140/** 1141 * Structure nix_rx_sg_s 1142 * 1143 * NIX Receive Scatter/Gather Subdescriptor Structure The receive 1144 * scatter/gather subdescriptor specifies one to three segments of packet 1145 * data bytes. There may be multiple NIX_RX_SG_Ss in each NIX receive 1146 * descriptor. NIX_RX_SG_S is immediately followed by one NIX_IOVA_S 1147 * word when [SEGS] = 1, three NIX_IOVA_S words when [SEGS] \>= 2. Each 1148 * NIX_IOVA_S word specifies the LF IOVA of first packet data byte in the 1149 * corresponding segment; first NIX_IOVA_S word for segment 1, second 1150 * word for segment 2, third word for segment 3. Note the third word is 1151 * present when [SEGS] \>= 2 but only valid when [SEGS] = 3. 1152 */ 1153union nix_rx_sg_s { 1154 u64 u; 1155 struct nix_rx_sg_s_s { 1156 u64 seg1_size : 16; 1157 u64 seg2_size : 16; 1158 u64 seg3_size : 16; 1159 u64 segs : 2; 1160 u64 reserved_50_59 : 10; 1161 u64 subdc : 4; 1162 } s; 1163 /* struct nix_rx_sg_s_s cn; */ 1164}; 1165 1166/** 1167 * Structure nix_rx_vtag_action_s 1168 * 1169 * NIX Receive Vtag Action Structure This structure defines the format of 1170 * NPC_RESULT_S[VTAG_ACTION] for a receive packet. It specifies up to two 1171 * Vtags (e.g. C-VLAN/S-VLAN tags, 802.1BR E-TAG) for optional capture 1172 * and/or stripping. 1173 */ 1174union nix_rx_vtag_action_s { 1175 u64 u; 1176 struct nix_rx_vtag_action_s_s { 1177 u64 vtag0_relptr : 8; 1178 u64 vtag0_lid : 3; 1179 u64 reserved_11 : 1; 1180 u64 vtag0_type : 3; 1181 u64 vtag0_valid : 1; 1182 u64 reserved_16_31 : 16; 1183 u64 vtag1_relptr : 8; 1184 u64 vtag1_lid : 3; 1185 u64 reserved_43 : 1; 1186 u64 vtag1_type : 3; 1187 u64 vtag1_valid : 1; 1188 u64 reserved_48_63 : 16; 1189 } s; 1190 /* struct nix_rx_vtag_action_s_s cn; */ 1191}; 1192 1193/** 1194 * Structure nix_send_comp_s 1195 * 1196 * NIX Send Completion Structure This structure immediately follows 1197 * NIX_CQE_HDR_S in a send completion CQE. 1198 */ 1199union nix_send_comp_s { 1200 u64 u; 1201 struct nix_send_comp_s_s { 1202 u64 status : 8; 1203 u64 sqe_id : 16; 1204 u64 reserved_24_63 : 40; 1205 } s; 1206 /* struct nix_send_comp_s_s cn; */ 1207}; 1208 1209/** 1210 * Structure nix_send_crc_s 1211 * 1212 * NIX Send CRC Subdescriptor Structure The send CRC subdescriptor 1213 * specifies a CRC calculation be performed during transmission. Ignored 1214 * when present in a send descriptor with NIX_SEND_EXT_S[LSO] set. There 1215 * may be up to two NIX_SEND_CRC_Ss per send descriptor. NIX_SEND_CRC_S 1216 * constraints: * When present, NIX_SEND_CRC_S subdescriptors must 1217 * precede all NIX_SEND_SG_S, NIX_SEND_IMM_S and NIX_SEND_MEM_S 1218 * subdescriptors in the send descriptor. * NIX_SEND_CRC_S subdescriptors 1219 * must follow the same order as their checksum and insert regions in the 1220 * packet, i.e. the checksum and insert regions of a NIX_SEND_CRC_S must 1221 * come after the checksum and insert regions of a preceding 1222 * NIX_SEND_CRC_S. There must be no overlap between any NIX_SEND_CRC_S 1223 * checksum and insert regions. * If either 1224 * NIX_SEND_HDR_S[OL4TYPE,IL4TYPE] = NIX_SENDL4TYPE_E::SCTP_CKSUM, the 1225 * SCTP checksum region and NIX_SEND_CRC_S insert region must not 1226 * overlap, and likewise the NIX_SEND_CRC_S checksum region and SCTP 1227 * insert region must not overlap. * If either 1228 * NIX_SEND_HDR_S[OL3TYPE,IL3TYPE] = NIX_SENDL3TYPE_E::IP4_CKSUM, the 1229 * IPv4 header checksum region and NIX_SEND_CRC_S insert region must not 1230 * overlap. * Any checksums inserted by 1231 * NIX_SEND_HDR_S[OL3TYPE,OL4TYPE,IL3TYPE,IL4TYPE] must be outside of the 1232 * NIX_SEND_CRC_S checksum and insert regions. Hardware adjusts [START], 1233 * [SIZE] and [INSERT] as needed to account for any VLAN inserted by 1234 * NIX_SEND_EXT_S[VLAN*] or Vtag inserted by NIX_TX_VTAG_ACTION_S. 1235 */ 1236union nix_send_crc_s { 1237 u64 u[2]; 1238 struct nix_send_crc_s_s { 1239 u64 size : 16; 1240 u64 start : 16; 1241 u64 insert : 16; 1242 u64 reserved_48_57 : 10; 1243 u64 alg : 2; 1244 u64 subdc : 4; 1245 u64 iv : 32; 1246 u64 reserved_96_127 : 32; 1247 } s; 1248 /* struct nix_send_crc_s_s cn; */ 1249}; 1250 1251/** 1252 * Structure nix_send_ext_s 1253 * 1254 * NIX Send Extended Header Subdescriptor Structure The send extended 1255 * header specifies LSO, VLAN insertion, timestamp and/or scheduling 1256 * services on the packet. If present, it must immediately follow 1257 * NIX_SEND_HDR_S. All fields are assumed to be zero when this 1258 * subdescriptor is not present. 1259 */ 1260union nix_send_ext_s { 1261 u64 u[2]; 1262 struct nix_send_ext_s_s { 1263 u64 lso_mps : 14; 1264 u64 lso : 1; 1265 u64 tstmp : 1; 1266 u64 lso_sb : 8; 1267 u64 lso_format : 5; 1268 u64 reserved_29_31 : 3; 1269 u64 shp_chg : 9; 1270 u64 shp_dis : 1; 1271 u64 shp_ra : 2; 1272 u64 markptr : 8; 1273 u64 markform : 7; 1274 u64 mark_en : 1; 1275 u64 subdc : 4; 1276 u64 vlan0_ins_ptr : 8; 1277 u64 vlan0_ins_tci : 16; 1278 u64 vlan1_ins_ptr : 8; 1279 u64 vlan1_ins_tci : 16; 1280 u64 vlan0_ins_ena : 1; 1281 u64 vlan1_ins_ena : 1; 1282 u64 reserved_114_127 : 14; 1283 } s; 1284 /* struct nix_send_ext_s_s cn; */ 1285}; 1286 1287/** 1288 * Structure nix_send_hdr_s 1289 * 1290 * NIX Send Header Subdescriptor Structure The send header is the first 1291 * subdescriptor of every send descriptor. 1292 */ 1293union nix_send_hdr_s { 1294 u64 u[2]; 1295 struct nix_send_hdr_s_s { 1296 u64 total : 18; 1297 u64 reserved_18 : 1; 1298 u64 df : 1; 1299 u64 aura : 20; 1300 u64 sizem1 : 3; 1301 u64 pnc : 1; 1302 u64 sq : 20; 1303 u64 ol3ptr : 8; 1304 u64 ol4ptr : 8; 1305 u64 il3ptr : 8; 1306 u64 il4ptr : 8; 1307 u64 ol3type : 4; 1308 u64 ol4type : 4; 1309 u64 il3type : 4; 1310 u64 il4type : 4; 1311 u64 sqe_id : 16; 1312 } s; 1313 /* struct nix_send_hdr_s_s cn; */ 1314}; 1315 1316/** 1317 * Structure nix_send_imm_s 1318 * 1319 * NIX Send Immediate Subdescriptor Structure The send immediate 1320 * subdescriptor requests that bytes immediately following this 1321 * NIX_SEND_IMM_S (after skipping [APAD] bytes) are to be included in the 1322 * packet data. The next subdescriptor following this NIX_SEND_IMM_S 1323 * (when one exists) will follow the immediate bytes, after rounding up 1324 * the address to a multiple of 16 bytes. There may be multiple 1325 * NIX_SEND_IMM_S in one NIX send descriptor. A NIX_SEND_IMM_S is ignored 1326 * in a NIX send descriptor if the sum of all prior 1327 * NIX_SEND_SG_S[SEG*_SIZE]s and NIX_SEND_IMM_S[SIZE]s meets or exceeds 1328 * NIX_SEND_HDR_S[TOTAL]. When NIX_SEND_EXT_S[LSO] is set in the 1329 * descriptor, all NIX_SEND_IMM_S bytes must be included in the first 1330 * NIX_SEND_EXT_S[LSO_SB] bytes of the source packet. 1331 */ 1332union nix_send_imm_s { 1333 u64 u; 1334 struct nix_send_imm_s_s { 1335 u64 size : 16; 1336 u64 apad : 3; 1337 u64 reserved_19_59 : 41; 1338 u64 subdc : 4; 1339 } s; 1340 /* struct nix_send_imm_s_s cn; */ 1341}; 1342 1343/** 1344 * Structure nix_send_jump_s 1345 * 1346 * NIX Send Jump Subdescriptor Structure The send jump subdescriptor 1347 * selects a new address for fetching the remaining subdescriptors of a 1348 * send descriptor. This allows software to create a send descriptor 1349 * longer than SQE size selected by NIX_SQ_CTX_S[MAX_SQE_SIZE]. There 1350 * can be only one NIX_SEND_JUMP_S subdescriptor in a send descriptor. If 1351 * present, it must immediately follow NIX_SEND_HDR_S if NIX_SEND_EXT_S 1352 * is not present, else it must immediately follow NIX_SEND_EXT_S. In 1353 * either case, it must terminate the SQE enqueued by software. 1354 */ 1355union nix_send_jump_s { 1356 u64 u[2]; 1357 struct nix_send_jump_s_s { 1358 u64 sizem1 : 7; 1359 u64 reserved_7_13 : 7; 1360 u64 ld_type : 2; 1361 u64 aura : 20; 1362 u64 reserved_36_58 : 23; 1363 u64 f : 1; 1364 u64 subdc : 4; 1365 u64 addr : 64; 1366 } s; 1367 /* struct nix_send_jump_s_s cn; */ 1368}; 1369 1370/** 1371 * Structure nix_send_mem_s 1372 * 1373 * NIX Send Memory Subdescriptor Structure The send memory subdescriptor 1374 * atomically sets, increments or decrements a memory location. 1375 * NIX_SEND_MEM_S subdescriptors must follow all NIX_SEND_SG_S and 1376 * NIX_SEND_IMM_S subdescriptors in the NIX send descriptor. NIX will not 1377 * initiate the memory update for this subdescriptor until after it has 1378 * completed all LLC/DRAM fetches that service all prior NIX_SEND_SG_S 1379 * subdescriptors. The memory update is executed once, even if the packet 1380 * is replicated due to NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST. 1381 * Performance is best if a memory decrement by one is used rather than 1382 * any other memory set/increment/decrement. (Less internal bus bandwidth 1383 * is used with memory decrements by one.) When NIX_SEND_EXT_S[LSO] is 1384 * set in the descriptor, NIX executes the memory update only while 1385 * processing the last LSO segment, after processing prior segments. 1386 */ 1387union nix_send_mem_s { 1388 u64 u[2]; 1389 struct nix_send_mem_s_s { 1390 u64 offset : 16; 1391 u64 reserved_16_52 : 37; 1392 u64 wmem : 1; 1393 u64 dsz : 2; 1394 u64 alg : 4; 1395 u64 subdc : 4; 1396 u64 addr : 64; 1397 } s; 1398 /* struct nix_send_mem_s_s cn; */ 1399}; 1400 1401/** 1402 * Structure nix_send_sg_s 1403 * 1404 * NIX Send Scatter/Gather Subdescriptor Structure The send 1405 * scatter/gather subdescriptor requests one to three segments of packet 1406 * data bytes to be transmitted. There may be multiple NIX_SEND_SG_Ss in 1407 * each NIX send descriptor. NIX_SEND_SG_S is immediately followed by 1408 * one NIX_IOVA_S word when [SEGS] = 1, three NIX_IOVA_S words when 1409 * [SEGS] \>= 2. Each NIX_IOVA_S word specifies the LF IOVA of first 1410 * packet data byte in the corresponding segment; first NIX_IOVA_S word 1411 * for segment 1, second word for segment 2, third word for segment 3. 1412 * Note the third word is present when [SEGS] \>= 2 but only valid when 1413 * [SEGS] = 3. If the sum of all prior NIX_SEND_SG_S[SEG*_SIZE]s and 1414 * NIX_SEND_IMM_S[SIZE]s meets or exceeds NIX_SEND_HDR_S[TOTAL], this 1415 * subdescriptor will not contribute any packet data but may free buffers 1416 * to NPA (see [I1]). 1417 */ 1418union nix_send_sg_s { 1419 u64 u; 1420 struct nix_send_sg_s_s { 1421 u64 seg1_size : 16; 1422 u64 seg2_size : 16; 1423 u64 seg3_size : 16; 1424 u64 segs : 2; 1425 u64 reserved_50_54 : 5; 1426 u64 i1 : 1; 1427 u64 i2 : 1; 1428 u64 i3 : 1; 1429 u64 ld_type : 2; 1430 u64 subdc : 4; 1431 } s; 1432 /* struct nix_send_sg_s_s cn; */ 1433}; 1434 1435/** 1436 * Structure nix_send_work_s 1437 * 1438 * NIX Send Work Subdescriptor Structure This subdescriptor adds work to 1439 * the SSO. At most one NIX_SEND_WORK_S subdescriptor can exist in the 1440 * NIX send descriptor. If a NIX_SEND_WORK_S exists in the descriptor, it 1441 * must be the last subdescriptor. NIX will not initiate the work add for 1442 * this subdescriptor until after (1) it has completed all LLC/DRAM 1443 * fetches that service all prior NIX_SEND_SG_S subdescriptors, (2) it 1444 * has fetched all subdescriptors in the descriptor, and (3) all 1445 * NIX_SEND_MEM_S[WMEM]=1 LLC/DRAM updates have completed. Provided the 1446 * path of descriptors from the SQ through NIX to an output FIFO is 1447 * unmodified between the descriptors (as should normally be the case, 1448 * but it is possible for software to change the path), NIX also (1) will 1449 * submit the SSO add works from all descriptors in the SQ in order, and 1450 * (2) will not submit an SSO work add until after all prior descriptors 1451 * in the SQ have completed their NIX_SEND_SG_S processing, and (3) will 1452 * not submit an SSO work add until after it has fetched all 1453 * subdescriptors from prior descriptors in the SQ. When 1454 * NIX_SEND_EXT_S[LSO] is set in the descriptor, NIX executes the 1455 * NIX_SEND_WORK_S work add only while processing the last LSO segment, 1456 * after processing prior segments. Hardware ignores NIX_SEND_WORK_S 1457 * when NIX_SQ_CTX_S[SSO_ENA] is clear. 1458 */ 1459union nix_send_work_s { 1460 u64 u[2]; 1461 struct nix_send_work_s_s { 1462 u64 tag : 32; 1463 u64 tt : 2; 1464 u64 grp : 10; 1465 u64 reserved_44_59 : 16; 1466 u64 subdc : 4; 1467 u64 addr : 64; 1468 } s; 1469 /* struct nix_send_work_s_s cn; */ 1470}; 1471 1472/** 1473 * Structure nix_sq_ctx_hw_s 1474 * 1475 * NIX SQ Context Hardware Structure This structure contains context 1476 * state maintained by hardware for each SQ in NDC/LLC/DRAM. Software 1477 * uses the equivalent NIX_SQ_CTX_S structure format to read and write an 1478 * SQ context with the NIX admin queue. Always stored in byte invariant 1479 * little-endian format (LE8). 1480 */ 1481union nix_sq_ctx_hw_s { 1482 u64 u[16]; 1483 struct nix_sq_ctx_hw_s_s { 1484 u64 ena : 1; 1485 u64 substream : 20; 1486 u64 max_sqe_size : 2; 1487 u64 sqe_way_mask : 16; 1488 u64 sqb_aura : 20; 1489 u64 gbl_rsvd1 : 5; 1490 u64 cq_id : 20; 1491 u64 cq_ena : 1; 1492 u64 qint_idx : 6; 1493 u64 gbl_rsvd2 : 1; 1494 u64 sq_int : 8; 1495 u64 sq_int_ena : 8; 1496 u64 xoff : 1; 1497 u64 sqe_stype : 2; 1498 u64 gbl_rsvd : 17; 1499 u64 head_sqb : 64; 1500 u64 head_offset : 6; 1501 u64 sqb_dequeue_count : 16; 1502 u64 default_chan : 12; 1503 u64 sdp_mcast : 1; 1504 u64 sso_ena : 1; 1505 u64 dse_rsvd1 : 28; 1506 u64 sqb_enqueue_count : 16; 1507 u64 tail_offset : 6; 1508 u64 lmt_dis : 1; 1509 u64 smq_rr_quantum : 24; 1510 u64 dnq_rsvd1 : 17; 1511 u64 tail_sqb : 64; 1512 u64 next_sqb : 64; 1513 u64 mnq_dis : 1; 1514 u64 smq : 9; 1515 u64 smq_pend : 1; 1516 u64 smq_next_sq : 20; 1517 u64 smq_next_sq_vld : 1; 1518 u64 scm1_rsvd2 : 32; 1519 u64 smenq_sqb : 64; 1520 u64 smenq_offset : 6; 1521 u64 cq_limit : 8; 1522 u64 smq_rr_count : 25; 1523 u64 scm_lso_rem : 18; 1524 u64 scm_dq_rsvd0 : 7; 1525 u64 smq_lso_segnum : 8; 1526 u64 vfi_lso_total : 18; 1527 u64 vfi_lso_sizem1 : 3; 1528 u64 vfi_lso_sb : 8; 1529 u64 vfi_lso_mps : 14; 1530 u64 vfi_lso_vlan0_ins_ena : 1; 1531 u64 vfi_lso_vlan1_ins_ena : 1; 1532 u64 vfi_lso_vld : 1; 1533 u64 smenq_next_sqb_vld : 1; 1534 u64 scm_dq_rsvd1 : 9; 1535 u64 smenq_next_sqb : 64; 1536 u64 seb_rsvd1 : 64; 1537 u64 drop_pkts : 48; 1538 u64 drop_octs_lsw : 16; 1539 u64 drop_octs_msw : 32; 1540 u64 pkts_lsw : 32; 1541 u64 pkts_msw : 16; 1542 u64 octs : 48; 1543 } s; 1544 /* struct nix_sq_ctx_hw_s_s cn; */ 1545}; 1546 1547/** 1548 * Structure nix_sq_ctx_s 1549 * 1550 * NIX Send Queue Context Structure This structure specifies the format 1551 * used by software with the NIX admin queue to read and write a send 1552 * queue's NIX_SQ_CTX_HW_S structure maintained by hardware in 1553 * NDC/LLC/DRAM. The SQ statistics ([OCTS], [PKTS], [DROP_OCTS], 1554 * [DROP_PKTS]) do not account for packet replication due to 1555 * NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST. 1556 */ 1557union nix_sq_ctx_s { 1558 u64 u[16]; 1559 struct nix_sq_ctx_s_s { 1560 u64 ena : 1; 1561 u64 qint_idx : 6; 1562 u64 substream : 20; 1563 u64 sdp_mcast : 1; 1564 u64 cq : 20; 1565 u64 sqe_way_mask : 16; 1566 u64 smq : 9; 1567 u64 cq_ena : 1; 1568 u64 xoff : 1; 1569 u64 sso_ena : 1; 1570 u64 smq_rr_quantum : 24; 1571 u64 default_chan : 12; 1572 u64 sqb_count : 16; 1573 u64 smq_rr_count : 25; 1574 u64 sqb_aura : 20; 1575 u64 sq_int : 8; 1576 u64 sq_int_ena : 8; 1577 u64 sqe_stype : 2; 1578 u64 reserved_191 : 1; 1579 u64 max_sqe_size : 2; 1580 u64 cq_limit : 8; 1581 u64 lmt_dis : 1; 1582 u64 mnq_dis : 1; 1583 u64 smq_next_sq : 20; 1584 u64 smq_lso_segnum : 8; 1585 u64 tail_offset : 6; 1586 u64 smenq_offset : 6; 1587 u64 head_offset : 6; 1588 u64 smenq_next_sqb_vld : 1; 1589 u64 smq_pend : 1; 1590 u64 smq_next_sq_vld : 1; 1591 u64 reserved_253_255 : 3; 1592 u64 next_sqb : 64; 1593 u64 tail_sqb : 64; 1594 u64 smenq_sqb : 64; 1595 u64 smenq_next_sqb : 64; 1596 u64 head_sqb : 64; 1597 u64 reserved_576_583 : 8; 1598 u64 vfi_lso_total : 18; 1599 u64 vfi_lso_sizem1 : 3; 1600 u64 vfi_lso_sb : 8; 1601 u64 vfi_lso_mps : 14; 1602 u64 vfi_lso_vlan0_ins_ena : 1; 1603 u64 vfi_lso_vlan1_ins_ena : 1; 1604 u64 vfi_lso_vld : 1; 1605 u64 reserved_630_639 : 10; 1606 u64 scm_lso_rem : 18; 1607 u64 reserved_658_703 : 46; 1608 u64 octs : 48; 1609 u64 reserved_752_767 : 16; 1610 u64 pkts : 48; 1611 u64 reserved_816_831 : 16; 1612 u64 reserved_832_895 : 64; 1613 u64 drop_octs : 48; 1614 u64 reserved_944_959 : 16; 1615 u64 drop_pkts : 48; 1616 u64 reserved_1008_1023 : 16; 1617 } s; 1618 /* struct nix_sq_ctx_s_s cn; */ 1619}; 1620 1621/** 1622 * Structure nix_tx_action_s 1623 * 1624 * NIX Transmit Action Structure This structure defines the format of 1625 * NPC_RESULT_S[ACTION] for a transmit packet. 1626 */ 1627union nix_tx_action_s { 1628 u64 u; 1629 struct nix_tx_action_s_s { 1630 u64 op : 4; 1631 u64 reserved_4_11 : 8; 1632 u64 index : 20; 1633 u64 match_id : 16; 1634 u64 reserved_48_63 : 16; 1635 } s; 1636 /* struct nix_tx_action_s_s cn; */ 1637}; 1638 1639/** 1640 * Structure nix_tx_vtag_action_s 1641 * 1642 * NIX Transmit Vtag Action Structure This structure defines the format 1643 * of NPC_RESULT_S[VTAG_ACTION] for a transmit packet. It specifies the 1644 * optional insertion or replacement of up to two Vtags (e.g. 1645 * C-VLAN/S-VLAN tags, 802.1BR E-TAG). If two Vtags are specified: * The 1646 * Vtag 0 byte offset from packet start (see [VTAG0_RELPTR]) must be less 1647 * than or equal to the Vtag 1 byte offset. * Hardware executes the Vtag 1648 * 0 action first, Vtag 1 action second. * If Vtag 0 is inserted, 1649 * hardware adjusts the Vtag 1 byte offset accordingly. Thus, if the two 1650 * offsets are equal in the structure, hardware inserts Vtag 1 1651 * immediately after Vtag 0 in the packet. A Vtag must not be inserted 1652 * or replaced within an outer or inner L3/L4 header, but may be inserted 1653 * or replaced within an outer L4 payload. 1654 */ 1655union nix_tx_vtag_action_s { 1656 u64 u; 1657 struct nix_tx_vtag_action_s_s { 1658 u64 vtag0_relptr : 8; 1659 u64 vtag0_lid : 3; 1660 u64 reserved_11 : 1; 1661 u64 vtag0_op : 2; 1662 u64 reserved_14_15 : 2; 1663 u64 vtag0_def : 10; 1664 u64 reserved_26_31 : 6; 1665 u64 vtag1_relptr : 8; 1666 u64 vtag1_lid : 3; 1667 u64 reserved_43 : 1; 1668 u64 vtag1_op : 2; 1669 u64 reserved_46_47 : 2; 1670 u64 vtag1_def : 10; 1671 u64 reserved_58_63 : 6; 1672 } s; 1673 /* struct nix_tx_vtag_action_s_s cn; */ 1674}; 1675 1676/** 1677 * Structure nix_wqe_hdr_s 1678 * 1679 * NIX Work Queue Entry Header Structure This 64-bit structure defines 1680 * the first word of every receive WQE generated by NIX. It is 1681 * immediately followed by NIX_RX_PARSE_S. Stored in memory as little- 1682 * endian unless NIX_AF_LF()_CFG[BE] is set. 1683 */ 1684union nix_wqe_hdr_s { 1685 u64 u; 1686 struct nix_wqe_hdr_s_s { 1687 u64 tag : 32; 1688 u64 tt : 2; 1689 u64 grp : 10; 1690 u64 node : 2; 1691 u64 q : 14; 1692 u64 wqe_type : 4; 1693 } s; 1694 /* struct nix_wqe_hdr_s_s cn; */ 1695}; 1696 1697/** 1698 * Register (RVU_PF_BAR0) nix#_af_aq_base 1699 * 1700 * NIX AF Admin Queue Base Address Register 1701 */ 1702union nixx_af_aq_base { 1703 u64 u; 1704 struct nixx_af_aq_base_s { 1705 u64 reserved_0_6 : 7; 1706 u64 base_addr : 46; 1707 u64 reserved_53_63 : 11; 1708 } s; 1709 /* struct nixx_af_aq_base_s cn; */ 1710}; 1711 1712static inline u64 NIXX_AF_AQ_BASE(void) 1713 __attribute__ ((pure, always_inline)); 1714static inline u64 NIXX_AF_AQ_BASE(void) 1715{ 1716 return 0x410; 1717} 1718 1719/** 1720 * Register (RVU_PF_BAR0) nix#_af_aq_cfg 1721 * 1722 * NIX AF Admin Queue Configuration Register 1723 */ 1724union nixx_af_aq_cfg { 1725 u64 u; 1726 struct nixx_af_aq_cfg_s { 1727 u64 qsize : 4; 1728 u64 reserved_4_63 : 60; 1729 } s; 1730 /* struct nixx_af_aq_cfg_s cn; */ 1731}; 1732 1733static inline u64 NIXX_AF_AQ_CFG(void) 1734 __attribute__ ((pure, always_inline)); 1735static inline u64 NIXX_AF_AQ_CFG(void) 1736{ 1737 return 0x400; 1738} 1739 1740/** 1741 * Register (RVU_PF_BAR0) nix#_af_aq_done 1742 * 1743 * NIX AF Admin Queue Done Count Register 1744 */ 1745union nixx_af_aq_done { 1746 u64 u; 1747 struct nixx_af_aq_done_s { 1748 u64 done : 20; 1749 u64 reserved_20_63 : 44; 1750 } s; 1751 /* struct nixx_af_aq_done_s cn; */ 1752}; 1753 1754static inline u64 NIXX_AF_AQ_DONE(void) 1755 __attribute__ ((pure, always_inline)); 1756static inline u64 NIXX_AF_AQ_DONE(void) 1757{ 1758 return 0x450; 1759} 1760 1761/** 1762 * Register (RVU_PF_BAR0) nix#_af_aq_done_ack 1763 * 1764 * NIX AF Admin Queue Done Count Ack Register This register is written by 1765 * software to acknowledge interrupts. 1766 */ 1767union nixx_af_aq_done_ack { 1768 u64 u; 1769 struct nixx_af_aq_done_ack_s { 1770 u64 done_ack : 20; 1771 u64 reserved_20_63 : 44; 1772 } s; 1773 /* struct nixx_af_aq_done_ack_s cn; */ 1774}; 1775 1776static inline u64 NIXX_AF_AQ_DONE_ACK(void) 1777 __attribute__ ((pure, always_inline)); 1778static inline u64 NIXX_AF_AQ_DONE_ACK(void) 1779{ 1780 return 0x460; 1781} 1782 1783/** 1784 * Register (RVU_PF_BAR0) nix#_af_aq_done_ena_w1c 1785 * 1786 * NIX AF Admin Queue Done Interrupt Enable Clear Register 1787 */ 1788union nixx_af_aq_done_ena_w1c { 1789 u64 u; 1790 struct nixx_af_aq_done_ena_w1c_s { 1791 u64 done : 1; 1792 u64 reserved_1_63 : 63; 1793 } s; 1794 /* struct nixx_af_aq_done_ena_w1c_s cn; */ 1795}; 1796 1797static inline u64 NIXX_AF_AQ_DONE_ENA_W1C(void) 1798 __attribute__ ((pure, always_inline)); 1799static inline u64 NIXX_AF_AQ_DONE_ENA_W1C(void) 1800{ 1801 return 0x498; 1802} 1803 1804/** 1805 * Register (RVU_PF_BAR0) nix#_af_aq_done_ena_w1s 1806 * 1807 * NIX AF Admin Queue Done Interrupt Enable Set Register 1808 */ 1809union nixx_af_aq_done_ena_w1s { 1810 u64 u; 1811 struct nixx_af_aq_done_ena_w1s_s { 1812 u64 done : 1; 1813 u64 reserved_1_63 : 63; 1814 } s; 1815 /* struct nixx_af_aq_done_ena_w1s_s cn; */ 1816}; 1817 1818static inline u64 NIXX_AF_AQ_DONE_ENA_W1S(void) 1819 __attribute__ ((pure, always_inline)); 1820static inline u64 NIXX_AF_AQ_DONE_ENA_W1S(void) 1821{ 1822 return 0x490; 1823} 1824 1825/** 1826 * Register (RVU_PF_BAR0) nix#_af_aq_done_int 1827 * 1828 * INTERNAL: NIX AF Admin Queue Done Interrupt Register 1829 */ 1830union nixx_af_aq_done_int { 1831 u64 u; 1832 struct nixx_af_aq_done_int_s { 1833 u64 done : 1; 1834 u64 reserved_1_63 : 63; 1835 } s; 1836 /* struct nixx_af_aq_done_int_s cn; */ 1837}; 1838 1839static inline u64 NIXX_AF_AQ_DONE_INT(void) 1840 __attribute__ ((pure, always_inline)); 1841static inline u64 NIXX_AF_AQ_DONE_INT(void) 1842{ 1843 return 0x480; 1844} 1845 1846/** 1847 * Register (RVU_PF_BAR0) nix#_af_aq_done_int_w1s 1848 * 1849 * INTERNAL: NIX AF Admin Queue Done Interrupt Set Register 1850 */ 1851union nixx_af_aq_done_int_w1s { 1852 u64 u; 1853 struct nixx_af_aq_done_int_w1s_s { 1854 u64 done : 1; 1855 u64 reserved_1_63 : 63; 1856 } s; 1857 /* struct nixx_af_aq_done_int_w1s_s cn; */ 1858}; 1859 1860static inline u64 NIXX_AF_AQ_DONE_INT_W1S(void) 1861 __attribute__ ((pure, always_inline)); 1862static inline u64 NIXX_AF_AQ_DONE_INT_W1S(void) 1863{ 1864 return 0x488; 1865} 1866 1867/** 1868 * Register (RVU_PF_BAR0) nix#_af_aq_done_timer 1869 * 1870 * NIX AF Admin Queue Done Interrupt Timer Register 1871 */ 1872union nixx_af_aq_done_timer { 1873 u64 u; 1874 struct nixx_af_aq_done_timer_s { 1875 u64 count : 16; 1876 u64 reserved_16_63 : 48; 1877 } s; 1878 /* struct nixx_af_aq_done_timer_s cn; */ 1879}; 1880 1881static inline u64 NIXX_AF_AQ_DONE_TIMER(void) 1882 __attribute__ ((pure, always_inline)); 1883static inline u64 NIXX_AF_AQ_DONE_TIMER(void) 1884{ 1885 return 0x470; 1886} 1887 1888/** 1889 * Register (RVU_PF_BAR0) nix#_af_aq_done_wait 1890 * 1891 * NIX AF Admin Queue Done Interrupt Coalescing Wait Register Specifies 1892 * the queue interrupt coalescing settings. 1893 */ 1894union nixx_af_aq_done_wait { 1895 u64 u; 1896 struct nixx_af_aq_done_wait_s { 1897 u64 num_wait : 20; 1898 u64 reserved_20_31 : 12; 1899 u64 time_wait : 16; 1900 u64 reserved_48_63 : 16; 1901 } s; 1902 /* struct nixx_af_aq_done_wait_s cn; */ 1903}; 1904 1905static inline u64 NIXX_AF_AQ_DONE_WAIT(void) 1906 __attribute__ ((pure, always_inline)); 1907static inline u64 NIXX_AF_AQ_DONE_WAIT(void) 1908{ 1909 return 0x440; 1910} 1911 1912/** 1913 * Register (RVU_PF_BAR0) nix#_af_aq_door 1914 * 1915 * NIX AF Admin Queue Doorbell Register Software writes to this register 1916 * to enqueue entries to AQ. 1917 */ 1918union nixx_af_aq_door { 1919 u64 u; 1920 struct nixx_af_aq_door_s { 1921 u64 count : 16; 1922 u64 reserved_16_63 : 48; 1923 } s; 1924 /* struct nixx_af_aq_door_s cn; */ 1925}; 1926 1927static inline u64 NIXX_AF_AQ_DOOR(void) 1928 __attribute__ ((pure, always_inline)); 1929static inline u64 NIXX_AF_AQ_DOOR(void) 1930{ 1931 return 0x430; 1932} 1933 1934/** 1935 * Register (RVU_PF_BAR0) nix#_af_aq_status 1936 * 1937 * NIX AF Admin Queue Status Register 1938 */ 1939union nixx_af_aq_status { 1940 u64 u; 1941 struct nixx_af_aq_status_s { 1942 u64 reserved_0_3 : 4; 1943 u64 head_ptr : 20; 1944 u64 reserved_24_35 : 12; 1945 u64 tail_ptr : 20; 1946 u64 reserved_56_61 : 6; 1947 u64 aq_busy : 1; 1948 u64 aq_err : 1; 1949 } s; 1950 struct nixx_af_aq_status_cn { 1951 u64 reserved_0_3 : 4; 1952 u64 head_ptr : 20; 1953 u64 reserved_24_31 : 8; 1954 u64 reserved_32_35 : 4; 1955 u64 tail_ptr : 20; 1956 u64 reserved_56_61 : 6; 1957 u64 aq_busy : 1; 1958 u64 aq_err : 1; 1959 } cn; 1960}; 1961 1962static inline u64 NIXX_AF_AQ_STATUS(void) 1963 __attribute__ ((pure, always_inline)); 1964static inline u64 NIXX_AF_AQ_STATUS(void) 1965{ 1966 return 0x420; 1967} 1968 1969/** 1970 * Register (RVU_PF_BAR0) nix#_af_avg_delay 1971 * 1972 * NIX AF Queue Average Delay Register 1973 */ 1974union nixx_af_avg_delay { 1975 u64 u; 1976 struct nixx_af_avg_delay_s { 1977 u64 avg_dly : 19; 1978 u64 reserved_19_23 : 5; 1979 u64 avg_timer : 16; 1980 u64 reserved_40_63 : 24; 1981 } s; 1982 /* struct nixx_af_avg_delay_s cn; */ 1983}; 1984 1985static inline u64 NIXX_AF_AVG_DELAY(void) 1986 __attribute__ ((pure, always_inline)); 1987static inline u64 NIXX_AF_AVG_DELAY(void) 1988{ 1989 return 0xe0; 1990} 1991 1992/** 1993 * Register (RVU_PF_BAR0) nix#_af_bar2_alias# 1994 * 1995 * NIX Admin Function BAR2 Alias Registers These registers alias to the 1996 * NIX BAR2 registers for the PF and function selected by 1997 * NIX_AF_BAR2_SEL[PF_FUNC]. Internal: Not implemented. Placeholder for 1998 * bug33464. 1999 */ 2000union nixx_af_bar2_aliasx { 2001 u64 u; 2002 struct nixx_af_bar2_aliasx_s { 2003 u64 data : 64; 2004 } s; 2005 /* struct nixx_af_bar2_aliasx_s cn; */ 2006}; 2007 2008static inline u64 NIXX_AF_BAR2_ALIASX(u64 a) 2009 __attribute__ ((pure, always_inline)); 2010static inline u64 NIXX_AF_BAR2_ALIASX(u64 a) 2011{ 2012 return 0x9100000 + 8 * a; 2013} 2014 2015/** 2016 * Register (RVU_PF_BAR0) nix#_af_bar2_sel 2017 * 2018 * NIX Admin Function BAR2 Select Register This register configures BAR2 2019 * accesses from the NIX_AF_BAR2_ALIAS() registers in BAR0. Internal: Not 2020 * implemented. Placeholder for bug33464. 2021 */ 2022union nixx_af_bar2_sel { 2023 u64 u; 2024 struct nixx_af_bar2_sel_s { 2025 u64 alias_pf_func : 16; 2026 u64 alias_ena : 1; 2027 u64 reserved_17_63 : 47; 2028 } s; 2029 /* struct nixx_af_bar2_sel_s cn; */ 2030}; 2031 2032static inline u64 NIXX_AF_BAR2_SEL(void) 2033 __attribute__ ((pure, always_inline)); 2034static inline u64 NIXX_AF_BAR2_SEL(void) 2035{ 2036 return 0x9000000; 2037} 2038 2039/** 2040 * Register (RVU_PF_BAR0) nix#_af_blk_rst 2041 * 2042 * NIX AF Block Reset Register 2043 */ 2044union nixx_af_blk_rst { 2045 u64 u; 2046 struct nixx_af_blk_rst_s { 2047 u64 rst : 1; 2048 u64 reserved_1_62 : 62; 2049 u64 busy : 1; 2050 } s; 2051 /* struct nixx_af_blk_rst_s cn; */ 2052}; 2053 2054static inline u64 NIXX_AF_BLK_RST(void) 2055 __attribute__ ((pure, always_inline)); 2056static inline u64 NIXX_AF_BLK_RST(void) 2057{ 2058 return 0xb0; 2059} 2060 2061/** 2062 * Register (RVU_PF_BAR0) nix#_af_cfg 2063 * 2064 * NIX AF General Configuration Register 2065 */ 2066union nixx_af_cfg { 2067 u64 u; 2068 struct nixx_af_cfg_s { 2069 u64 force_cond_clk_en : 1; 2070 u64 force_rx_gbl_clk_en : 1; 2071 u64 force_rx_strm_clk_en : 1; 2072 u64 force_cqm_clk_en : 1; 2073 u64 force_seb_clk_en : 1; 2074 u64 force_sqm_clk_en : 1; 2075 u64 force_pse_clk_en : 1; 2076 u64 reserved_7 : 1; 2077 u64 af_be : 1; 2078 u64 calibrate_x2p : 1; 2079 u64 force_intf_clk_en : 1; 2080 u64 reserved_11_63 : 53; 2081 } s; 2082 /* struct nixx_af_cfg_s cn; */ 2083}; 2084 2085static inline u64 NIXX_AF_CFG(void) 2086 __attribute__ ((pure, always_inline)); 2087static inline u64 NIXX_AF_CFG(void) 2088{ 2089 return 0; 2090} 2091 2092/** 2093 * Register (RVU_PF_BAR0) nix#_af_cint_delay 2094 * 2095 * NIX AF Completion Interrupt Delay Register 2096 */ 2097union nixx_af_cint_delay { 2098 u64 u; 2099 struct nixx_af_cint_delay_s { 2100 u64 cint_dly : 10; 2101 u64 reserved_10_15 : 6; 2102 u64 cint_timer : 16; 2103 u64 reserved_32_63 : 32; 2104 } s; 2105 /* struct nixx_af_cint_delay_s cn; */ 2106}; 2107 2108static inline u64 NIXX_AF_CINT_DELAY(void) 2109 __attribute__ ((pure, always_inline)); 2110static inline u64 NIXX_AF_CINT_DELAY(void) 2111{ 2112 return 0xf0; 2113} 2114 2115/** 2116 * Register (RVU_PF_BAR0) nix#_af_cint_timer# 2117 * 2118 * NIX AF Completion Interrupt Timer Registers 2119 */ 2120union nixx_af_cint_timerx { 2121 u64 u; 2122 struct nixx_af_cint_timerx_s { 2123 u64 expir_time : 16; 2124 u64 cint : 7; 2125 u64 reserved_23 : 1; 2126 u64 lf : 8; 2127 u64 active : 1; 2128 u64 reserved_33_63 : 31; 2129 } s; 2130 /* struct nixx_af_cint_timerx_s cn; */ 2131}; 2132 2133static inline u64 NIXX_AF_CINT_TIMERX(u64 a) 2134 __attribute__ ((pure, always_inline)); 2135static inline u64 NIXX_AF_CINT_TIMERX(u64 a) 2136{ 2137 return 0x1a40 + 0x40000 * a; 2138} 2139 2140/** 2141 * Register (RVU_PF_BAR0) nix#_af_const 2142 * 2143 * NIX AF Constants Register This register contains constants for 2144 * software discovery. 2145 */ 2146union nixx_af_const { 2147 u64 u; 2148 struct nixx_af_const_s { 2149 u64 cgx_lmac_channels : 8; 2150 u64 cgx_lmacs : 4; 2151 u64 num_cgx : 4; 2152 u64 lbk_channels : 8; 2153 u64 num_lbk : 4; 2154 u64 num_sdp : 4; 2155 u64 reserved_32_47 : 16; 2156 u64 links : 8; 2157 u64 intfs : 4; 2158 u64 reserved_60_63 : 4; 2159 } s; 2160 /* struct nixx_af_const_s cn; */ 2161}; 2162 2163static inline u64 NIXX_AF_CONST(void) 2164 __attribute__ ((pure, always_inline)); 2165static inline u64 NIXX_AF_CONST(void) 2166{ 2167 return 0x20; 2168} 2169 2170/** 2171 * Register (RVU_PF_BAR0) nix#_af_const1 2172 * 2173 * NIX AF Constants 1 Register This register contains constants for 2174 * software discovery. 2175 */ 2176union nixx_af_const1 { 2177 u64 u; 2178 struct nixx_af_const1_s { 2179 u64 sdp_channels : 12; 2180 u64 rx_bpids : 12; 2181 u64 lf_tx_stats : 8; 2182 u64 lf_rx_stats : 8; 2183 u64 lso_format_fields : 8; 2184 u64 lso_formats : 8; 2185 u64 reserved_56_63 : 8; 2186 } s; 2187 /* struct nixx_af_const1_s cn; */ 2188}; 2189 2190static inline u64 NIXX_AF_CONST1(void) 2191 __attribute__ ((pure, always_inline)); 2192static inline u64 NIXX_AF_CONST1(void) 2193{ 2194 return 0x28; 2195} 2196 2197/** 2198 * Register (RVU_PF_BAR0) nix#_af_const2 2199 * 2200 * NIX AF Constants 2 Register This register contains constants for 2201 * software discovery. 2202 */ 2203union nixx_af_const2 { 2204 u64 u; 2205 struct nixx_af_const2_s { 2206 u64 lfs : 12; 2207 u64 qints : 12; 2208 u64 cints : 12; 2209 u64 reserved_36_63 : 28; 2210 } s; 2211 /* struct nixx_af_const2_s cn; */ 2212}; 2213 2214static inline u64 NIXX_AF_CONST2(void) 2215 __attribute__ ((pure, always_inline)); 2216static inline u64 NIXX_AF_CONST2(void) 2217{ 2218 return 0x30; 2219} 2220 2221/** 2222 * Register (RVU_PF_BAR0) nix#_af_const3 2223 * 2224 * NIX AF Constants 2 Register This register contains constants for 2225 * software discovery. 2226 */ 2227union nixx_af_const3 { 2228 u64 u; 2229 struct nixx_af_const3_s { 2230 u64 sq_ctx_log2bytes : 4; 2231 u64 rq_ctx_log2bytes : 4; 2232 u64 cq_ctx_log2bytes : 4; 2233 u64 rsse_log2bytes : 4; 2234 u64 mce_log2bytes : 4; 2235 u64 qint_log2bytes : 4; 2236 u64 cint_log2bytes : 4; 2237 u64 dyno_log2bytes : 4; 2238 u64 reserved_32_63 : 32; 2239 } s; 2240 /* struct nixx_af_const3_s cn; */ 2241}; 2242 2243static inline u64 NIXX_AF_CONST3(void) 2244 __attribute__ ((pure, always_inline)); 2245static inline u64 NIXX_AF_CONST3(void) 2246{ 2247 return 0x38; 2248} 2249 2250/** 2251 * Register (RVU_PF_BAR0) nix#_af_cq_const 2252 * 2253 * NIX AF CQ Constants Register This register contains constants for 2254 * software discovery. 2255 */ 2256union nixx_af_cq_const { 2257 u64 u; 2258 struct nixx_af_cq_const_s { 2259 u64 queues_per_lf : 24; 2260 u64 reserved_24_63 : 40; 2261 } s; 2262 /* struct nixx_af_cq_const_s cn; */ 2263}; 2264 2265static inline u64 NIXX_AF_CQ_CONST(void) 2266 __attribute__ ((pure, always_inline)); 2267static inline u64 NIXX_AF_CQ_CONST(void) 2268{ 2269 return 0x48; 2270} 2271 2272/** 2273 * Register (RVU_PF_BAR0) nix#_af_cqm_bp_test 2274 * 2275 * INTERNAL: NIX AF CQM Backpressure Test Registers 2276 */ 2277union nixx_af_cqm_bp_test { 2278 u64 u; 2279 struct nixx_af_cqm_bp_test_s { 2280 u64 lfsr_freq : 12; 2281 u64 reserved_12_15 : 4; 2282 u64 bp_cfg : 24; 2283 u64 enable : 12; 2284 u64 reserved_52_63 : 12; 2285 } s; 2286 /* struct nixx_af_cqm_bp_test_s cn; */ 2287}; 2288 2289static inline u64 NIXX_AF_CQM_BP_TEST(void) 2290 __attribute__ ((pure, always_inline)); 2291static inline u64 NIXX_AF_CQM_BP_TEST(void) 2292{ 2293 return 0x48c0; 2294} 2295 2296/** 2297 * Register (RVU_PF_BAR0) nix#_af_cqm_eco 2298 * 2299 * INTERNAL: AF CQM ECO Register 2300 */ 2301union nixx_af_cqm_eco { 2302 u64 u; 2303 struct nixx_af_cqm_eco_s { 2304 u64 eco_rw : 64; 2305 } s; 2306 /* struct nixx_af_cqm_eco_s cn; */ 2307}; 2308 2309static inline u64 NIXX_AF_CQM_ECO(void) 2310 __attribute__ ((pure, always_inline)); 2311static inline u64 NIXX_AF_CQM_ECO(void) 2312{ 2313 return 0x590; 2314} 2315 2316/** 2317 * Register (RVU_PF_BAR0) nix#_af_csi_eco 2318 * 2319 * INTERNAL: AF CSI ECO Register 2320 */ 2321union nixx_af_csi_eco { 2322 u64 u; 2323 struct nixx_af_csi_eco_s { 2324 u64 eco_rw : 64; 2325 } s; 2326 /* struct nixx_af_csi_eco_s cn; */ 2327}; 2328 2329static inline u64 NIXX_AF_CSI_ECO(void) 2330 __attribute__ ((pure, always_inline)); 2331static inline u64 NIXX_AF_CSI_ECO(void) 2332{ 2333 return 0x580; 2334} 2335 2336/** 2337 * Register (RVU_PF_BAR0) nix#_af_err_int 2338 * 2339 * NIX Admin Function Error Interrupt Register 2340 */ 2341union nixx_af_err_int { 2342 u64 u; 2343 struct nixx_af_err_int_s { 2344 u64 rx_mcast_data_fault : 1; 2345 u64 rx_mirror_data_fault : 1; 2346 u64 rx_mcast_wqe_fault : 1; 2347 u64 rx_mirror_wqe_fault : 1; 2348 u64 rx_mce_fault : 1; 2349 u64 rx_mce_list_err : 1; 2350 u64 rx_unmapped_pf_func : 1; 2351 u64 reserved_7_11 : 5; 2352 u64 aq_door_err : 1; 2353 u64 aq_res_fault : 1; 2354 u64 aq_inst_fault : 1; 2355 u64 reserved_15_63 : 49; 2356 } s; 2357 /* struct nixx_af_err_int_s cn; */ 2358}; 2359 2360static inline u64 NIXX_AF_ERR_INT(void) 2361 __attribute__ ((pure, always_inline)); 2362static inline u64 NIXX_AF_ERR_INT(void) 2363{ 2364 return 0x180; 2365} 2366 2367/** 2368 * Register (RVU_PF_BAR0) nix#_af_err_int_ena_w1c 2369 * 2370 * NIX Admin Function Error Interrupt Enable Clear Register This register 2371 * clears interrupt enable bits. 2372 */ 2373union nixx_af_err_int_ena_w1c { 2374 u64 u; 2375 struct nixx_af_err_int_ena_w1c_s { 2376 u64 rx_mcast_data_fault : 1; 2377 u64 rx_mirror_data_fault : 1; 2378 u64 rx_mcast_wqe_fault : 1; 2379 u64 rx_mirror_wqe_fault : 1; 2380 u64 rx_mce_fault : 1; 2381 u64 rx_mce_list_err : 1; 2382 u64 rx_unmapped_pf_func : 1; 2383 u64 reserved_7_11 : 5; 2384 u64 aq_door_err : 1; 2385 u64 aq_res_fault : 1; 2386 u64 aq_inst_fault : 1; 2387 u64 reserved_15_63 : 49; 2388 } s; 2389 /* struct nixx_af_err_int_ena_w1c_s cn; */ 2390}; 2391 2392static inline u64 NIXX_AF_ERR_INT_ENA_W1C(void) 2393 __attribute__ ((pure, always_inline)); 2394static inline u64 NIXX_AF_ERR_INT_ENA_W1C(void) 2395{ 2396 return 0x198; 2397} 2398 2399/** 2400 * Register (RVU_PF_BAR0) nix#_af_err_int_ena_w1s 2401 * 2402 * NIX Admin Function Error Interrupt Enable Set Register This register 2403 * sets interrupt enable bits. 2404 */ 2405union nixx_af_err_int_ena_w1s { 2406 u64 u; 2407 struct nixx_af_err_int_ena_w1s_s { 2408 u64 rx_mcast_data_fault : 1; 2409 u64 rx_mirror_data_fault : 1; 2410 u64 rx_mcast_wqe_fault : 1; 2411 u64 rx_mirror_wqe_fault : 1; 2412 u64 rx_mce_fault : 1; 2413 u64 rx_mce_list_err : 1; 2414 u64 rx_unmapped_pf_func : 1; 2415 u64 reserved_7_11 : 5; 2416 u64 aq_door_err : 1; 2417 u64 aq_res_fault : 1; 2418 u64 aq_inst_fault : 1; 2419 u64 reserved_15_63 : 49; 2420 } s; 2421 /* struct nixx_af_err_int_ena_w1s_s cn; */ 2422}; 2423 2424static inline u64 NIXX_AF_ERR_INT_ENA_W1S(void) 2425 __attribute__ ((pure, always_inline)); 2426static inline u64 NIXX_AF_ERR_INT_ENA_W1S(void) 2427{ 2428 return 0x190; 2429} 2430 2431/** 2432 * Register (RVU_PF_BAR0) nix#_af_err_int_w1s 2433 * 2434 * NIX Admin Function Error Interrupt Set Register This register sets 2435 * interrupt bits. 2436 */ 2437union nixx_af_err_int_w1s { 2438 u64 u; 2439 struct nixx_af_err_int_w1s_s { 2440 u64 rx_mcast_data_fault : 1; 2441 u64 rx_mirror_data_fault : 1; 2442 u64 rx_mcast_wqe_fault : 1; 2443 u64 rx_mirror_wqe_fault : 1; 2444 u64 rx_mce_fault : 1; 2445 u64 rx_mce_list_err : 1; 2446 u64 rx_unmapped_pf_func : 1; 2447 u64 reserved_7_11 : 5; 2448 u64 aq_door_err : 1; 2449 u64 aq_res_fault : 1; 2450 u64 aq_inst_fault : 1; 2451 u64 reserved_15_63 : 49; 2452 } s; 2453 /* struct nixx_af_err_int_w1s_s cn; */ 2454}; 2455 2456static inline u64 NIXX_AF_ERR_INT_W1S(void) 2457 __attribute__ ((pure, always_inline)); 2458static inline u64 NIXX_AF_ERR_INT_W1S(void) 2459{ 2460 return 0x188; 2461} 2462 2463/** 2464 * Register (RVU_PF_BAR0) nix#_af_expr_tx_fifo_status 2465 * 2466 * INTERNAL: NIX AF Express Transmit FIFO Status Register Internal: 2467 * 802.3br frame preemption/express path is defeatured. Old definition: 2468 * Status of FIFO which transmits express packets to CGX and LBK. 2469 */ 2470union nixx_af_expr_tx_fifo_status { 2471 u64 u; 2472 struct nixx_af_expr_tx_fifo_status_s { 2473 u64 count : 12; 2474 u64 reserved_12_63 : 52; 2475 } s; 2476 /* struct nixx_af_expr_tx_fifo_status_s cn; */ 2477}; 2478 2479static inline u64 NIXX_AF_EXPR_TX_FIFO_STATUS(void) 2480 __attribute__ ((pure, always_inline)); 2481static inline u64 NIXX_AF_EXPR_TX_FIFO_STATUS(void) 2482{ 2483 return 0x640; 2484} 2485 2486/** 2487 * Register (RVU_PF_BAR0) nix#_af_gen_int 2488 * 2489 * NIX AF General Interrupt Register 2490 */ 2491union nixx_af_gen_int { 2492 u64 u; 2493 struct nixx_af_gen_int_s { 2494 u64 rx_mcast_drop : 1; 2495 u64 rx_mirror_drop : 1; 2496 u64 reserved_2 : 1; 2497 u64 tl1_drain : 1; 2498 u64 smq_flush_done : 1; 2499 u64 reserved_5_63 : 59; 2500 } s; 2501 /* struct nixx_af_gen_int_s cn; */ 2502}; 2503 2504static inline u64 NIXX_AF_GEN_INT(void) 2505 __attribute__ ((pure, always_inline)); 2506static inline u64 NIXX_AF_GEN_INT(void) 2507{ 2508 return 0x160; 2509} 2510 2511/** 2512 * Register (RVU_PF_BAR0) nix#_af_gen_int_ena_w1c 2513 * 2514 * NIX AF General Interrupt Enable Clear Register This register clears 2515 * interrupt enable bits. 2516 */ 2517union nixx_af_gen_int_ena_w1c { 2518 u64 u; 2519 struct nixx_af_gen_int_ena_w1c_s { 2520 u64 rx_mcast_drop : 1; 2521 u64 rx_mirror_drop : 1; 2522 u64 reserved_2 : 1; 2523 u64 tl1_drain : 1; 2524 u64 smq_flush_done : 1; 2525 u64 reserved_5_63 : 59; 2526 } s; 2527 /* struct nixx_af_gen_int_ena_w1c_s cn; */ 2528}; 2529 2530static inline u64 NIXX_AF_GEN_INT_ENA_W1C(void) 2531 __attribute__ ((pure, always_inline)); 2532static inline u64 NIXX_AF_GEN_INT_ENA_W1C(void) 2533{ 2534 return 0x178; 2535} 2536 2537/** 2538 * Register (RVU_PF_BAR0) nix#_af_gen_int_ena_w1s 2539 * 2540 * NIX AF General Interrupt Enable Set Register This register sets 2541 * interrupt enable bits. 2542 */ 2543union nixx_af_gen_int_ena_w1s { 2544 u64 u; 2545 struct nixx_af_gen_int_ena_w1s_s { 2546 u64 rx_mcast_drop : 1; 2547 u64 rx_mirror_drop : 1; 2548 u64 reserved_2 : 1; 2549 u64 tl1_drain : 1; 2550 u64 smq_flush_done : 1; 2551 u64 reserved_5_63 : 59; 2552 } s; 2553 /* struct nixx_af_gen_int_ena_w1s_s cn; */ 2554}; 2555 2556static inline u64 NIXX_AF_GEN_INT_ENA_W1S(void) 2557 __attribute__ ((pure, always_inline)); 2558static inline u64 NIXX_AF_GEN_INT_ENA_W1S(void) 2559{ 2560 return 0x170; 2561} 2562 2563/** 2564 * Register (RVU_PF_BAR0) nix#_af_gen_int_w1s 2565 * 2566 * NIX AF General Interrupt Set Register This register sets interrupt 2567 * bits. 2568 */ 2569union nixx_af_gen_int_w1s { 2570 u64 u; 2571 struct nixx_af_gen_int_w1s_s { 2572 u64 rx_mcast_drop : 1; 2573 u64 rx_mirror_drop : 1; 2574 u64 reserved_2 : 1; 2575 u64 tl1_drain : 1; 2576 u64 smq_flush_done : 1; 2577 u64 reserved_5_63 : 59; 2578 } s; 2579 /* struct nixx_af_gen_int_w1s_s cn; */ 2580}; 2581 2582static inline u64 NIXX_AF_GEN_INT_W1S(void) 2583 __attribute__ ((pure, always_inline)); 2584static inline u64 NIXX_AF_GEN_INT_W1S(void) 2585{ 2586 return 0x168; 2587} 2588 2589/** 2590 * Register (RVU_PF_BAR0) nix#_af_lf#_cfg 2591 * 2592 * NIX AF Local Function Configuration Registers 2593 */ 2594union nixx_af_lfx_cfg { 2595 u64 u; 2596 struct nixx_af_lfx_cfg_s { 2597 u64 npa_pf_func : 16; 2598 u64 sso_pf_func : 16; 2599 u64 be : 1; 2600 u64 xqe_size : 2; 2601 u64 reserved_35_63 : 29; 2602 } s; 2603 /* struct nixx_af_lfx_cfg_s cn; */ 2604}; 2605 2606static inline u64 NIXX_AF_LFX_CFG(u64 a) 2607 __attribute__ ((pure, always_inline)); 2608static inline u64 NIXX_AF_LFX_CFG(u64 a) 2609{ 2610 return 0x4000 + 0x20000 * a; 2611} 2612 2613/** 2614 * Register (RVU_PF_BAR0) nix#_af_lf#_cints_base 2615 * 2616 * NIX AF Local Function Completion Interrupts Base Address Registers 2617 * This register specifies the base AF IOVA of LF's completion interrupt 2618 * context table in NDC/LLC/DRAM. The table consists of 2619 * NIX_AF_CONST2[CINTS] contiguous NIX_CINT_HW_S structures. After 2620 * writing to this register, software should read it back to ensure that 2621 * the write has completed before accessing any NIX_LF_CINT()_* 2622 * registers. 2623 */ 2624union nixx_af_lfx_cints_base { 2625 u64 u; 2626 struct nixx_af_lfx_cints_base_s { 2627 u64 reserved_0_6 : 7; 2628 u64 addr : 46; 2629 u64 reserved_53_63 : 11; 2630 } s; 2631 /* struct nixx_af_lfx_cints_base_s cn; */ 2632}; 2633 2634static inline u64 NIXX_AF_LFX_CINTS_BASE(u64 a) 2635 __attribute__ ((pure, always_inline)); 2636static inline u64 NIXX_AF_LFX_CINTS_BASE(u64 a) 2637{ 2638 return 0x4130 + 0x20000 * a; 2639} 2640 2641/** 2642 * Register (RVU_PF_BAR0) nix#_af_lf#_cints_cfg 2643 * 2644 * NIX AF Local Function Completion Interrupts Configuration Registers 2645 * This register controls access to the LF's completion interrupt context 2646 * table in NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[CINTS] 2647 * contiguous NIX_CINT_HW_S structures. The size of each structure is 1 2648 * \<\< NIX_AF_CONST3[CINT_LOG2BYTES]. After writing to this register, 2649 * software should read it back to ensure that the write has completed 2650 * before accessing any NIX_LF_CINT()_* registers. 2651 */ 2652union nixx_af_lfx_cints_cfg { 2653 u64 u; 2654 struct nixx_af_lfx_cints_cfg_s { 2655 u64 reserved_0_19 : 20; 2656 u64 way_mask : 16; 2657 u64 caching : 1; 2658 u64 reserved_37_63 : 27; 2659 } s; 2660 /* struct nixx_af_lfx_cints_cfg_s cn; */ 2661}; 2662 2663static inline u64 NIXX_AF_LFX_CINTS_CFG(u64 a) 2664 __attribute__ ((pure, always_inline)); 2665static inline u64 NIXX_AF_LFX_CINTS_CFG(u64 a) 2666{ 2667 return 0x4120 + 0x20000 * a; 2668} 2669 2670/** 2671 * Register (RVU_PF_BAR0) nix#_af_lf#_cqs_base 2672 * 2673 * NIX AF Local Function Completion Queues Base Address Register This 2674 * register specifies the base AF IOVA of the LF's CQ context table. The 2675 * table consists of NIX_AF_LF()_CQS_CFG[MAX_QUEUESM1]+1 contiguous 2676 * NIX_CQ_CTX_S structures. 2677 */ 2678union nixx_af_lfx_cqs_base { 2679 u64 u; 2680 struct nixx_af_lfx_cqs_base_s { 2681 u64 reserved_0_6 : 7; 2682 u64 addr : 46; 2683 u64 reserved_53_63 : 11; 2684 } s; 2685 /* struct nixx_af_lfx_cqs_base_s cn; */ 2686}; 2687 2688static inline u64 NIXX_AF_LFX_CQS_BASE(u64 a) 2689 __attribute__ ((pure, always_inline)); 2690static inline u64 NIXX_AF_LFX_CQS_BASE(u64 a) 2691{ 2692 return 0x4070 + 0x20000 * a; 2693} 2694 2695/** 2696 * Register (RVU_PF_BAR0) nix#_af_lf#_cqs_cfg 2697 * 2698 * NIX AF Local Function Completion Queues Configuration Register This 2699 * register configures completion queues in the LF. 2700 */ 2701union nixx_af_lfx_cqs_cfg { 2702 u64 u; 2703 struct nixx_af_lfx_cqs_cfg_s { 2704 u64 max_queuesm1 : 20; 2705 u64 way_mask : 16; 2706 u64 caching : 1; 2707 u64 reserved_37_63 : 27; 2708 } s; 2709 /* struct nixx_af_lfx_cqs_cfg_s cn; */ 2710}; 2711 2712static inline u64 NIXX_AF_LFX_CQS_CFG(u64 a) 2713 __attribute__ ((pure, always_inline)); 2714static inline u64 NIXX_AF_LFX_CQS_CFG(u64 a) 2715{ 2716 return 0x4060 + 0x20000 * a; 2717} 2718 2719/** 2720 * Register (RVU_PF_BAR0) nix#_af_lf#_lock# 2721 * 2722 * NIX AF Local Function Lockdown Registers Internal: The NIX lockdown 2723 * depth of 32 bytes is shallow compared to 96 bytes for NIC and meant 2724 * for outer MAC and/or VLAN (optionally preceded by a small number of 2725 * skip bytes). NPC's MCAM can be used for deeper protocol-aware 2726 * lockdown. 2727 */ 2728union nixx_af_lfx_lockx { 2729 u64 u; 2730 struct nixx_af_lfx_lockx_s { 2731 u64 data : 32; 2732 u64 bit_ena : 32; 2733 } s; 2734 /* struct nixx_af_lfx_lockx_s cn; */ 2735}; 2736 2737static inline u64 NIXX_AF_LFX_LOCKX(u64 a, u64 b) 2738 __attribute__ ((pure, always_inline)); 2739static inline u64 NIXX_AF_LFX_LOCKX(u64 a, u64 b) 2740{ 2741 return 0x4300 + 0x20000 * a + 8 * b; 2742} 2743 2744/** 2745 * Register (RVU_PF_BAR0) nix#_af_lf#_qints_base 2746 * 2747 * NIX AF Local Function Queue Interrupts Base Address Registers This 2748 * register specifies the base AF IOVA of LF's queue interrupt context 2749 * table in NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[QINTS] 2750 * contiguous NIX_QINT_HW_S structures. After writing to this register, 2751 * software should read it back to ensure that the write has completed 2752 * before accessing any NIX_LF_QINT()_* registers. 2753 */ 2754union nixx_af_lfx_qints_base { 2755 u64 u; 2756 struct nixx_af_lfx_qints_base_s { 2757 u64 reserved_0_6 : 7; 2758 u64 addr : 46; 2759 u64 reserved_53_63 : 11; 2760 } s; 2761 /* struct nixx_af_lfx_qints_base_s cn; */ 2762}; 2763 2764static inline u64 NIXX_AF_LFX_QINTS_BASE(u64 a) 2765 __attribute__ ((pure, always_inline)); 2766static inline u64 NIXX_AF_LFX_QINTS_BASE(u64 a) 2767{ 2768 return 0x4110 + 0x20000 * a; 2769} 2770 2771/** 2772 * Register (RVU_PF_BAR0) nix#_af_lf#_qints_cfg 2773 * 2774 * NIX AF Local Function Queue Interrupts Configuration Registers This 2775 * register controls access to the LF's queue interrupt context table in 2776 * NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[QINTS] contiguous 2777 * NIX_QINT_HW_S structures. The size of each structure is 1 \<\< 2778 * NIX_AF_CONST3[QINT_LOG2BYTES]. After writing to this register, 2779 * software should read it back to ensure that the write has completed 2780 * before accessing any NIX_LF_QINT()_* registers. 2781 */ 2782union nixx_af_lfx_qints_cfg { 2783 u64 u; 2784 struct nixx_af_lfx_qints_cfg_s { 2785 u64 reserved_0_19 : 20; 2786 u64 way_mask : 16; 2787 u64 caching : 1; 2788 u64 reserved_37_63 : 27; 2789 } s; 2790 /* struct nixx_af_lfx_qints_cfg_s cn; */ 2791}; 2792 2793static inline u64 NIXX_AF_LFX_QINTS_CFG(u64 a) 2794 __attribute__ ((pure, always_inline)); 2795static inline u64 NIXX_AF_LFX_QINTS_CFG(u64 a) 2796{ 2797 return 0x4100 + 0x20000 * a; 2798} 2799 2800/** 2801 * Register (RVU_PF_BAR0) nix#_af_lf#_rqs_base 2802 * 2803 * NIX AF Local Function Receive Queues Base Address Register This 2804 * register specifies the base AF IOVA of the LF's RQ context table. The 2805 * table consists of NIX_AF_LF()_RQS_CFG[MAX_QUEUESM1]+1 contiguous 2806 * NIX_RQ_CTX_S structures. 2807 */ 2808union nixx_af_lfx_rqs_base { 2809 u64 u; 2810 struct nixx_af_lfx_rqs_base_s { 2811 u64 reserved_0_6 : 7; 2812 u64 addr : 46; 2813 u64 reserved_53_63 : 11; 2814 } s; 2815 /* struct nixx_af_lfx_rqs_base_s cn; */ 2816}; 2817 2818static inline u64 NIXX_AF_LFX_RQS_BASE(u64 a) 2819 __attribute__ ((pure, always_inline)); 2820static inline u64 NIXX_AF_LFX_RQS_BASE(u64 a) 2821{ 2822 return 0x4050 + 0x20000 * a; 2823} 2824 2825/** 2826 * Register (RVU_PF_BAR0) nix#_af_lf#_rqs_cfg 2827 * 2828 * NIX AF Local Function Receive Queues Configuration Register This 2829 * register configures receive queues in the LF. 2830 */ 2831union nixx_af_lfx_rqs_cfg { 2832 u64 u; 2833 struct nixx_af_lfx_rqs_cfg_s { 2834 u64 max_queuesm1 : 20; 2835 u64 way_mask : 16; 2836 u64 caching : 1; 2837 u64 reserved_37_63 : 27; 2838 } s; 2839 /* struct nixx_af_lfx_rqs_cfg_s cn; */ 2840}; 2841 2842static inline u64 NIXX_AF_LFX_RQS_CFG(u64 a) 2843 __attribute__ ((pure, always_inline)); 2844static inline u64 NIXX_AF_LFX_RQS_CFG(u64 a) 2845{ 2846 return 0x4040 + 0x20000 * a; 2847} 2848 2849/** 2850 * Register (RVU_PF_BAR0) nix#_af_lf#_rss_base 2851 * 2852 * NIX AF Local Function Receive Size Scaling Table Base Address Register 2853 * This register specifies the base AF IOVA of the RSS table per LF. The 2854 * table is present when NIX_AF_LF()_RSS_CFG[ENA] is set and consists of 2855 * 1 \<\< (NIX_AF_LF()_RSS_CFG[SIZE] + 8) contiguous NIX_RSSE_S 2856 * structures, where the size of each structure is 1 \<\< 2857 * NIX_AF_CONST3[RSSE_LOG2BYTES]. See NIX_AF_LF()_RSS_GRP(). 2858 */ 2859union nixx_af_lfx_rss_base { 2860 u64 u; 2861 struct nixx_af_lfx_rss_base_s { 2862 u64 reserved_0_6 : 7; 2863 u64 addr : 46; 2864 u64 reserved_53_63 : 11; 2865 } s; 2866 /* struct nixx_af_lfx_rss_base_s cn; */ 2867}; 2868 2869static inline u64 NIXX_AF_LFX_RSS_BASE(u64 a) 2870 __attribute__ ((pure, always_inline)); 2871static inline u64 NIXX_AF_LFX_RSS_BASE(u64 a) 2872{ 2873 return 0x40d0 + 0x20000 * a; 2874} 2875 2876/** 2877 * Register (RVU_PF_BAR0) nix#_af_lf#_rss_cfg 2878 * 2879 * NIX AF Local Function Receive Size Scaling Table Configuration 2880 * Register See NIX_AF_LF()_RSS_BASE and NIX_AF_LF()_RSS_GRP(). 2881 */ 2882union nixx_af_lfx_rss_cfg { 2883 u64 u; 2884 struct nixx_af_lfx_rss_cfg_s { 2885 u64 size : 4; 2886 u64 ena : 1; 2887 u64 adder_is_tag_lsb : 1; 2888 u64 reserved_6_19 : 14; 2889 u64 way_mask : 16; 2890 u64 caching : 1; 2891 u64 reserved_37_63 : 27; 2892 } s; 2893 struct nixx_af_lfx_rss_cfg_cn96xxp1 { 2894 u64 size : 4; 2895 u64 ena : 1; 2896 u64 reserved_5_19 : 15; 2897 u64 way_mask : 16; 2898 u64 caching : 1; 2899 u64 reserved_37_63 : 27; 2900 } cn96xxp1; 2901 /* struct nixx_af_lfx_rss_cfg_s cn96xxp3; */ 2902 /* struct nixx_af_lfx_rss_cfg_cn96xxp1 cnf95xx; */ 2903}; 2904 2905static inline u64 NIXX_AF_LFX_RSS_CFG(u64 a) 2906 __attribute__ ((pure, always_inline)); 2907static inline u64 NIXX_AF_LFX_RSS_CFG(u64 a) 2908{ 2909 return 0x40c0 + 0x20000 * a; 2910} 2911 2912/** 2913 * Register (RVU_PF_BAR0) nix#_af_lf#_rss_grp# 2914 * 2915 * NIX AF Local Function Receive Side Scaling Group Registers A receive 2916 * packet targets a LF's RSS group when its NIX_RX_ACTION_S[OP] = 2917 * NIX_RX_ACTIONOP_E::RSS, or its target multicast list has an entry with 2918 * NIX_RX_MCE_S[OP] = NIX_RX_MCOP_E::RSS. The RSS group index (this 2919 * register's last index) is NIX_RX_ACTION_S[INDEX] or 2920 * NIX_RX_MCE_S[INDEX]. The RSS computation is as follows: * The 2921 * packet's flow_tag (see NIX_LF_RX_SECRET()) and RSS group are used to 2922 * select a NIX_RSSE_S entry in the LF's RSS table (see [SIZEM1]). * 2923 * NIX_RSSE_S selects the packet's destination RQ. 2924 */ 2925union nixx_af_lfx_rss_grpx { 2926 u64 u; 2927 struct nixx_af_lfx_rss_grpx_s { 2928 u64 offset : 11; 2929 u64 reserved_11_15 : 5; 2930 u64 sizem1 : 3; 2931 u64 reserved_19_63 : 45; 2932 } s; 2933 /* struct nixx_af_lfx_rss_grpx_s cn; */ 2934}; 2935 2936static inline u64 NIXX_AF_LFX_RSS_GRPX(u64 a, u64 b) 2937 __attribute__ ((pure, always_inline)); 2938static inline u64 NIXX_AF_LFX_RSS_GRPX(u64 a, u64 b) 2939{ 2940 return 0x4600 + 0x20000 * a + 8 * b; 2941} 2942 2943/** 2944 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_cfg 2945 * 2946 * NIX AF Local Function Receive Configuration Register 2947 */ 2948union nixx_af_lfx_rx_cfg { 2949 u64 u; 2950 struct nixx_af_lfx_rx_cfg_s { 2951 u64 reserved_0_31 : 32; 2952 u64 drop_re : 1; 2953 u64 lenerr_en : 1; 2954 u64 ip6_udp_opt : 1; 2955 u64 dis_apad : 1; 2956 u64 csum_il4 : 1; 2957 u64 csum_ol4 : 1; 2958 u64 len_il4 : 1; 2959 u64 len_il3 : 1; 2960 u64 len_ol4 : 1; 2961 u64 len_ol3 : 1; 2962 u64 reserved_42_63 : 22; 2963 } s; 2964 struct nixx_af_lfx_rx_cfg_cn96xxp1 { 2965 u64 reserved_0_31 : 32; 2966 u64 reserved_32 : 1; 2967 u64 lenerr_en : 1; 2968 u64 ip6_udp_opt : 1; 2969 u64 dis_apad : 1; 2970 u64 csum_il4 : 1; 2971 u64 csum_ol4 : 1; 2972 u64 len_il4 : 1; 2973 u64 len_il3 : 1; 2974 u64 len_ol4 : 1; 2975 u64 len_ol3 : 1; 2976 u64 reserved_42_63 : 22; 2977 } cn96xxp1; 2978 /* struct nixx_af_lfx_rx_cfg_s cn96xxp3; */ 2979 /* struct nixx_af_lfx_rx_cfg_s cnf95xx; */ 2980}; 2981 2982static inline u64 NIXX_AF_LFX_RX_CFG(u64 a) 2983 __attribute__ ((pure, always_inline)); 2984static inline u64 NIXX_AF_LFX_RX_CFG(u64 a) 2985{ 2986 return 0x40a0 + 0x20000 * a; 2987} 2988 2989/** 2990 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_cfg0 2991 * 2992 * INTERNAL: NIX AF LF Receive IPSEC Configuration Registers Internal: 2993 * Not used; no IPSEC fast-path. 2994 */ 2995union nixx_af_lfx_rx_ipsec_cfg0 { 2996 u64 u; 2997 struct nixx_af_lfx_rx_ipsec_cfg0_s { 2998 u64 lenm1_max : 14; 2999 u64 reserved_14_15 : 2; 3000 u64 sa_pow2_size : 4; 3001 u64 tag_const : 24; 3002 u64 tt : 2; 3003 u64 defcpt : 1; 3004 u64 hshcpt : 1; 3005 u64 reserved_48_63 : 16; 3006 } s; 3007 /* struct nixx_af_lfx_rx_ipsec_cfg0_s cn; */ 3008}; 3009 3010static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG0(u64 a) 3011 __attribute__ ((pure, always_inline)); 3012static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG0(u64 a) 3013{ 3014 return 0x4140 + 0x20000 * a; 3015} 3016 3017/** 3018 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_cfg1 3019 * 3020 * INTERNAL: NIX AF LF Receive IPSEC Security Association Configuration 3021 * Register Internal: Not used; no IPSEC fast-path. 3022 */ 3023union nixx_af_lfx_rx_ipsec_cfg1 { 3024 u64 u; 3025 struct nixx_af_lfx_rx_ipsec_cfg1_s { 3026 u64 sa_idx_max : 32; 3027 u64 sa_idx_w : 5; 3028 u64 reserved_37_63 : 27; 3029 } s; 3030 /* struct nixx_af_lfx_rx_ipsec_cfg1_s cn; */ 3031}; 3032 3033static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG1(u64 a) 3034 __attribute__ ((pure, always_inline)); 3035static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG1(u64 a) 3036{ 3037 return 0x4148 + 0x20000 * a; 3038} 3039 3040/** 3041 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_dyno_base 3042 * 3043 * INTERNAL: NIX AF LF Receive IPSEC Dynamic Ordering Base Address 3044 * Registers Internal: Not used; no IPSEC fast-path. 3045 */ 3046union nixx_af_lfx_rx_ipsec_dyno_base { 3047 u64 u; 3048 struct nixx_af_lfx_rx_ipsec_dyno_base_s { 3049 u64 reserved_0_6 : 7; 3050 u64 addr : 46; 3051 u64 reserved_53_63 : 11; 3052 } s; 3053 /* struct nixx_af_lfx_rx_ipsec_dyno_base_s cn; */ 3054}; 3055 3056static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_BASE(u64 a) 3057 __attribute__ ((pure, always_inline)); 3058static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_BASE(u64 a) 3059{ 3060 return 0x4158 + 0x20000 * a; 3061} 3062 3063/** 3064 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_dyno_cfg 3065 * 3066 * INTERNAL: NIX AF LF Receive IPSEC Dynamic Ordering Base Address 3067 * Registers Internal: Not used; no IPSEC fast-path. 3068 */ 3069union nixx_af_lfx_rx_ipsec_dyno_cfg { 3070 u64 u; 3071 struct nixx_af_lfx_rx_ipsec_dyno_cfg_s { 3072 u64 dyno_idx_w : 4; 3073 u64 dyno_ena : 1; 3074 u64 reserved_5_19 : 15; 3075 u64 way_mask : 16; 3076 u64 caching : 1; 3077 u64 reserved_37_63 : 27; 3078 } s; 3079 /* struct nixx_af_lfx_rx_ipsec_dyno_cfg_s cn; */ 3080}; 3081 3082static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_CFG(u64 a) 3083 __attribute__ ((pure, always_inline)); 3084static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_CFG(u64 a) 3085{ 3086 return 0x4150 + 0x20000 * a; 3087} 3088 3089/** 3090 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_sa_base 3091 * 3092 * INTERNAL: NIX AF LF Receive IPSEC Security Association Base Address 3093 * Register Internal: Not used; no IPSEC fast-path. 3094 */ 3095union nixx_af_lfx_rx_ipsec_sa_base { 3096 u64 u; 3097 struct nixx_af_lfx_rx_ipsec_sa_base_s { 3098 u64 reserved_0_6 : 7; 3099 u64 addr : 46; 3100 u64 reserved_53_63 : 11; 3101 } s; 3102 /* struct nixx_af_lfx_rx_ipsec_sa_base_s cn; */ 3103}; 3104 3105static inline u64 NIXX_AF_LFX_RX_IPSEC_SA_BASE(u64 a) 3106 __attribute__ ((pure, always_inline)); 3107static inline u64 NIXX_AF_LFX_RX_IPSEC_SA_BASE(u64 a) 3108{ 3109 return 0x4170 + 0x20000 * a; 3110} 3111 3112/** 3113 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_stat# 3114 * 3115 * NIX AF Local Function Receive Statistics Registers The last dimension 3116 * indicates which statistic, and is enumerated by NIX_STAT_LF_RX_E. 3117 */ 3118union nixx_af_lfx_rx_statx { 3119 u64 u; 3120 struct nixx_af_lfx_rx_statx_s { 3121 u64 stat : 48; 3122 u64 reserved_48_63 : 16; 3123 } s; 3124 /* struct nixx_af_lfx_rx_statx_s cn; */ 3125}; 3126 3127static inline u64 NIXX_AF_LFX_RX_STATX(u64 a, u64 b) 3128 __attribute__ ((pure, always_inline)); 3129static inline u64 NIXX_AF_LFX_RX_STATX(u64 a, u64 b) 3130{ 3131 return 0x4500 + 0x20000 * a + 8 * b; 3132} 3133 3134/** 3135 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_vtag_type# 3136 * 3137 * NIX AF Local Function Receive Vtag Type Registers These registers 3138 * specify optional Vtag (e.g. VLAN, E-TAG) actions for received packets. 3139 * Indexed by NIX_RX_VTAG_ACTION_S[VTAG*_TYPE]. 3140 */ 3141union nixx_af_lfx_rx_vtag_typex { 3142 u64 u; 3143 struct nixx_af_lfx_rx_vtag_typex_s { 3144 u64 size : 1; 3145 u64 reserved_1_3 : 3; 3146 u64 strip : 1; 3147 u64 capture : 1; 3148 u64 reserved_6_63 : 58; 3149 } s; 3150 /* struct nixx_af_lfx_rx_vtag_typex_s cn; */ 3151}; 3152 3153static inline u64 NIXX_AF_LFX_RX_VTAG_TYPEX(u64 a, u64 b) 3154 __attribute__ ((pure, always_inline)); 3155static inline u64 NIXX_AF_LFX_RX_VTAG_TYPEX(u64 a, u64 b) 3156{ 3157 return 0x4200 + 0x20000 * a + 8 * b; 3158} 3159 3160/** 3161 * Register (RVU_PF_BAR0) nix#_af_lf#_sqs_base 3162 * 3163 * NIX AF Local Function Send Queues Base Address Register This register 3164 * specifies the base AF IOVA of the LF's SQ context table. The table 3165 * consists of NIX_AF_LF()_SQS_CFG[MAX_QUEUESM1]+1 contiguous 3166 * NIX_SQ_CTX_HW_S structures. 3167 */ 3168union nixx_af_lfx_sqs_base { 3169 u64 u; 3170 struct nixx_af_lfx_sqs_base_s { 3171 u64 reserved_0_6 : 7; 3172 u64 addr : 46; 3173 u64 reserved_53_63 : 11; 3174 } s; 3175 /* struct nixx_af_lfx_sqs_base_s cn; */ 3176}; 3177 3178static inline u64 NIXX_AF_LFX_SQS_BASE(u64 a) 3179 __attribute__ ((pure, always_inline)); 3180static inline u64 NIXX_AF_LFX_SQS_BASE(u64 a) 3181{ 3182 return 0x4030 + 0x20000 * a; 3183} 3184 3185/** 3186 * Register (RVU_PF_BAR0) nix#_af_lf#_sqs_cfg 3187 * 3188 * NIX AF Local Function Send Queues Configuration Register This register 3189 * configures send queues in the LF. 3190 */ 3191union nixx_af_lfx_sqs_cfg { 3192 u64 u; 3193 struct nixx_af_lfx_sqs_cfg_s { 3194 u64 max_queuesm1 : 20; 3195 u64 way_mask : 16; 3196 u64 caching : 1; 3197 u64 reserved_37_63 : 27; 3198 } s; 3199 /* struct nixx_af_lfx_sqs_cfg_s cn; */ 3200}; 3201 3202static inline u64 NIXX_AF_LFX_SQS_CFG(u64 a) 3203 __attribute__ ((pure, always_inline)); 3204static inline u64 NIXX_AF_LFX_SQS_CFG(u64 a) 3205{ 3206 return 0x4020 + 0x20000 * a; 3207} 3208 3209/** 3210 * Register (RVU_PF_BAR0) nix#_af_lf#_tx_cfg 3211 * 3212 * NIX AF Local Function Transmit Configuration Register 3213 */ 3214union nixx_af_lfx_tx_cfg { 3215 u64 u; 3216 struct nixx_af_lfx_tx_cfg_s { 3217 u64 vlan0_ins_etype : 16; 3218 u64 vlan1_ins_etype : 16; 3219 u64 send_tstmp_ena : 1; 3220 u64 lock_viol_cqe_ena : 1; 3221 u64 lock_ena : 1; 3222 u64 reserved_35_63 : 29; 3223 } s; 3224 /* struct nixx_af_lfx_tx_cfg_s cn; */ 3225}; 3226 3227static inline u64 NIXX_AF_LFX_TX_CFG(u64 a) 3228 __attribute__ ((pure, always_inline)); 3229static inline u64 NIXX_AF_LFX_TX_CFG(u64 a) 3230{ 3231 return 0x4080 + 0x20000 * a; 3232} 3233 3234/** 3235 * Register (RVU_PF_BAR0) nix#_af_lf#_tx_cfg2 3236 * 3237 * NIX AF Local Function Transmit Configuration Register 3238 */ 3239union nixx_af_lfx_tx_cfg2 { 3240 u64 u; 3241 struct nixx_af_lfx_tx_cfg2_s { 3242 u64 lmt_ena : 1; 3243 u64 reserved_1_63 : 63; 3244 } s; 3245 /* struct nixx_af_lfx_tx_cfg2_s cn; */ 3246}; 3247 3248static inline u64 NIXX_AF_LFX_TX_CFG2(u64 a) 3249 __attribute__ ((pure, always_inline)); 3250static inline u64 NIXX_AF_LFX_TX_CFG2(u64 a) 3251{ 3252 return 0x4028 + 0x20000 * a; 3253} 3254 3255/** 3256 * Register (RVU_PF_BAR0) nix#_af_lf#_tx_parse_cfg 3257 * 3258 * NIX AF Local Function Transmit Parse Configuration Register 3259 */ 3260union nixx_af_lfx_tx_parse_cfg { 3261 u64 u; 3262 struct nixx_af_lfx_tx_parse_cfg_s { 3263 u64 pkind : 6; 3264 u64 reserved_6_63 : 58; 3265 } s; 3266 /* struct nixx_af_lfx_tx_parse_cfg_s cn; */ 3267}; 3268 3269static inline u64 NIXX_AF_LFX_TX_PARSE_CFG(u64 a) 3270 __attribute__ ((pure, always_inline)); 3271static inline u64 NIXX_AF_LFX_TX_PARSE_CFG(u64 a) 3272{ 3273 return 0x4090 + 0x20000 * a; 3274} 3275 3276/** 3277 * Register (RVU_PF_BAR0) nix#_af_lf#_tx_stat# 3278 * 3279 * NIX AF Local Function Transmit Statistics Registers The last dimension 3280 * indicates which statistic, and is enumerated by NIX_STAT_LF_TX_E. 3281 */ 3282union nixx_af_lfx_tx_statx { 3283 u64 u; 3284 struct nixx_af_lfx_tx_statx_s { 3285 u64 stat : 48; 3286 u64 reserved_48_63 : 16; 3287 } s; 3288 /* struct nixx_af_lfx_tx_statx_s cn; */ 3289}; 3290 3291static inline u64 NIXX_AF_LFX_TX_STATX(u64 a, u64 b) 3292 __attribute__ ((pure, always_inline)); 3293static inline u64 NIXX_AF_LFX_TX_STATX(u64 a, u64 b) 3294{ 3295 return 0x4400 + 0x20000 * a + 8 * b; 3296} 3297 3298/** 3299 * Register (RVU_PF_BAR0) nix#_af_lf#_tx_status 3300 * 3301 * NIX AF LF Transmit Status Register 3302 */ 3303union nixx_af_lfx_tx_status { 3304 u64 u; 3305 struct nixx_af_lfx_tx_status_s { 3306 u64 sq_ctx_err : 1; 3307 u64 reserved_1_63 : 63; 3308 } s; 3309 /* struct nixx_af_lfx_tx_status_s cn; */ 3310}; 3311 3312static inline u64 NIXX_AF_LFX_TX_STATUS(u64 a) 3313 __attribute__ ((pure, always_inline)); 3314static inline u64 NIXX_AF_LFX_TX_STATUS(u64 a) 3315{ 3316 return 0x4180 + 0x20000 * a; 3317} 3318 3319/** 3320 * Register (RVU_PF_BAR0) nix#_af_lf_rst 3321 * 3322 * NIX Admin Function LF Reset Register 3323 */ 3324union nixx_af_lf_rst { 3325 u64 u; 3326 struct nixx_af_lf_rst_s { 3327 u64 lf : 8; 3328 u64 reserved_8_11 : 4; 3329 u64 exec : 1; 3330 u64 reserved_13_63 : 51; 3331 } s; 3332 /* struct nixx_af_lf_rst_s cn; */ 3333}; 3334 3335static inline u64 NIXX_AF_LF_RST(void) 3336 __attribute__ ((pure, always_inline)); 3337static inline u64 NIXX_AF_LF_RST(void) 3338{ 3339 return 0x150; 3340} 3341 3342/** 3343 * Register (RVU_PF_BAR0) nix#_af_lso_cfg 3344 * 3345 * NIX AF Large Send Offload Configuration Register 3346 */ 3347union nixx_af_lso_cfg { 3348 u64 u; 3349 struct nixx_af_lso_cfg_s { 3350 u64 tcp_lsf : 16; 3351 u64 tcp_msf : 16; 3352 u64 tcp_fsf : 16; 3353 u64 reserved_48_62 : 15; 3354 u64 enable : 1; 3355 } s; 3356 /* struct nixx_af_lso_cfg_s cn; */ 3357}; 3358 3359static inline u64 NIXX_AF_LSO_CFG(void) 3360 __attribute__ ((pure, always_inline)); 3361static inline u64 NIXX_AF_LSO_CFG(void) 3362{ 3363 return 0xa8; 3364} 3365 3366/** 3367 * Register (RVU_PF_BAR0) nix#_af_lso_format#_field# 3368 * 3369 * NIX AF Large Send Offload Format Field Registers These registers 3370 * specify LSO packet modification formats. Each format may modify up to 3371 * eight packet fields with the following constraints: * If fewer than 3372 * eight fields are modified, [ALG] must be NIX_LSOALG_E::NOP in the 3373 * unused field registers. * Modified fields must be specified in 3374 * contiguous field registers starting with NIX_AF_LSO_FORMAT()_FIELD(0). 3375 * * Modified fields cannot overlap. * Multiple fields with the same 3376 * [LAYER] value must be specified in ascending [OFFSET] order. * Fields 3377 * in different layers must be specified in ascending [LAYER] order. 3378 */ 3379union nixx_af_lso_formatx_fieldx { 3380 u64 u; 3381 struct nixx_af_lso_formatx_fieldx_s { 3382 u64 offset : 8; 3383 u64 layer : 2; 3384 u64 reserved_10_11 : 2; 3385 u64 sizem1 : 2; 3386 u64 reserved_14_15 : 2; 3387 u64 alg : 3; 3388 u64 reserved_19_63 : 45; 3389 } s; 3390 /* struct nixx_af_lso_formatx_fieldx_s cn; */ 3391}; 3392 3393static inline u64 NIXX_AF_LSO_FORMATX_FIELDX(u64 a, u64 b) 3394 __attribute__ ((pure, always_inline)); 3395static inline u64 NIXX_AF_LSO_FORMATX_FIELDX(u64 a, u64 b) 3396{ 3397 return 0x1b00 + 0x10000 * a + 8 * b; 3398} 3399 3400/** 3401 * Register (RVU_PF_BAR0) nix#_af_mark_format#_ctl 3402 * 3403 * NIX AF Packet Marking Format Registers Describes packet marking 3404 * calculations for YELLOW and for NIX_COLORRESULT_E::RED_SEND packets. 3405 * NIX_SEND_EXT_S[MARKFORM] selects the CSR used for the packet 3406 * descriptor. All the packet marking offset calculations assume big- 3407 * endian bits within a byte. For example, if NIX_SEND_EXT_S[MARKPTR] is 3408 * 3 and [OFFSET] is 5 and the packet is YELLOW, the NIX marking hardware 3409 * would do this: _ byte[3]\<2:0\> |= [Y_VAL]\<3:1\> _ 3410 * byte[3]\<2:0\> &= ~[Y_MASK]\<3:1\> _ byte[4]\<7\> |= [Y_VAL]\<0\> 3411 * _ byte[4]\<7\> &= ~[Y_MASK]\<0\> where byte[3] is the third byte 3412 * in the packet, and byte[4] the fourth. For another example, if 3413 * NIX_SEND_EXT_S[MARKPTR] is 3 and [OFFSET] is 0 and the packet is 3414 * NIX_COLORRESULT_E::RED_SEND, _ byte[3]\<7:4\> |= [R_VAL]\<3:0\> _ 3415 * byte[3]\<7:4\> &= ~[R_MASK]\<3:0\> 3416 */ 3417union nixx_af_mark_formatx_ctl { 3418 u64 u; 3419 struct nixx_af_mark_formatx_ctl_s { 3420 u64 r_val : 4; 3421 u64 r_mask : 4; 3422 u64 y_val : 4; 3423 u64 y_mask : 4; 3424 u64 offset : 3; 3425 u64 reserved_19_63 : 45; 3426 } s; 3427 /* struct nixx_af_mark_formatx_ctl_s cn; */ 3428}; 3429 3430static inline u64 NIXX_AF_MARK_FORMATX_CTL(u64 a) 3431 __attribute__ ((pure, always_inline)); 3432static inline u64 NIXX_AF_MARK_FORMATX_CTL(u64 a) 3433{ 3434 return 0x900 + 0x40000 * a; 3435} 3436 3437/** 3438 * Register (RVU_PF_BAR0) nix#_af_mc_mirror_const 3439 * 3440 * NIX AF Multicast/Mirror Constants Register This register contains 3441 * constants for software discovery. 3442 */ 3443union nixx_af_mc_mirror_const { 3444 u64 u; 3445 struct nixx_af_mc_mirror_const_s { 3446 u64 buf_size : 16; 3447 u64 reserved_16_63 : 48; 3448 } s; 3449 /* struct nixx_af_mc_mirror_const_s cn; */ 3450}; 3451 3452static inline u64 NIXX_AF_MC_MIRROR_CONST(void) 3453 __attribute__ ((pure, always_inline)); 3454static inline u64 NIXX_AF_MC_MIRROR_CONST(void) 3455{ 3456 return 0x98; 3457} 3458 3459/** 3460 * Register (RVU_PF_BAR0) nix#_af_mdq#_cir 3461 * 3462 * NIX AF Meta Descriptor Queue Committed Information Rate Registers This 3463 * register has the same bit fields as NIX_AF_TL1()_CIR. 3464 */ 3465union nixx_af_mdqx_cir { 3466 u64 u; 3467 struct nixx_af_mdqx_cir_s { 3468 u64 enable : 1; 3469 u64 rate_mantissa : 8; 3470 u64 rate_exponent : 4; 3471 u64 rate_divider_exponent : 4; 3472 u64 reserved_17_28 : 12; 3473 u64 burst_mantissa : 8; 3474 u64 burst_exponent : 4; 3475 u64 reserved_41_63 : 23; 3476 } s; 3477 /* struct nixx_af_mdqx_cir_s cn; */ 3478}; 3479 3480static inline u64 NIXX_AF_MDQX_CIR(u64 a) 3481 __attribute__ ((pure, always_inline)); 3482static inline u64 NIXX_AF_MDQX_CIR(u64 a) 3483{ 3484 return 0x1420 + 0x10000 * a; 3485} 3486 3487/** 3488 * Register (RVU_PF_BAR0) nix#_af_mdq#_md_debug 3489 * 3490 * NIX AF Meta Descriptor Queue Meta Descriptor State Debug Registers 3491 * This register provides access to the meta descriptor at the front of 3492 * the MDQ. An MDQ can hold up to 8 packet meta descriptors (PMD) and one 3493 * flush meta descriptor (FMD). 3494 */ 3495union nixx_af_mdqx_md_debug { 3496 u64 u; 3497 struct nixx_af_mdqx_md_debug_s { 3498 u64 pkt_len : 16; 3499 u64 red_algo_override : 2; 3500 u64 shp_dis : 1; 3501 u64 reserved_19 : 1; 3502 u64 shp_chg : 9; 3503 u64 reserved_29_31 : 3; 3504 u64 sqm_pkt_id : 13; 3505 u64 reserved_45_60 : 16; 3506 u64 md_type : 2; 3507 u64 reserved_63 : 1; 3508 } s; 3509 /* struct nixx_af_mdqx_md_debug_s cn; */ 3510}; 3511 3512static inline u64 NIXX_AF_MDQX_MD_DEBUG(u64 a) 3513 __attribute__ ((pure, always_inline)); 3514static inline u64 NIXX_AF_MDQX_MD_DEBUG(u64 a) 3515{ 3516 return 0x14c0 + 0x10000 * a; 3517} 3518 3519/** 3520 * Register (RVU_PF_BAR0) nix#_af_mdq#_parent 3521 * 3522 * NIX AF Meta Descriptor Queue Topology Registers 3523 */ 3524union nixx_af_mdqx_parent { 3525 u64 u; 3526 struct nixx_af_mdqx_parent_s { 3527 u64 reserved_0_15 : 16; 3528 u64 parent : 9; 3529 u64 reserved_25_63 : 39; 3530 } s; 3531 /* struct nixx_af_mdqx_parent_s cn; */ 3532}; 3533 3534static inline u64 NIXX_AF_MDQX_PARENT(u64 a) 3535 __attribute__ ((pure, always_inline)); 3536static inline u64 NIXX_AF_MDQX_PARENT(u64 a) 3537{ 3538 return 0x1480 + 0x10000 * a; 3539} 3540 3541/** 3542 * Register (RVU_PF_BAR0) nix#_af_mdq#_pir 3543 * 3544 * NIX AF Meta Descriptor Queue Peak Information Rate Registers This 3545 * register has the same bit fields as NIX_AF_TL1()_CIR. 3546 */ 3547union nixx_af_mdqx_pir { 3548 u64 u; 3549 struct nixx_af_mdqx_pir_s { 3550 u64 enable : 1; 3551 u64 rate_mantissa : 8; 3552 u64 rate_exponent : 4; 3553 u64 rate_divider_exponent : 4; 3554 u64 reserved_17_28 : 12; 3555 u64 burst_mantissa : 8; 3556 u64 burst_exponent : 4; 3557 u64 reserved_41_63 : 23; 3558 } s; 3559 /* struct nixx_af_mdqx_pir_s cn; */ 3560}; 3561 3562static inline u64 NIXX_AF_MDQX_PIR(u64 a) 3563 __attribute__ ((pure, always_inline)); 3564static inline u64 NIXX_AF_MDQX_PIR(u64 a) 3565{ 3566 return 0x1430 + 0x10000 * a; 3567} 3568 3569/** 3570 * Register (RVU_PF_BAR0) nix#_af_mdq#_pointers 3571 * 3572 * INTERNAL: NIX AF Meta Descriptor 4 Linked List Pointers Debug Register 3573 * This register has the same bit fields as NIX_AF_TL4()_POINTERS. 3574 */ 3575union nixx_af_mdqx_pointers { 3576 u64 u; 3577 struct nixx_af_mdqx_pointers_s { 3578 u64 next : 9; 3579 u64 reserved_9_15 : 7; 3580 u64 prev : 9; 3581 u64 reserved_25_63 : 39; 3582 } s; 3583 /* struct nixx_af_mdqx_pointers_s cn; */ 3584}; 3585 3586static inline u64 NIXX_AF_MDQX_POINTERS(u64 a) 3587 __attribute__ ((pure, always_inline)); 3588static inline u64 NIXX_AF_MDQX_POINTERS(u64 a) 3589{ 3590 return 0x1460 + 0x10000 * a; 3591} 3592 3593/** 3594 * Register (RVU_PF_BAR0) nix#_af_mdq#_ptr_fifo 3595 * 3596 * INTERNAL: NIX Meta Descriptor Queue Pointer FIFO State Debug Registers 3597 */ 3598union nixx_af_mdqx_ptr_fifo { 3599 u64 u; 3600 struct nixx_af_mdqx_ptr_fifo_s { 3601 u64 tail : 4; 3602 u64 head : 4; 3603 u64 p_con : 1; 3604 u64 reserved_9_63 : 55; 3605 } s; 3606 /* struct nixx_af_mdqx_ptr_fifo_s cn; */ 3607}; 3608 3609static inline u64 NIXX_AF_MDQX_PTR_FIFO(u64 a) 3610 __attribute__ ((pure, always_inline)); 3611static inline u64 NIXX_AF_MDQX_PTR_FIFO(u64 a) 3612{ 3613 return 0x14d0 + 0x10000 * a; 3614} 3615 3616/** 3617 * Register (RVU_PF_BAR0) nix#_af_mdq#_sched_state 3618 * 3619 * NIX AF Meta Descriptor Queue Scheduling Control State Registers This 3620 * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE. 3621 */ 3622union nixx_af_mdqx_sched_state { 3623 u64 u; 3624 struct nixx_af_mdqx_sched_state_s { 3625 u64 rr_count : 25; 3626 u64 reserved_25_63 : 39; 3627 } s; 3628 /* struct nixx_af_mdqx_sched_state_s cn; */ 3629}; 3630 3631static inline u64 NIXX_AF_MDQX_SCHED_STATE(u64 a) 3632 __attribute__ ((pure, always_inline)); 3633static inline u64 NIXX_AF_MDQX_SCHED_STATE(u64 a) 3634{ 3635 return 0x1440 + 0x10000 * a; 3636} 3637 3638/** 3639 * Register (RVU_PF_BAR0) nix#_af_mdq#_schedule 3640 * 3641 * NIX AF Meta Descriptor Queue Scheduling Control Registers This 3642 * register has the same bit fields as NIX_AF_TL2()_SCHEDULE. 3643 */ 3644union nixx_af_mdqx_schedule { 3645 u64 u; 3646 struct nixx_af_mdqx_schedule_s { 3647 u64 rr_quantum : 24; 3648 u64 prio : 4; 3649 u64 reserved_28_63 : 36; 3650 } s; 3651 /* struct nixx_af_mdqx_schedule_s cn; */ 3652}; 3653 3654static inline u64 NIXX_AF_MDQX_SCHEDULE(u64 a) 3655 __attribute__ ((pure, always_inline)); 3656static inline u64 NIXX_AF_MDQX_SCHEDULE(u64 a) 3657{ 3658 return 0x1400 + 0x10000 * a; 3659} 3660 3661/** 3662 * Register (RVU_PF_BAR0) nix#_af_mdq#_shape 3663 * 3664 * NIX AF Meta Descriptor Queue Shaping Control Registers This register 3665 * has the same bit fields as NIX_AF_TL3()_SHAPE. 3666 */ 3667union nixx_af_mdqx_shape { 3668 u64 u; 3669 struct nixx_af_mdqx_shape_s { 3670 u64 adjust : 9; 3671 u64 red_algo : 2; 3672 u64 red_disable : 1; 3673 u64 yellow_disable : 1; 3674 u64 reserved_13_23 : 11; 3675 u64 length_disable : 1; 3676 u64 schedule_list : 2; 3677 u64 reserved_27_63 : 37; 3678 } s; 3679 /* struct nixx_af_mdqx_shape_s cn; */ 3680}; 3681 3682static inline u64 NIXX_AF_MDQX_SHAPE(u64 a) 3683 __attribute__ ((pure, always_inline)); 3684static inline u64 NIXX_AF_MDQX_SHAPE(u64 a) 3685{ 3686 return 0x1410 + 0x10000 * a; 3687} 3688 3689/** 3690 * Register (RVU_PF_BAR0) nix#_af_mdq#_shape_state 3691 * 3692 * NIX AF Meta Descriptor Queue Shaping State Registers This register has 3693 * the same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must 3694 * not be written during normal operation. 3695 */ 3696union nixx_af_mdqx_shape_state { 3697 u64 u; 3698 struct nixx_af_mdqx_shape_state_s { 3699 u64 cir_accum : 26; 3700 u64 pir_accum : 26; 3701 u64 color : 2; 3702 u64 reserved_54_63 : 10; 3703 } s; 3704 /* struct nixx_af_mdqx_shape_state_s cn; */ 3705}; 3706 3707static inline u64 NIXX_AF_MDQX_SHAPE_STATE(u64 a) 3708 __attribute__ ((pure, always_inline)); 3709static inline u64 NIXX_AF_MDQX_SHAPE_STATE(u64 a) 3710{ 3711 return 0x1450 + 0x10000 * a; 3712} 3713 3714/** 3715 * Register (RVU_PF_BAR0) nix#_af_mdq#_sw_xoff 3716 * 3717 * NIX AF Meta Descriptor Controlled XOFF Registers This register has the 3718 * same bit fields as NIX_AF_TL1()_SW_XOFF 3719 */ 3720union nixx_af_mdqx_sw_xoff { 3721 u64 u; 3722 struct nixx_af_mdqx_sw_xoff_s { 3723 u64 xoff : 1; 3724 u64 drain : 1; 3725 u64 reserved_2 : 1; 3726 u64 drain_irq : 1; 3727 u64 reserved_4_63 : 60; 3728 } s; 3729 /* struct nixx_af_mdqx_sw_xoff_s cn; */ 3730}; 3731 3732static inline u64 NIXX_AF_MDQX_SW_XOFF(u64 a) 3733 __attribute__ ((pure, always_inline)); 3734static inline u64 NIXX_AF_MDQX_SW_XOFF(u64 a) 3735{ 3736 return 0x1470 + 0x10000 * a; 3737} 3738 3739/** 3740 * Register (RVU_PF_BAR0) nix#_af_mdq_const 3741 * 3742 * NIX AF Meta Descriptor Queue Constants Register This register contains 3743 * constants for software discovery. 3744 */ 3745union nixx_af_mdq_const { 3746 u64 u; 3747 struct nixx_af_mdq_const_s { 3748 u64 count : 16; 3749 u64 reserved_16_63 : 48; 3750 } s; 3751 /* struct nixx_af_mdq_const_s cn; */ 3752}; 3753 3754static inline u64 NIXX_AF_MDQ_CONST(void) 3755 __attribute__ ((pure, always_inline)); 3756static inline u64 NIXX_AF_MDQ_CONST(void) 3757{ 3758 return 0x90; 3759} 3760 3761/** 3762 * Register (RVU_PF_BAR0) nix#_af_ndc_cfg 3763 * 3764 * NIX AF General Configuration Register 3765 */ 3766union nixx_af_ndc_cfg { 3767 u64 u; 3768 struct nixx_af_ndc_cfg_s { 3769 u64 ndc_ign_pois : 1; 3770 u64 byp_sq : 1; 3771 u64 byp_sqb : 1; 3772 u64 byp_cqs : 1; 3773 u64 byp_cints : 1; 3774 u64 byp_dyno : 1; 3775 u64 byp_mce : 1; 3776 u64 byp_rqc : 1; 3777 u64 byp_rsse : 1; 3778 u64 byp_mc_data : 1; 3779 u64 byp_mc_wqe : 1; 3780 u64 byp_mr_data : 1; 3781 u64 byp_mr_wqe : 1; 3782 u64 byp_qints : 1; 3783 u64 reserved_14_63 : 50; 3784 } s; 3785 /* struct nixx_af_ndc_cfg_s cn; */ 3786}; 3787 3788static inline u64 NIXX_AF_NDC_CFG(void) 3789 __attribute__ ((pure, always_inline)); 3790static inline u64 NIXX_AF_NDC_CFG(void) 3791{ 3792 return 0x18; 3793} 3794 3795/** 3796 * Register (RVU_PF_BAR0) nix#_af_ndc_rx_sync 3797 * 3798 * NIX AF Receive NDC Sync Register Used to synchronize the NIX receive 3799 * NDC (NDC_IDX_E::NIX()_RX). 3800 */ 3801union nixx_af_ndc_rx_sync { 3802 u64 u; 3803 struct nixx_af_ndc_rx_sync_s { 3804 u64 lf : 8; 3805 u64 reserved_8_11 : 4; 3806 u64 exec : 1; 3807 u64 reserved_13_63 : 51; 3808 } s; 3809 /* struct nixx_af_ndc_rx_sync_s cn; */ 3810}; 3811 3812static inline u64 NIXX_AF_NDC_RX_SYNC(void) 3813 __attribute__ ((pure, always_inline)); 3814static inline u64 NIXX_AF_NDC_RX_SYNC(void) 3815{ 3816 return 0x3e0; 3817} 3818 3819/** 3820 * Register (RVU_PF_BAR0) nix#_af_ndc_tx_sync 3821 * 3822 * NIX AF NDC_TX Sync Register Used to synchronize the NIX transmit NDC 3823 * (NDC_IDX_E::NIX()_TX). 3824 */ 3825union nixx_af_ndc_tx_sync { 3826 u64 u; 3827 struct nixx_af_ndc_tx_sync_s { 3828 u64 lf : 8; 3829 u64 reserved_8_11 : 4; 3830 u64 exec : 1; 3831 u64 reserved_13_63 : 51; 3832 } s; 3833 /* struct nixx_af_ndc_tx_sync_s cn; */ 3834}; 3835 3836static inline u64 NIXX_AF_NDC_TX_SYNC(void) 3837 __attribute__ ((pure, always_inline)); 3838static inline u64 NIXX_AF_NDC_TX_SYNC(void) 3839{ 3840 return 0x3f0; 3841} 3842 3843/** 3844 * Register (RVU_PF_BAR0) nix#_af_norm_tx_fifo_status 3845 * 3846 * NIX AF Normal Transmit FIFO Status Register Status of FIFO which 3847 * transmits normal packets to CGX and LBK. 3848 */ 3849union nixx_af_norm_tx_fifo_status { 3850 u64 u; 3851 struct nixx_af_norm_tx_fifo_status_s { 3852 u64 count : 12; 3853 u64 reserved_12_63 : 52; 3854 } s; 3855 /* struct nixx_af_norm_tx_fifo_status_s cn; */ 3856}; 3857 3858static inline u64 NIXX_AF_NORM_TX_FIFO_STATUS(void) 3859 __attribute__ ((pure, always_inline)); 3860static inline u64 NIXX_AF_NORM_TX_FIFO_STATUS(void) 3861{ 3862 return 0x648; 3863} 3864 3865/** 3866 * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_exp 3867 * 3868 * INTERNAL: NIX AF PQ Arb Link EXPRESS Debug Register 3869 */ 3870union nixx_af_pqx_dbg_arb_link_exp { 3871 u64 u; 3872 struct nixx_af_pqx_dbg_arb_link_exp_s { 3873 u64 req : 1; 3874 u64 act_c_con : 1; 3875 u64 cnt : 2; 3876 u64 reserved_4_5 : 2; 3877 u64 rr_mask : 1; 3878 u64 reserved_7_63 : 57; 3879 } s; 3880 /* struct nixx_af_pqx_dbg_arb_link_exp_s cn; */ 3881}; 3882 3883static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_EXP(u64 a) 3884 __attribute__ ((pure, always_inline)); 3885static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_EXP(u64 a) 3886{ 3887 return 0xce8 + 0x10000 * a; 3888} 3889 3890/** 3891 * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_nrm 3892 * 3893 * INTERNAL: NIX AF PQ Arb Link NORMAL Debug Register 3894 */ 3895union nixx_af_pqx_dbg_arb_link_nrm { 3896 u64 u; 3897 struct nixx_af_pqx_dbg_arb_link_nrm_s { 3898 u64 req : 1; 3899 u64 act_c_con : 1; 3900 u64 cnt : 2; 3901 u64 reserved_4_5 : 2; 3902 u64 rr_mask : 1; 3903 u64 reserved_7_63 : 57; 3904 } s; 3905 /* struct nixx_af_pqx_dbg_arb_link_nrm_s cn; */ 3906}; 3907 3908static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_NRM(u64 a) 3909 __attribute__ ((pure, always_inline)); 3910static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_NRM(u64 a) 3911{ 3912 return 0xce0 + 0x10000 * a; 3913} 3914 3915/** 3916 * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_sdp 3917 * 3918 * INTERNAL: NIX AF PQ Arb Link SDP Debug Register 3919 */ 3920union nixx_af_pqx_dbg_arb_link_sdp { 3921 u64 u; 3922 struct nixx_af_pqx_dbg_arb_link_sdp_s { 3923 u64 req : 1; 3924 u64 act_c_con : 1; 3925 u64 cnt : 2; 3926 u64 reserved_4_5 : 2; 3927 u64 rr_mask : 1; 3928 u64 reserved_7_63 : 57; 3929 } s; 3930 /* struct nixx_af_pqx_dbg_arb_link_sdp_s cn; */ 3931}; 3932 3933static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_SDP(u64 a) 3934 __attribute__ ((pure, always_inline)); 3935static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_SDP(u64 a) 3936{ 3937 return 0xcf0 + 0x10000 * a; 3938} 3939 3940/** 3941 * Register (RVU_PF_BAR0) nix#_af_pq_arb_crd_rdy_debug 3942 * 3943 * INTERNAL: NIX AF PQ_ARB Node Credit Ready Registers NIX AF PQ ARB 3944 * Credit ready register 3945 */ 3946union nixx_af_pq_arb_crd_rdy_debug { 3947 u64 u; 3948 struct nixx_af_pq_arb_crd_rdy_debug_s { 3949 u64 node_crd_rdy : 28; 3950 u64 reserved_28_63 : 36; 3951 } s; 3952 /* struct nixx_af_pq_arb_crd_rdy_debug_s cn; */ 3953}; 3954 3955static inline u64 NIXX_AF_PQ_ARB_CRD_RDY_DEBUG(void) 3956 __attribute__ ((pure, always_inline)); 3957static inline u64 NIXX_AF_PQ_ARB_CRD_RDY_DEBUG(void) 3958{ 3959 return 0xf10; 3960} 3961 3962/** 3963 * Register (RVU_PF_BAR0) nix#_af_pq_arb_dwrr_msk_debug 3964 * 3965 * INTERNAL: NIX AF PQ_ARB DWRR mask set read only debug Registers 3966 */ 3967union nixx_af_pq_arb_dwrr_msk_debug { 3968 u64 u; 3969 struct nixx_af_pq_arb_dwrr_msk_debug_s { 3970 u64 node_dwrr_mask_set : 28; 3971 u64 reserved_28_63 : 36; 3972 } s; 3973 /* struct nixx_af_pq_arb_dwrr_msk_debug_s cn; */ 3974}; 3975 3976static inline u64 NIXX_AF_PQ_ARB_DWRR_MSK_DEBUG(void) 3977 __attribute__ ((pure, always_inline)); 3978static inline u64 NIXX_AF_PQ_ARB_DWRR_MSK_DEBUG(void) 3979{ 3980 return 0xf30; 3981} 3982 3983/** 3984 * Register (RVU_PF_BAR0) nix#_af_pq_arb_node_gnt_debug 3985 * 3986 * INTERNAL: NIX AF PQ_ARB Node Grant vector Registers 3987 */ 3988union nixx_af_pq_arb_node_gnt_debug { 3989 u64 u; 3990 struct nixx_af_pq_arb_node_gnt_debug_s { 3991 u64 node_grant_vec : 28; 3992 u64 reserved_28_63 : 36; 3993 } s; 3994 /* struct nixx_af_pq_arb_node_gnt_debug_s cn; */ 3995}; 3996 3997static inline u64 NIXX_AF_PQ_ARB_NODE_GNT_DEBUG(void) 3998 __attribute__ ((pure, always_inline)); 3999static inline u64 NIXX_AF_PQ_ARB_NODE_GNT_DEBUG(void) 4000{ 4001 return 0xf20; 4002} 4003 4004/** 4005 * Register (RVU_PF_BAR0) nix#_af_pq_arb_node_req_debug 4006 * 4007 * INTERNAL: NIX AF PQ_ARB Node Request Debug Registers NIX AF PQ ARB 4008 * Node Request Debug register 4009 */ 4010union nixx_af_pq_arb_node_req_debug { 4011 u64 u; 4012 struct nixx_af_pq_arb_node_req_debug_s { 4013 u64 node_req : 28; 4014 u64 reserved_28_63 : 36; 4015 } s; 4016 /* struct nixx_af_pq_arb_node_req_debug_s cn; */ 4017}; 4018 4019static inline u64 NIXX_AF_PQ_ARB_NODE_REQ_DEBUG(void) 4020 __attribute__ ((pure, always_inline)); 4021static inline u64 NIXX_AF_PQ_ARB_NODE_REQ_DEBUG(void) 4022{ 4023 return 0xf00; 4024} 4025 4026/** 4027 * Register (RVU_PF_BAR0) nix#_af_pq_arb_shape_vld_dbg 4028 * 4029 * INTERNAL: NIX AF PQ_ARB shape valid set Register 4030 */ 4031union nixx_af_pq_arb_shape_vld_dbg { 4032 u64 u; 4033 struct nixx_af_pq_arb_shape_vld_dbg_s { 4034 u64 node_shape_vld_set : 28; 4035 u64 reserved_28_63 : 36; 4036 } s; 4037 /* struct nixx_af_pq_arb_shape_vld_dbg_s cn; */ 4038}; 4039 4040static inline u64 NIXX_AF_PQ_ARB_SHAPE_VLD_DBG(void) 4041 __attribute__ ((pure, always_inline)); 4042static inline u64 NIXX_AF_PQ_ARB_SHAPE_VLD_DBG(void) 4043{ 4044 return 0xf40; 4045} 4046 4047/** 4048 * Register (RVU_PF_BAR0) nix#_af_pq_dbg_arb_0 4049 * 4050 * INTERNAL: NIX AF PQ Arb Debug 0 Register 4051 */ 4052union nixx_af_pq_dbg_arb_0 { 4053 u64 u; 4054 struct nixx_af_pq_dbg_arb_0_s { 4055 u64 rr_mask_clr : 1; 4056 u64 reserved_1_63 : 63; 4057 } s; 4058 /* struct nixx_af_pq_dbg_arb_0_s cn; */ 4059}; 4060 4061static inline u64 NIXX_AF_PQ_DBG_ARB_0(void) 4062 __attribute__ ((pure, always_inline)); 4063static inline u64 NIXX_AF_PQ_DBG_ARB_0(void) 4064{ 4065 return 0xcf8; 4066} 4067 4068/** 4069 * Register (RVU_PF_BAR0) nix#_af_pq_lnk_#_dwrr_msk_dbg 4070 * 4071 * INTERNAL: NIX AF PQ_ARB Physical Link DWRR MASK Registers 4072 */ 4073union nixx_af_pq_lnk_x_dwrr_msk_dbg { 4074 u64 u; 4075 struct nixx_af_pq_lnk_x_dwrr_msk_dbg_s { 4076 u64 link_dwrr_mask_set : 28; 4077 u64 reserved_28_63 : 36; 4078 } s; 4079 /* struct nixx_af_pq_lnk_x_dwrr_msk_dbg_s cn; */ 4080}; 4081 4082static inline u64 NIXX_AF_PQ_LNK_X_DWRR_MSK_DBG(u64 a) 4083 __attribute__ ((pure, always_inline)); 4084static inline u64 NIXX_AF_PQ_LNK_X_DWRR_MSK_DBG(u64 a) 4085{ 4086 return 0x1100 + 0x10000 * a; 4087} 4088 4089/** 4090 * Register (RVU_PF_BAR0) nix#_af_pse_400_rate_divider 4091 * 4092 * INTERNAL: NIX AF PSE 400 Rate Divider Register 4093 */ 4094union nixx_af_pse_400_rate_divider { 4095 u64 u; 4096 struct nixx_af_pse_400_rate_divider_s { 4097 u64 rate_div_cfg : 9; 4098 u64 reserved_9_63 : 55; 4099 } s; 4100 /* struct nixx_af_pse_400_rate_divider_s cn; */ 4101}; 4102 4103static inline u64 NIXX_AF_PSE_400_RATE_DIVIDER(void) 4104 __attribute__ ((pure, always_inline)); 4105static inline u64 NIXX_AF_PSE_400_RATE_DIVIDER(void) 4106{ 4107 return 0x830; 4108} 4109 4110/** 4111 * Register (RVU_PF_BAR0) nix#_af_pse_active_cycles_pc 4112 * 4113 * NIX AF Active Cycles Register These registers are indexed by the 4114 * conditional clock domain number. 4115 */ 4116union nixx_af_pse_active_cycles_pc { 4117 u64 u; 4118 struct nixx_af_pse_active_cycles_pc_s { 4119 u64 act_cyc : 64; 4120 } s; 4121 /* struct nixx_af_pse_active_cycles_pc_s cn; */ 4122}; 4123 4124static inline u64 NIXX_AF_PSE_ACTIVE_CYCLES_PC(void) 4125 __attribute__ ((pure, always_inline)); 4126static inline u64 NIXX_AF_PSE_ACTIVE_CYCLES_PC(void) 4127{ 4128 return 0x8c0; 4129} 4130 4131/** 4132 * Register (RVU_PF_BAR0) nix#_af_pse_bp_test0 4133 * 4134 * INTERNAL: NIX AF PSE Backpressure Test 0 Register 4135 */ 4136union nixx_af_pse_bp_test0 { 4137 u64 u; 4138 struct nixx_af_pse_bp_test0_s { 4139 u64 lfsr_freq : 12; 4140 u64 reserved_12_63 : 52; 4141 } s; 4142 struct nixx_af_pse_bp_test0_cn96xxp1 { 4143 u64 lfsr_freq : 12; 4144 u64 reserved_12_15 : 4; 4145 u64 bp_cfg : 8; 4146 u64 reserved_24_59 : 36; 4147 u64 enable : 4; 4148 } cn96xxp1; 4149 struct nixx_af_pse_bp_test0_cn96xxp3 { 4150 u64 lfsr_freq : 12; 4151 u64 reserved_12_15 : 4; 4152 u64 reserved_16_19 : 4; 4153 u64 bp_cfg : 12; 4154 u64 reserved_32_55 : 24; 4155 u64 reserved_56_57 : 2; 4156 u64 enable : 6; 4157 } cn96xxp3; 4158 /* struct nixx_af_pse_bp_test0_cn96xxp1 cnf95xxp1; */ 4159 struct nixx_af_pse_bp_test0_cnf95xxp2 { 4160 u64 lfsr_freq : 12; 4161 u64 reserved_12_15 : 4; 4162 u64 bp_cfg : 8; 4163 u64 reserved_24_31 : 8; 4164 u64 reserved_32_55 : 24; 4165 u64 reserved_56_59 : 4; 4166 u64 enable : 4; 4167 } cnf95xxp2; 4168}; 4169 4170static inline u64 NIXX_AF_PSE_BP_TEST0(void) 4171 __attribute__ ((pure, always_inline)); 4172static inline u64 NIXX_AF_PSE_BP_TEST0(void) 4173{ 4174 return 0x840; 4175} 4176 4177/** 4178 * Register (RVU_PF_BAR0) nix#_af_pse_bp_test1 4179 * 4180 * INTERNAL: NIX AF PSE Backpressure Test 1 Register 4181 */ 4182union nixx_af_pse_bp_test1 { 4183 u64 u; 4184 struct nixx_af_pse_bp_test1_s { 4185 u64 lfsr_freq : 12; 4186 u64 reserved_12_15 : 4; 4187 u64 bp_cfg : 10; 4188 u64 reserved_26_63 : 38; 4189 } s; 4190 struct nixx_af_pse_bp_test1_cn96xxp1 { 4191 u64 lfsr_freq : 12; 4192 u64 reserved_12_15 : 4; 4193 u64 bp_cfg : 8; 4194 u64 reserved_24_59 : 36; 4195 u64 enable : 4; 4196 } cn96xxp1; 4197 struct nixx_af_pse_bp_test1_cn96xxp3 { 4198 u64 lfsr_freq : 12; 4199 u64 reserved_12_15 : 4; 4200 u64 bp_cfg : 10; 4201 u64 reserved_26_31 : 6; 4202 u64 reserved_32_55 : 24; 4203 u64 reserved_56_58 : 3; 4204 u64 enable : 5; 4205 } cn96xxp3; 4206 /* struct nixx_af_pse_bp_test1_cn96xxp1 cnf95xxp1; */ 4207 struct nixx_af_pse_bp_test1_cnf95xxp2 { 4208 u64 lfsr_freq : 12; 4209 u64 reserved_12_15 : 4; 4210 u64 bp_cfg : 8; 4211 u64 reserved_24_31 : 8; 4212 u64 reserved_32_55 : 24; 4213 u64 reserved_56_59 : 4; 4214 u64 enable : 4; 4215 } cnf95xxp2; 4216}; 4217 4218static inline u64 NIXX_AF_PSE_BP_TEST1(void) 4219 __attribute__ ((pure, always_inline)); 4220static inline u64 NIXX_AF_PSE_BP_TEST1(void) 4221{ 4222 return 0x850; 4223} 4224 4225/** 4226 * Register (RVU_PF_BAR0) nix#_af_pse_bp_test2 4227 * 4228 * INTERNAL: NIX AF PSE Backpressure Test 2 Register 4229 */ 4230union nixx_af_pse_bp_test2 { 4231 u64 u; 4232 struct nixx_af_pse_bp_test2_s { 4233 u64 lfsr_freq : 12; 4234 u64 reserved_12_15 : 4; 4235 u64 bp_cfg : 10; 4236 u64 reserved_26_63 : 38; 4237 } s; 4238 struct nixx_af_pse_bp_test2_cn96xxp1 { 4239 u64 lfsr_freq : 12; 4240 u64 reserved_12_15 : 4; 4241 u64 bp_cfg : 8; 4242 u64 reserved_24_59 : 36; 4243 u64 enable : 4; 4244 } cn96xxp1; 4245 struct nixx_af_pse_bp_test2_cn96xxp3 { 4246 u64 lfsr_freq : 12; 4247 u64 reserved_12_15 : 4; 4248 u64 bp_cfg : 10; 4249 u64 reserved_26_31 : 6; 4250 u64 reserved_32_55 : 24; 4251 u64 reserved_56_58 : 3; 4252 u64 enable : 5; 4253 } cn96xxp3; 4254 /* struct nixx_af_pse_bp_test2_cn96xxp1 cnf95xxp1; */ 4255 struct nixx_af_pse_bp_test2_cnf95xxp2 { 4256 u64 lfsr_freq : 12; 4257 u64 reserved_12_15 : 4; 4258 u64 bp_cfg : 8; 4259 u64 reserved_24_31 : 8; 4260 u64 reserved_32_55 : 24; 4261 u64 reserved_56_59 : 4; 4262 u64 enable : 4; 4263 } cnf95xxp2; 4264}; 4265 4266static inline u64 NIXX_AF_PSE_BP_TEST2(void) 4267 __attribute__ ((pure, always_inline)); 4268static inline u64 NIXX_AF_PSE_BP_TEST2(void) 4269{ 4270 return 0x860; 4271} 4272 4273/** 4274 * Register (RVU_PF_BAR0) nix#_af_pse_bp_test3 4275 * 4276 * INTERNAL: NIX AF PSE Backpressure Test 3 Register 4277 */ 4278union nixx_af_pse_bp_test3 { 4279 u64 u; 4280 struct nixx_af_pse_bp_test3_s { 4281 u64 lfsr_freq : 12; 4282 u64 reserved_12_15 : 4; 4283 u64 bp_cfg : 10; 4284 u64 reserved_26_63 : 38; 4285 } s; 4286 struct nixx_af_pse_bp_test3_cn96xxp1 { 4287 u64 lfsr_freq : 12; 4288 u64 reserved_12_15 : 4; 4289 u64 bp_cfg : 8; 4290 u64 reserved_24_59 : 36; 4291 u64 enable : 4; 4292 } cn96xxp1; 4293 struct nixx_af_pse_bp_test3_cn96xxp3 { 4294 u64 lfsr_freq : 12; 4295 u64 reserved_12_15 : 4; 4296 u64 bp_cfg : 10; 4297 u64 reserved_26_31 : 6; 4298 u64 reserved_32_55 : 24; 4299 u64 reserved_56_58 : 3; 4300 u64 enable : 5; 4301 } cn96xxp3; 4302 /* struct nixx_af_pse_bp_test3_cn96xxp1 cnf95xxp1; */ 4303 struct nixx_af_pse_bp_test3_cnf95xxp2 { 4304 u64 lfsr_freq : 12; 4305 u64 reserved_12_15 : 4; 4306 u64 bp_cfg : 8; 4307 u64 reserved_24_31 : 8; 4308 u64 reserved_32_55 : 24; 4309 u64 reserved_56_59 : 4; 4310 u64 enable : 4; 4311 } cnf95xxp2; 4312}; 4313 4314static inline u64 NIXX_AF_PSE_BP_TEST3(void) 4315 __attribute__ ((pure, always_inline)); 4316static inline u64 NIXX_AF_PSE_BP_TEST3(void) 4317{ 4318 return 0x870; 4319} 4320 4321/** 4322 * Register (RVU_PF_BAR0) nix#_af_pse_channel_level 4323 * 4324 * NIX AF PSE Channel Level Register 4325 */ 4326union nixx_af_pse_channel_level { 4327 u64 u; 4328 struct nixx_af_pse_channel_level_s { 4329 u64 bp_level : 1; 4330 u64 reserved_1_63 : 63; 4331 } s; 4332 /* struct nixx_af_pse_channel_level_s cn; */ 4333}; 4334 4335static inline u64 NIXX_AF_PSE_CHANNEL_LEVEL(void) 4336 __attribute__ ((pure, always_inline)); 4337static inline u64 NIXX_AF_PSE_CHANNEL_LEVEL(void) 4338{ 4339 return 0x800; 4340} 4341 4342/** 4343 * Register (RVU_PF_BAR0) nix#_af_pse_const 4344 * 4345 * NIX AF PSE Constants Register This register contains constants for 4346 * software discovery. 4347 */ 4348union nixx_af_pse_const { 4349 u64 u; 4350 struct nixx_af_pse_const_s { 4351 u64 levels : 4; 4352 u64 reserved_4_7 : 4; 4353 u64 mark_formats : 8; 4354 u64 reserved_16_63 : 48; 4355 } s; 4356 /* struct nixx_af_pse_const_s cn; */ 4357}; 4358 4359static inline u64 NIXX_AF_PSE_CONST(void) 4360 __attribute__ ((pure, always_inline)); 4361static inline u64 NIXX_AF_PSE_CONST(void) 4362{ 4363 return 0x60; 4364} 4365 4366/** 4367 * Register (RVU_PF_BAR0) nix#_af_pse_eco 4368 * 4369 * INTERNAL: AF PSE ECO Register 4370 */ 4371union nixx_af_pse_eco { 4372 u64 u; 4373 struct nixx_af_pse_eco_s { 4374 u64 eco_rw : 64; 4375 } s; 4376 /* struct nixx_af_pse_eco_s cn; */ 4377}; 4378 4379static inline u64 NIXX_AF_PSE_ECO(void) 4380 __attribute__ ((pure, always_inline)); 4381static inline u64 NIXX_AF_PSE_ECO(void) 4382{ 4383 return 0x5d0; 4384} 4385 4386/** 4387 * Register (RVU_PF_BAR0) nix#_af_pse_expr_bp_test 4388 * 4389 * INTERNAL: NIX AF PSE Express Backpressure Test Register Internal: 4390 * 802.3br frame preemption/express path is defeatured. 4391 */ 4392union nixx_af_pse_expr_bp_test { 4393 u64 u; 4394 struct nixx_af_pse_expr_bp_test_s { 4395 u64 lfsr_freq : 12; 4396 u64 reserved_12_15 : 4; 4397 u64 bp_cfg : 32; 4398 u64 enable : 16; 4399 } s; 4400 /* struct nixx_af_pse_expr_bp_test_s cn; */ 4401}; 4402 4403static inline u64 NIXX_AF_PSE_EXPR_BP_TEST(void) 4404 __attribute__ ((pure, always_inline)); 4405static inline u64 NIXX_AF_PSE_EXPR_BP_TEST(void) 4406{ 4407 return 0x890; 4408} 4409 4410/** 4411 * Register (RVU_PF_BAR0) nix#_af_pse_norm_bp_test 4412 * 4413 * INTERNAL: NIX AF PSE Normal Backpressure Test Register 4414 */ 4415union nixx_af_pse_norm_bp_test { 4416 u64 u; 4417 struct nixx_af_pse_norm_bp_test_s { 4418 u64 lfsr_freq : 12; 4419 u64 reserved_12_15 : 4; 4420 u64 bp_cfg : 32; 4421 u64 reserved_48_63 : 16; 4422 } s; 4423 struct nixx_af_pse_norm_bp_test_cn96xxp1 { 4424 u64 lfsr_freq : 12; 4425 u64 reserved_12_15 : 4; 4426 u64 bp_cfg : 32; 4427 u64 enable : 16; 4428 } cn96xxp1; 4429 struct nixx_af_pse_norm_bp_test_cn96xxp3 { 4430 u64 lfsr_freq : 12; 4431 u64 reserved_12_15 : 4; 4432 u64 bp_cfg : 12; 4433 u64 reserved_28_57 : 30; 4434 u64 enable : 6; 4435 } cn96xxp3; 4436 /* struct nixx_af_pse_norm_bp_test_cn96xxp1 cnf95xx; */ 4437}; 4438 4439static inline u64 NIXX_AF_PSE_NORM_BP_TEST(void) 4440 __attribute__ ((pure, always_inline)); 4441static inline u64 NIXX_AF_PSE_NORM_BP_TEST(void) 4442{ 4443 return 0x880; 4444} 4445 4446/** 4447 * Register (RVU_PF_BAR0) nix#_af_pse_shaper_cfg 4448 * 4449 * NIX AF PSE Shaper Configuration Register 4450 */ 4451union nixx_af_pse_shaper_cfg { 4452 u64 u; 4453 struct nixx_af_pse_shaper_cfg_s { 4454 u64 red_send_as_yellow : 1; 4455 u64 color_aware : 1; 4456 u64 reserved_2_63 : 62; 4457 } s; 4458 /* struct nixx_af_pse_shaper_cfg_s cn; */ 4459}; 4460 4461static inline u64 NIXX_AF_PSE_SHAPER_CFG(void) 4462 __attribute__ ((pure, always_inline)); 4463static inline u64 NIXX_AF_PSE_SHAPER_CFG(void) 4464{ 4465 return 0x810; 4466} 4467 4468/** 4469 * Register (RVU_PF_BAR0) nix#_af_ras 4470 * 4471 * NIX AF RAS Interrupt Register This register is intended for delivery 4472 * of RAS events to the SCP, so should be ignored by OS drivers. 4473 */ 4474union nixx_af_ras { 4475 u64 u; 4476 struct nixx_af_ras_s { 4477 u64 rx_mce_poison : 1; 4478 u64 rx_mcast_wqe_poison : 1; 4479 u64 rx_mirror_wqe_poison : 1; 4480 u64 rx_mcast_data_poison : 1; 4481 u64 rx_mirror_data_poison : 1; 4482 u64 reserved_5_31 : 27; 4483 u64 aq_ctx_poison : 1; 4484 u64 aq_res_poison : 1; 4485 u64 aq_inst_poison : 1; 4486 u64 reserved_35_63 : 29; 4487 } s; 4488 /* struct nixx_af_ras_s cn; */ 4489}; 4490 4491static inline u64 NIXX_AF_RAS(void) 4492 __attribute__ ((pure, always_inline)); 4493static inline u64 NIXX_AF_RAS(void) 4494{ 4495 return 0x1a0; 4496} 4497 4498/** 4499 * Register (RVU_PF_BAR0) nix#_af_ras_ena_w1c 4500 * 4501 * NIX AF RAS Interrupt Enable Clear Register This register clears 4502 * interrupt enable bits. 4503 */ 4504union nixx_af_ras_ena_w1c { 4505 u64 u; 4506 struct nixx_af_ras_ena_w1c_s { 4507 u64 rx_mce_poison : 1; 4508 u64 rx_mcast_wqe_poison : 1; 4509 u64 rx_mirror_wqe_poison : 1; 4510 u64 rx_mcast_data_poison : 1; 4511 u64 rx_mirror_data_poison : 1; 4512 u64 reserved_5_31 : 27; 4513 u64 aq_ctx_poison : 1; 4514 u64 aq_res_poison : 1; 4515 u64 aq_inst_poison : 1; 4516 u64 reserved_35_63 : 29; 4517 } s; 4518 /* struct nixx_af_ras_ena_w1c_s cn; */ 4519}; 4520 4521static inline u64 NIXX_AF_RAS_ENA_W1C(void) 4522 __attribute__ ((pure, always_inline)); 4523static inline u64 NIXX_AF_RAS_ENA_W1C(void) 4524{ 4525 return 0x1b8; 4526} 4527 4528/** 4529 * Register (RVU_PF_BAR0) nix#_af_ras_ena_w1s 4530 * 4531 * NIX AF RAS Interrupt Enable Set Register This register sets interrupt 4532 * enable bits. 4533 */ 4534union nixx_af_ras_ena_w1s { 4535 u64 u; 4536 struct nixx_af_ras_ena_w1s_s { 4537 u64 rx_mce_poison : 1; 4538 u64 rx_mcast_wqe_poison : 1; 4539 u64 rx_mirror_wqe_poison : 1; 4540 u64 rx_mcast_data_poison : 1; 4541 u64 rx_mirror_data_poison : 1; 4542 u64 reserved_5_31 : 27; 4543 u64 aq_ctx_poison : 1; 4544 u64 aq_res_poison : 1; 4545 u64 aq_inst_poison : 1; 4546 u64 reserved_35_63 : 29; 4547 } s; 4548 /* struct nixx_af_ras_ena_w1s_s cn; */ 4549}; 4550 4551static inline u64 NIXX_AF_RAS_ENA_W1S(void) 4552 __attribute__ ((pure, always_inline)); 4553static inline u64 NIXX_AF_RAS_ENA_W1S(void) 4554{ 4555 return 0x1b0; 4556} 4557 4558/** 4559 * Register (RVU_PF_BAR0) nix#_af_ras_w1s 4560 * 4561 * NIX AF RAS Interrupt Set Register This register sets interrupt bits. 4562 */ 4563union nixx_af_ras_w1s { 4564 u64 u; 4565 struct nixx_af_ras_w1s_s { 4566 u64 rx_mce_poison : 1; 4567 u64 rx_mcast_wqe_poison : 1; 4568 u64 rx_mirror_wqe_poison : 1; 4569 u64 rx_mcast_data_poison : 1; 4570 u64 rx_mirror_data_poison : 1; 4571 u64 reserved_5_31 : 27; 4572 u64 aq_ctx_poison : 1; 4573 u64 aq_res_poison : 1; 4574 u64 aq_inst_poison : 1; 4575 u64 reserved_35_63 : 29; 4576 } s; 4577 /* struct nixx_af_ras_w1s_s cn; */ 4578}; 4579 4580static inline u64 NIXX_AF_RAS_W1S(void) 4581 __attribute__ ((pure, always_inline)); 4582static inline u64 NIXX_AF_RAS_W1S(void) 4583{ 4584 return 0x1a8; 4585} 4586 4587/** 4588 * Register (RVU_PF_BAR0) nix#_af_reb_bp_test# 4589 * 4590 * INTERNAL: NIX AF REB Backpressure Test Registers 4591 */ 4592union nixx_af_reb_bp_testx { 4593 u64 u; 4594 struct nixx_af_reb_bp_testx_s { 4595 u64 lfsr_freq : 12; 4596 u64 reserved_12_15 : 4; 4597 u64 bp_cfg : 8; 4598 u64 reserved_24_47 : 24; 4599 u64 enable : 4; 4600 u64 reserved_52_63 : 12; 4601 } s; 4602 /* struct nixx_af_reb_bp_testx_s cn; */ 4603}; 4604 4605static inline u64 NIXX_AF_REB_BP_TESTX(u64 a) 4606 __attribute__ ((pure, always_inline)); 4607static inline u64 NIXX_AF_REB_BP_TESTX(u64 a) 4608{ 4609 return 0x4840 + 0x10000 * a; 4610} 4611 4612/** 4613 * Register (RVU_PF_BAR0) nix#_af_rq_const 4614 * 4615 * NIX AF RQ Constants Register This register contains constants for 4616 * software discovery. 4617 */ 4618union nixx_af_rq_const { 4619 u64 u; 4620 struct nixx_af_rq_const_s { 4621 u64 queues_per_lf : 24; 4622 u64 reserved_24_63 : 40; 4623 } s; 4624 /* struct nixx_af_rq_const_s cn; */ 4625}; 4626 4627static inline u64 NIXX_AF_RQ_CONST(void) 4628 __attribute__ ((pure, always_inline)); 4629static inline u64 NIXX_AF_RQ_CONST(void) 4630{ 4631 return 0x50; 4632} 4633 4634/** 4635 * Register (RVU_PF_BAR0) nix#_af_rqm_bp_test 4636 * 4637 * INTERNAL: NIX AF REB Backpressure Test Registers 4638 */ 4639union nixx_af_rqm_bp_test { 4640 u64 u; 4641 struct nixx_af_rqm_bp_test_s { 4642 u64 lfsr_freq : 12; 4643 u64 reserved_12_15 : 4; 4644 u64 bp_cfg : 16; 4645 u64 reserved_32_47 : 16; 4646 u64 enable : 8; 4647 u64 reserved_56_63 : 8; 4648 } s; 4649 /* struct nixx_af_rqm_bp_test_s cn; */ 4650}; 4651 4652static inline u64 NIXX_AF_RQM_BP_TEST(void) 4653 __attribute__ ((pure, always_inline)); 4654static inline u64 NIXX_AF_RQM_BP_TEST(void) 4655{ 4656 return 0x4880; 4657} 4658 4659/** 4660 * Register (RVU_PF_BAR0) nix#_af_rqm_eco 4661 * 4662 * INTERNAL: AF RQM ECO Register 4663 */ 4664union nixx_af_rqm_eco { 4665 u64 u; 4666 struct nixx_af_rqm_eco_s { 4667 u64 eco_rw : 64; 4668 } s; 4669 /* struct nixx_af_rqm_eco_s cn; */ 4670}; 4671 4672static inline u64 NIXX_AF_RQM_ECO(void) 4673 __attribute__ ((pure, always_inline)); 4674static inline u64 NIXX_AF_RQM_ECO(void) 4675{ 4676 return 0x5a0; 4677} 4678 4679/** 4680 * Register (RVU_PF_BAR0) nix#_af_rvu_int 4681 * 4682 * NIX AF RVU Interrupt Register This register contains RVU error 4683 * interrupt summary bits. 4684 */ 4685union nixx_af_rvu_int { 4686 u64 u; 4687 struct nixx_af_rvu_int_s { 4688 u64 unmapped_slot : 1; 4689 u64 reserved_1_63 : 63; 4690 } s; 4691 /* struct nixx_af_rvu_int_s cn; */ 4692}; 4693 4694static inline u64 NIXX_AF_RVU_INT(void) 4695 __attribute__ ((pure, always_inline)); 4696static inline u64 NIXX_AF_RVU_INT(void) 4697{ 4698 return 0x1c0; 4699} 4700 4701/** 4702 * Register (RVU_PF_BAR0) nix#_af_rvu_int_ena_w1c 4703 * 4704 * NIX AF RVU Interrupt Enable Clear Register This register clears 4705 * interrupt enable bits. 4706 */ 4707union nixx_af_rvu_int_ena_w1c { 4708 u64 u; 4709 struct nixx_af_rvu_int_ena_w1c_s { 4710 u64 unmapped_slot : 1; 4711 u64 reserved_1_63 : 63; 4712 } s; 4713 /* struct nixx_af_rvu_int_ena_w1c_s cn; */ 4714}; 4715 4716static inline u64 NIXX_AF_RVU_INT_ENA_W1C(void) 4717 __attribute__ ((pure, always_inline)); 4718static inline u64 NIXX_AF_RVU_INT_ENA_W1C(void) 4719{ 4720 return 0x1d8; 4721} 4722 4723/** 4724 * Register (RVU_PF_BAR0) nix#_af_rvu_int_ena_w1s 4725 * 4726 * NIX AF RVU Interrupt Enable Set Register This register sets interrupt 4727 * enable bits. 4728 */ 4729union nixx_af_rvu_int_ena_w1s { 4730 u64 u; 4731 struct nixx_af_rvu_int_ena_w1s_s { 4732 u64 unmapped_slot : 1; 4733 u64 reserved_1_63 : 63; 4734 } s; 4735 /* struct nixx_af_rvu_int_ena_w1s_s cn; */ 4736}; 4737 4738static inline u64 NIXX_AF_RVU_INT_ENA_W1S(void) 4739 __attribute__ ((pure, always_inline)); 4740static inline u64 NIXX_AF_RVU_INT_ENA_W1S(void) 4741{ 4742 return 0x1d0; 4743} 4744 4745/** 4746 * Register (RVU_PF_BAR0) nix#_af_rvu_int_w1s 4747 * 4748 * NIX AF RVU Interrupt Set Register This register sets interrupt bits. 4749 */ 4750union nixx_af_rvu_int_w1s { 4751 u64 u; 4752 struct nixx_af_rvu_int_w1s_s { 4753 u64 unmapped_slot : 1; 4754 u64 reserved_1_63 : 63; 4755 } s; 4756 /* struct nixx_af_rvu_int_w1s_s cn; */ 4757}; 4758 4759static inline u64 NIXX_AF_RVU_INT_W1S(void) 4760 __attribute__ ((pure, always_inline)); 4761static inline u64 NIXX_AF_RVU_INT_W1S(void) 4762{ 4763 return 0x1c8; 4764} 4765 4766/** 4767 * Register (RVU_PF_BAR0) nix#_af_rvu_lf_cfg_debug 4768 * 4769 * NIX Privileged LF Configuration Debug Register This debug register 4770 * allows software to lookup the reverse mapping from VF/PF slot to LF. 4771 * The forward mapping is programmed with NIX_PRIV_LF()_CFG. 4772 */ 4773union nixx_af_rvu_lf_cfg_debug { 4774 u64 u; 4775 struct nixx_af_rvu_lf_cfg_debug_s { 4776 u64 lf : 12; 4777 u64 lf_valid : 1; 4778 u64 exec : 1; 4779 u64 reserved_14_15 : 2; 4780 u64 slot : 8; 4781 u64 pf_func : 16; 4782 u64 reserved_40_63 : 24; 4783 } s; 4784 /* struct nixx_af_rvu_lf_cfg_debug_s cn; */ 4785}; 4786 4787static inline u64 NIXX_AF_RVU_LF_CFG_DEBUG(void) 4788 __attribute__ ((pure, always_inline)); 4789static inline u64 NIXX_AF_RVU_LF_CFG_DEBUG(void) 4790{ 4791 return 0x8000030; 4792} 4793 4794/** 4795 * Register (RVU_PF_BAR0) nix#_af_rx_active_cycles_pc# 4796 * 4797 * NIX AF Active Cycles Register These registers are indexed by the 4798 * conditional clock domain number. 4799 */ 4800union nixx_af_rx_active_cycles_pcx { 4801 u64 u; 4802 struct nixx_af_rx_active_cycles_pcx_s { 4803 u64 act_cyc : 64; 4804 } s; 4805 /* struct nixx_af_rx_active_cycles_pcx_s cn; */ 4806}; 4807 4808static inline u64 NIXX_AF_RX_ACTIVE_CYCLES_PCX(u64 a) 4809 __attribute__ ((pure, always_inline)); 4810static inline u64 NIXX_AF_RX_ACTIVE_CYCLES_PCX(u64 a) 4811{ 4812 return 0x4800 + 0x10000 * a; 4813} 4814 4815/** 4816 * Register (RVU_PF_BAR0) nix#_af_rx_bpid#_status 4817 * 4818 * NIX AF Receive Backpressure ID Status Registers 4819 */ 4820union nixx_af_rx_bpidx_status { 4821 u64 u; 4822 struct nixx_af_rx_bpidx_status_s { 4823 u64 aura_cnt : 32; 4824 u64 cq_cnt : 32; 4825 } s; 4826 /* struct nixx_af_rx_bpidx_status_s cn; */ 4827}; 4828 4829static inline u64 NIXX_AF_RX_BPIDX_STATUS(u64 a) 4830 __attribute__ ((pure, always_inline)); 4831static inline u64 NIXX_AF_RX_BPIDX_STATUS(u64 a) 4832{ 4833 return 0x1a20 + 0x20000 * a; 4834} 4835 4836/** 4837 * Register (RVU_PF_BAR0) nix#_af_rx_cfg 4838 * 4839 * NIX AF Receive Configuration Register 4840 */ 4841union nixx_af_rx_cfg { 4842 u64 u; 4843 struct nixx_af_rx_cfg_s { 4844 u64 cbp_ena : 1; 4845 u64 reserved_1_63 : 63; 4846 } s; 4847 /* struct nixx_af_rx_cfg_s cn; */ 4848}; 4849 4850static inline u64 NIXX_AF_RX_CFG(void) 4851 __attribute__ ((pure, always_inline)); 4852static inline u64 NIXX_AF_RX_CFG(void) 4853{ 4854 return 0xd0; 4855} 4856 4857/** 4858 * Register (RVU_PF_BAR0) nix#_af_rx_chan#_cfg 4859 * 4860 * NIX AF Receive Channel Configuration Registers 4861 */ 4862union nixx_af_rx_chanx_cfg { 4863 u64 u; 4864 struct nixx_af_rx_chanx_cfg_s { 4865 u64 bpid : 9; 4866 u64 reserved_9_15 : 7; 4867 u64 bp_ena : 1; 4868 u64 sw_xoff : 1; 4869 u64 imp : 1; 4870 u64 reserved_19_63 : 45; 4871 } s; 4872 /* struct nixx_af_rx_chanx_cfg_s cn; */ 4873}; 4874 4875static inline u64 NIXX_AF_RX_CHANX_CFG(u64 a) 4876 __attribute__ ((pure, always_inline)); 4877static inline u64 NIXX_AF_RX_CHANX_CFG(u64 a) 4878{ 4879 return 0x1a30 + 0x8000 * a; 4880} 4881 4882/** 4883 * Register (RVU_PF_BAR0) nix#_af_rx_cpt#_credit 4884 * 4885 * INTERNAL: NIX AF Receive CPT Credit Register Internal: Not used; no 4886 * IPSEC fast-path. 4887 */ 4888union nixx_af_rx_cptx_credit { 4889 u64 u; 4890 struct nixx_af_rx_cptx_credit_s { 4891 u64 inst_cred_cnt : 22; 4892 u64 reserved_22_63 : 42; 4893 } s; 4894 /* struct nixx_af_rx_cptx_credit_s cn; */ 4895}; 4896 4897static inline u64 NIXX_AF_RX_CPTX_CREDIT(u64 a) 4898 __attribute__ ((pure, always_inline)); 4899static inline u64 NIXX_AF_RX_CPTX_CREDIT(u64 a) 4900{ 4901 return 0x360 + 8 * a; 4902} 4903 4904/** 4905 * Register (RVU_PF_BAR0) nix#_af_rx_cpt#_inst_qsel 4906 * 4907 * INTERNAL: NIX AF Receive CPT Instruction Queue Select Register 4908 * Internal: Not used; no IPSEC fast-path. 4909 */ 4910union nixx_af_rx_cptx_inst_qsel { 4911 u64 u; 4912 struct nixx_af_rx_cptx_inst_qsel_s { 4913 u64 slot : 8; 4914 u64 pf_func : 16; 4915 u64 reserved_24_63 : 40; 4916 } s; 4917 /* struct nixx_af_rx_cptx_inst_qsel_s cn; */ 4918}; 4919 4920static inline u64 NIXX_AF_RX_CPTX_INST_QSEL(u64 a) 4921 __attribute__ ((pure, always_inline)); 4922static inline u64 NIXX_AF_RX_CPTX_INST_QSEL(u64 a) 4923{ 4924 return 0x320 + 8 * a; 4925} 4926 4927/** 4928 * Register (RVU_PF_BAR0) nix#_af_rx_def_iip4 4929 * 4930 * NIX AF Receive Inner IPv4 Header Definition Register Defines layer 4931 * information in NPC_RESULT_S to identify an inner IPv4 header. 4932 * Typically the same as NPC_AF_PCK_DEF_IIP4. 4933 */ 4934union nixx_af_rx_def_iip4 { 4935 u64 u; 4936 struct nixx_af_rx_def_iip4_s { 4937 u64 ltype_mask : 4; 4938 u64 ltype_match : 4; 4939 u64 lid : 3; 4940 u64 reserved_11_63 : 53; 4941 } s; 4942 /* struct nixx_af_rx_def_iip4_s cn; */ 4943}; 4944 4945static inline u64 NIXX_AF_RX_DEF_IIP4(void) 4946 __attribute__ ((pure, always_inline)); 4947static inline u64 NIXX_AF_RX_DEF_IIP4(void) 4948{ 4949 return 0x220; 4950} 4951 4952/** 4953 * Register (RVU_PF_BAR0) nix#_af_rx_def_iip6 4954 * 4955 * NIX AF Receive Inner IPv6 Header Definition Register Defines layer 4956 * information in NPC_RESULT_S to identify an inner IPv6 header. 4957 */ 4958union nixx_af_rx_def_iip6 { 4959 u64 u; 4960 struct nixx_af_rx_def_iip6_s { 4961 u64 ltype_mask : 4; 4962 u64 ltype_match : 4; 4963 u64 lid : 3; 4964 u64 reserved_11_63 : 53; 4965 } s; 4966 /* struct nixx_af_rx_def_iip6_s cn; */ 4967}; 4968 4969static inline u64 NIXX_AF_RX_DEF_IIP6(void) 4970 __attribute__ ((pure, always_inline)); 4971static inline u64 NIXX_AF_RX_DEF_IIP6(void) 4972{ 4973 return 0x240; 4974} 4975 4976/** 4977 * Register (RVU_PF_BAR0) nix#_af_rx_def_ipsec# 4978 * 4979 * INTERNAL: NIX AF Receive IPSEC Header Definition Registers Internal: 4980 * Not used; no IPSEC fast-path. 4981 */ 4982union nixx_af_rx_def_ipsecx { 4983 u64 u; 4984 struct nixx_af_rx_def_ipsecx_s { 4985 u64 ltype_mask : 4; 4986 u64 ltype_match : 4; 4987 u64 lid : 3; 4988 u64 reserved_11 : 1; 4989 u64 spi_offset : 4; 4990 u64 spi_nz : 1; 4991 u64 reserved_17_63 : 47; 4992 } s; 4993 /* struct nixx_af_rx_def_ipsecx_s cn; */ 4994}; 4995 4996static inline u64 NIXX_AF_RX_DEF_IPSECX(u64 a) 4997 __attribute__ ((pure, always_inline)); 4998static inline u64 NIXX_AF_RX_DEF_IPSECX(u64 a) 4999{ 5000 return 0x2b0 + 8 * a; 5001} 5002 5003/** 5004 * Register (RVU_PF_BAR0) nix#_af_rx_def_isctp 5005 * 5006 * NIX AF Receive Inner SCTP Header Definition Register Defines layer 5007 * information in NPC_RESULT_S to identify an inner SCTP header. 5008 */ 5009union nixx_af_rx_def_isctp { 5010 u64 u; 5011 struct nixx_af_rx_def_isctp_s { 5012 u64 ltype_mask : 4; 5013 u64 ltype_match : 4; 5014 u64 lid : 3; 5015 u64 reserved_11_63 : 53; 5016 } s; 5017 /* struct nixx_af_rx_def_isctp_s cn; */ 5018}; 5019 5020static inline u64 NIXX_AF_RX_DEF_ISCTP(void) 5021 __attribute__ ((pure, always_inline)); 5022static inline u64 NIXX_AF_RX_DEF_ISCTP(void) 5023{ 5024 return 0x2a0; 5025} 5026 5027/** 5028 * Register (RVU_PF_BAR0) nix#_af_rx_def_itcp 5029 * 5030 * NIX AF Receive Inner TCP Header Definition Register Defines layer 5031 * information in NPC_RESULT_S to identify an inner TCP header. 5032 */ 5033union nixx_af_rx_def_itcp { 5034 u64 u; 5035 struct nixx_af_rx_def_itcp_s { 5036 u64 ltype_mask : 4; 5037 u64 ltype_match : 4; 5038 u64 lid : 3; 5039 u64 reserved_11_63 : 53; 5040 } s; 5041 /* struct nixx_af_rx_def_itcp_s cn; */ 5042}; 5043 5044static inline u64 NIXX_AF_RX_DEF_ITCP(void) 5045 __attribute__ ((pure, always_inline)); 5046static inline u64 NIXX_AF_RX_DEF_ITCP(void) 5047{ 5048 return 0x260; 5049} 5050 5051/** 5052 * Register (RVU_PF_BAR0) nix#_af_rx_def_iudp 5053 * 5054 * NIX AF Receive Inner UDP Header Definition Register Defines layer 5055 * information in NPC_RESULT_S to identify an inner UDP header. 5056 */ 5057union nixx_af_rx_def_iudp { 5058 u64 u; 5059 struct nixx_af_rx_def_iudp_s { 5060 u64 ltype_mask : 4; 5061 u64 ltype_match : 4; 5062 u64 lid : 3; 5063 u64 reserved_11_63 : 53; 5064 } s; 5065 /* struct nixx_af_rx_def_iudp_s cn; */ 5066}; 5067 5068static inline u64 NIXX_AF_RX_DEF_IUDP(void) 5069 __attribute__ ((pure, always_inline)); 5070static inline u64 NIXX_AF_RX_DEF_IUDP(void) 5071{ 5072 return 0x280; 5073} 5074 5075/** 5076 * Register (RVU_PF_BAR0) nix#_af_rx_def_oip4 5077 * 5078 * NIX AF Receive Outer IPv4 Header Definition Register Defines layer 5079 * information in NPC_RESULT_S to identify an outer IPv4 L3 header. 5080 * Typically the same as NPC_AF_PCK_DEF_OIP4. 5081 */ 5082union nixx_af_rx_def_oip4 { 5083 u64 u; 5084 struct nixx_af_rx_def_oip4_s { 5085 u64 ltype_mask : 4; 5086 u64 ltype_match : 4; 5087 u64 lid : 3; 5088 u64 reserved_11_63 : 53; 5089 } s; 5090 /* struct nixx_af_rx_def_oip4_s cn; */ 5091}; 5092 5093static inline u64 NIXX_AF_RX_DEF_OIP4(void) 5094 __attribute__ ((pure, always_inline)); 5095static inline u64 NIXX_AF_RX_DEF_OIP4(void) 5096{ 5097 return 0x210; 5098} 5099 5100/** 5101 * Register (RVU_PF_BAR0) nix#_af_rx_def_oip6 5102 * 5103 * NIX AF Receive Outer IPv6 Header Definition Register Defines layer 5104 * information in NPC_RESULT_S to identify an outer IPv6 header. 5105 * Typically the same as NPC_AF_PCK_DEF_OIP6. 5106 */ 5107union nixx_af_rx_def_oip6 { 5108 u64 u; 5109 struct nixx_af_rx_def_oip6_s { 5110 u64 ltype_mask : 4; 5111 u64 ltype_match : 4; 5112 u64 lid : 3; 5113 u64 reserved_11_63 : 53; 5114 } s; 5115 /* struct nixx_af_rx_def_oip6_s cn; */ 5116}; 5117 5118static inline u64 NIXX_AF_RX_DEF_OIP6(void) 5119 __attribute__ ((pure, always_inline)); 5120static inline u64 NIXX_AF_RX_DEF_OIP6(void) 5121{ 5122 return 0x230; 5123} 5124 5125/** 5126 * Register (RVU_PF_BAR0) nix#_af_rx_def_ol2 5127 * 5128 * NIX AF Receive Outer L2 Header Definition Register Defines layer 5129 * information in NPC_RESULT_S to identify an outer L2/Ethernet header. 5130 * Typically the same as NPC_AF_PCK_DEF_OL2. 5131 */ 5132union nixx_af_rx_def_ol2 { 5133 u64 u; 5134 struct nixx_af_rx_def_ol2_s { 5135 u64 ltype_mask : 4; 5136 u64 ltype_match : 4; 5137 u64 lid : 3; 5138 u64 reserved_11_63 : 53; 5139 } s; 5140 /* struct nixx_af_rx_def_ol2_s cn; */ 5141}; 5142 5143static inline u64 NIXX_AF_RX_DEF_OL2(void) 5144 __attribute__ ((pure, always_inline)); 5145static inline u64 NIXX_AF_RX_DEF_OL2(void) 5146{ 5147 return 0x200; 5148} 5149 5150/** 5151 * Register (RVU_PF_BAR0) nix#_af_rx_def_osctp 5152 * 5153 * NIX AF Receive Outer SCTP Header Definition Register Defines layer 5154 * information in NPC_RESULT_S to identify an outer SCTP header. 5155 */ 5156union nixx_af_rx_def_osctp { 5157 u64 u; 5158 struct nixx_af_rx_def_osctp_s { 5159 u64 ltype_mask : 4; 5160 u64 ltype_match : 4; 5161 u64 lid : 3; 5162 u64 reserved_11_63 : 53; 5163 } s; 5164 /* struct nixx_af_rx_def_osctp_s cn; */ 5165}; 5166 5167static inline u64 NIXX_AF_RX_DEF_OSCTP(void) 5168 __attribute__ ((pure, always_inline)); 5169static inline u64 NIXX_AF_RX_DEF_OSCTP(void) 5170{ 5171 return 0x290; 5172} 5173 5174/** 5175 * Register (RVU_PF_BAR0) nix#_af_rx_def_otcp 5176 * 5177 * NIX AF Receive Outer TCP Header Definition Register Defines layer 5178 * information in NPC_RESULT_S to identify an outer TCP header. 5179 */ 5180union nixx_af_rx_def_otcp { 5181 u64 u; 5182 struct nixx_af_rx_def_otcp_s { 5183 u64 ltype_mask : 4; 5184 u64 ltype_match : 4; 5185 u64 lid : 3; 5186 u64 reserved_11_63 : 53; 5187 } s; 5188 /* struct nixx_af_rx_def_otcp_s cn; */ 5189}; 5190 5191static inline u64 NIXX_AF_RX_DEF_OTCP(void) 5192 __attribute__ ((pure, always_inline)); 5193static inline u64 NIXX_AF_RX_DEF_OTCP(void) 5194{ 5195 return 0x250; 5196} 5197 5198/** 5199 * Register (RVU_PF_BAR0) nix#_af_rx_def_oudp 5200 * 5201 * NIX AF Receive Outer UDP Header Definition Register Defines layer 5202 * information in NPC_RESULT_S to identify an outer UDP header. 5203 */ 5204union nixx_af_rx_def_oudp { 5205 u64 u; 5206 struct nixx_af_rx_def_oudp_s { 5207 u64 ltype_mask : 4; 5208 u64 ltype_match : 4; 5209 u64 lid : 3; 5210 u64 reserved_11_63 : 53; 5211 } s; 5212 /* struct nixx_af_rx_def_oudp_s cn; */ 5213}; 5214 5215static inline u64 NIXX_AF_RX_DEF_OUDP(void) 5216 __attribute__ ((pure, always_inline)); 5217static inline u64 NIXX_AF_RX_DEF_OUDP(void) 5218{ 5219 return 0x270; 5220} 5221 5222/** 5223 * Register (RVU_PF_BAR0) nix#_af_rx_flow_key_alg#_field# 5224 * 5225 * NIX AF Receive Flow Key Algorithm Field Registers A flow key algorithm 5226 * defines how the 40-byte FLOW_KEY is formed from the received packet 5227 * header. FLOW_KEY is formed using up to five header fields (this 5228 * register's last index) with up to 16 bytes per field. Header fields 5229 * must not overlap in FLOW_KEY. The algorithm (index {a} (ALG) of these 5230 * registers) is selected by NIX_RX_ACTION_S[FLOW_KEY_ALG] from the 5231 * packet's NPC_RESULT_S[ACTION]. Internal: 40-byte FLOW_KEY is wide 5232 * enough to support an IPv6 5-tuple that includes a VXLAN/GENEVE/NVGRE 5233 * tunnel ID, e.g: _ Source IP: 16B. _ Dest IP: 16B. _ Source port: 2B. _ 5234 * Dest port: 2B. _ Tunnel VNI/VSI: 3B. _ Total: 39B. 5235 */ 5236union nixx_af_rx_flow_key_algx_fieldx { 5237 u64 u; 5238 struct nixx_af_rx_flow_key_algx_fieldx_s { 5239 u64 key_offset : 6; 5240 u64 ln_mask : 1; 5241 u64 fn_mask : 1; 5242 u64 hdr_offset : 8; 5243 u64 bytesm1 : 5; 5244 u64 lid : 3; 5245 u64 reserved_24 : 1; 5246 u64 ena : 1; 5247 u64 sel_chan : 1; 5248 u64 ltype_mask : 4; 5249 u64 ltype_match : 4; 5250 u64 reserved_35_63 : 29; 5251 } s; 5252 /* struct nixx_af_rx_flow_key_algx_fieldx_s cn; */ 5253}; 5254 5255static inline u64 NIXX_AF_RX_FLOW_KEY_ALGX_FIELDX(u64 a, u64 b) 5256 __attribute__ ((pure, always_inline)); 5257static inline u64 NIXX_AF_RX_FLOW_KEY_ALGX_FIELDX(u64 a, u64 b) 5258{ 5259 return 0x1800 + 0x40000 * a + 8 * b; 5260} 5261 5262/** 5263 * Register (RVU_PF_BAR0) nix#_af_rx_ipsec_gen_cfg 5264 * 5265 * INTERNAL: NIX AF Receive IPSEC General Configuration Register 5266 * Internal: Not used; no IPSEC fast-path. 5267 */ 5268union nixx_af_rx_ipsec_gen_cfg { 5269 u64 u; 5270 struct nixx_af_rx_ipsec_gen_cfg_s { 5271 u64 param2 : 16; 5272 u64 param1 : 16; 5273 u64 opcode : 16; 5274 u64 egrp : 3; 5275 u64 reserved_51_63 : 13; 5276 } s; 5277 /* struct nixx_af_rx_ipsec_gen_cfg_s cn; */ 5278}; 5279 5280static inline u64 NIXX_AF_RX_IPSEC_GEN_CFG(void) 5281 __attribute__ ((pure, always_inline)); 5282static inline u64 NIXX_AF_RX_IPSEC_GEN_CFG(void) 5283{ 5284 return 0x300; 5285} 5286 5287/** 5288 * Register (RVU_PF_BAR0) nix#_af_rx_link#_cfg 5289 * 5290 * NIX AF Receive Link Configuration Registers Index enumerated by 5291 * NIX_LINK_E. 5292 */ 5293union nixx_af_rx_linkx_cfg { 5294 u64 u; 5295 struct nixx_af_rx_linkx_cfg_s { 5296 u64 minlen : 16; 5297 u64 maxlen : 16; 5298 u64 reserved_32_63 : 32; 5299 } s; 5300 /* struct nixx_af_rx_linkx_cfg_s cn; */ 5301}; 5302 5303static inline u64 NIXX_AF_RX_LINKX_CFG(u64 a) 5304 __attribute__ ((pure, always_inline)); 5305static inline u64 NIXX_AF_RX_LINKX_CFG(u64 a) 5306{ 5307 return 0x540 + 0x10000 * a; 5308} 5309 5310/** 5311 * Register (RVU_PF_BAR0) nix#_af_rx_link#_sl#_spkt_cnt 5312 * 5313 * INTERNAL: NIX Receive Software Sync Link Packet Count Registers For 5314 * diagnostic use only for debug of NIX_AF_RX_SW_SYNC[ENA] function. LINK 5315 * index is enumerated by NIX_LINK_E. For the internal multicast/mirror 5316 * link (NIX_LINK_E::MC), SL index is zero for multicast replay, one for 5317 * mirror replay. SL index one is reserved for all other links. 5318 * Internal: 802.3br frame preemption/express path is defeatured. Old 5319 * definition of SL index: SL index is zero for non-express packets, one 5320 * for express packets. For the internal NIX_LINK_E::MC, SL index is zero 5321 * for multicast replay, one for mirror replay. 5322 */ 5323union nixx_af_rx_linkx_slx_spkt_cnt { 5324 u64 u; 5325 struct nixx_af_rx_linkx_slx_spkt_cnt_s { 5326 u64 in_cnt : 20; 5327 u64 reserved_20_31 : 12; 5328 u64 out_cnt : 20; 5329 u64 reserved_52_63 : 12; 5330 } s; 5331 /* struct nixx_af_rx_linkx_slx_spkt_cnt_s cn; */ 5332}; 5333 5334static inline u64 NIXX_AF_RX_LINKX_SLX_SPKT_CNT(u64 a, u64 b) 5335 __attribute__ ((pure, always_inline)); 5336static inline u64 NIXX_AF_RX_LINKX_SLX_SPKT_CNT(u64 a, u64 b) 5337{ 5338 return 0x500 + 0x10000 * a + 8 * b; 5339} 5340 5341/** 5342 * Register (RVU_PF_BAR0) nix#_af_rx_link#_wrr_cfg 5343 * 5344 * NIX AF Receive Link Weighted Round Robin Configuration Registers Index 5345 * enumerated by NIX_LINK_E. 5346 */ 5347union nixx_af_rx_linkx_wrr_cfg { 5348 u64 u; 5349 struct nixx_af_rx_linkx_wrr_cfg_s { 5350 u64 weight : 8; 5351 u64 reserved_8_63 : 56; 5352 } s; 5353 /* struct nixx_af_rx_linkx_wrr_cfg_s cn; */ 5354}; 5355 5356static inline u64 NIXX_AF_RX_LINKX_WRR_CFG(u64 a) 5357 __attribute__ ((pure, always_inline)); 5358static inline u64 NIXX_AF_RX_LINKX_WRR_CFG(u64 a) 5359{ 5360 return 0x560 + 0x10000 * a; 5361} 5362 5363/** 5364 * Register (RVU_PF_BAR0) nix#_af_rx_mcast_base 5365 * 5366 * NIX AF Receive Multicast/Mirror Table Base Address Register This 5367 * register specifies the base AF IOVA of the receive multicast/mirror 5368 * table in NDC/LLC/DRAM. The table consists of 1 \<\< 5369 * (NIX_AF_RX_MCAST_CFG[SIZE] + 8) contiguous NIX_RX_MCE_S structures. 5370 * The size of each structure is 1 \<\< NIX_AF_CONST3[MCE_LOG2BYTES]. 5371 * The table contains multicast/mirror replication lists. Each list 5372 * consists of linked entries with NIX_RX_MCE_S[EOL] = 1 in the last 5373 * entry. All lists must reside within the table size specified by 5374 * NIX_AF_RX_MCAST_CFG[SIZE]. A mirror replication list will typically 5375 * consist of two entries, but that is not checked or enforced by 5376 * hardware. A receive packet is multicast when the action returned by 5377 * NPC has NIX_RX_ACTION_S[OP] = NIX_RX_ACTIONOP_E::MCAST. A receive 5378 * packet is mirrored when the action returned by NPC has 5379 * NIX_RX_ACTION_S[OP] = NIX_RX_ACTIONOP_E::MIRROR. In both cases, 5380 * NIX_RX_ACTION_S[INDEX] specifies the index of the replication list's 5381 * first NIX_RX_MCE_S in the table, and a linked entry with 5382 * NIX_RX_MCE_S[EOL] = 1 indicates the end of list. If a mirrored flow 5383 * is part of a multicast replication list, software should include the 5384 * two mirror entries in that list. Internal: A multicast list may have 5385 * multiple entries for the same LF (e.g. for future RoCE/IB multicast). 5386 */ 5387union nixx_af_rx_mcast_base { 5388 u64 u; 5389 struct nixx_af_rx_mcast_base_s { 5390 u64 reserved_0_6 : 7; 5391 u64 addr : 46; 5392 u64 reserved_53_63 : 11; 5393 } s; 5394 /* struct nixx_af_rx_mcast_base_s cn; */ 5395}; 5396 5397static inline u64 NIXX_AF_RX_MCAST_BASE(void) 5398 __attribute__ ((pure, always_inline)); 5399static inline u64 NIXX_AF_RX_MCAST_BASE(void) 5400{ 5401 return 0x100; 5402} 5403 5404/** 5405 * Register (RVU_PF_BAR0) nix#_af_rx_mcast_buf_base 5406 * 5407 * NIX AF Receive Multicast Buffer Base Address Register This register 5408 * specifies the base AF IOVA of the receive multicast buffers in 5409 * NDC/LLC/DRAM. These buffers are used to temporarily store packets 5410 * whose action returned by NPC has NIX_RX_ACTION_S[OP] = 5411 * NIX_RX_ACTIONOP_E::MCAST. The number of buffers is configured by 5412 * NIX_AF_RX_MCAST_BUF_CFG[SIZE]. If the number of free buffers is 5413 * insufficient for a received multicast packet, hardware tail drops the 5414 * packet and sets NIX_AF_GEN_INT[RX_MCAST_DROP]. Hardware prioritizes 5415 * the processing of RX mirror packets over RX multicast packets. 5416 */ 5417union nixx_af_rx_mcast_buf_base { 5418 u64 u; 5419 struct nixx_af_rx_mcast_buf_base_s { 5420 u64 reserved_0_6 : 7; 5421 u64 addr : 46; 5422 u64 reserved_53_63 : 11; 5423 } s; 5424 /* struct nixx_af_rx_mcast_buf_base_s cn; */ 5425}; 5426 5427static inline u64 NIXX_AF_RX_MCAST_BUF_BASE(void) 5428 __attribute__ ((pure, always_inline)); 5429static inline u64 NIXX_AF_RX_MCAST_BUF_BASE(void) 5430{ 5431 return 0x120; 5432} 5433 5434/** 5435 * Register (RVU_PF_BAR0) nix#_af_rx_mcast_buf_cfg 5436 * 5437 * NIX AF Receive Multicast Buffer Configuration Register See 5438 * NIX_AF_RX_MCAST_BUF_BASE. 5439 */ 5440union nixx_af_rx_mcast_buf_cfg { 5441 u64 u; 5442 struct nixx_af_rx_mcast_buf_cfg_s { 5443 u64 size : 4; 5444 u64 way_mask : 16; 5445 u64 caching : 1; 5446 u64 reserved_21_23 : 3; 5447 u64 npc_replay_pkind : 6; 5448 u64 reserved_30_31 : 2; 5449 u64 free_buf_level : 11; 5450 u64 reserved_43_61 : 19; 5451 u64 busy : 1; 5452 u64 ena : 1; 5453 } s; 5454 struct nixx_af_rx_mcast_buf_cfg_cn96xxp1 { 5455 u64 size : 4; 5456 u64 way_mask : 16; 5457 u64 caching : 1; 5458 u64 reserved_21_23 : 3; 5459 u64 npc_replay_pkind : 6; 5460 u64 reserved_30_31 : 2; 5461 u64 free_buf_level : 11; 5462 u64 reserved_43_61 : 19; 5463 u64 reserved_62 : 1; 5464 u64 ena : 1; 5465 } cn96xxp1; 5466 /* struct nixx_af_rx_mcast_buf_cfg_s cn96xxp3; */ 5467 struct nixx_af_rx_mcast_buf_cfg_cnf95xxp1 { 5468 u64 size : 4; 5469 u64 way_mask : 16; 5470 u64 caching : 1; 5471 u64 reserved_21_23 : 3; 5472 u64 npc_replay_pkind : 6; 5473 u64 reserved_30_31 : 2; 5474 u64 free_buf_level : 11; 5475 u64 reserved_43_62 : 20; 5476 u64 ena : 1; 5477 } cnf95xxp1; 5478 /* struct nixx_af_rx_mcast_buf_cfg_s cnf95xxp2; */ 5479}; 5480 5481static inline u64 NIXX_AF_RX_MCAST_BUF_CFG(void) 5482 __attribute__ ((pure, always_inline)); 5483static inline u64 NIXX_AF_RX_MCAST_BUF_CFG(void) 5484{ 5485 return 0x130; 5486} 5487 5488/** 5489 * Register (RVU_PF_BAR0) nix#_af_rx_mcast_cfg 5490 * 5491 * NIX AF Receive Multicast/Mirror Table Configuration Register See 5492 * NIX_AF_RX_MCAST_BASE. 5493 */ 5494union nixx_af_rx_mcast_cfg { 5495 u64 u; 5496 struct nixx_af_rx_mcast_cfg_s { 5497 u64 size : 4; 5498 u64 max_list_lenm1 : 8; 5499 u64 reserved_12_19 : 8; 5500 u64 way_mask : 16; 5501 u64 caching : 1; 5502 u64 reserved_37_63 : 27; 5503 } s; 5504 /* struct nixx_af_rx_mcast_cfg_s cn; */ 5505}; 5506 5507static inline u64 NIXX_AF_RX_MCAST_CFG(void) 5508 __attribute__ ((pure, always_inline)); 5509static inline u64 NIXX_AF_RX_MCAST_CFG(void) 5510{ 5511 return 0x110; 5512} 5513 5514/** 5515 * Register (RVU_PF_BAR0) nix#_af_rx_mirror_buf_base 5516 * 5517 * NIX AF Receive Mirror Buffer Base Address Register This register 5518 * specifies the base AF IOVA of the receive mirror buffers in 5519 * NDC/LLC/DRAM. These buffers are used to temporarily store packets 5520 * whose action returned by NPC has NIX_RX_ACTION_S[OP] = 5521 * NIX_RX_ACTIONOP_E::MIRROR. The number of buffers is configured by 5522 * NIX_AF_RX_MIRROR_BUF_CFG[SIZE]. If the number of free buffers is 5523 * insufficient for a received multicast packet, hardware tail drops the 5524 * packet and sets NIX_AF_GEN_INT[RX_MIRROR_DROP]. Hardware prioritizes 5525 * the processing of RX mirror packets over RX multicast packets. 5526 */ 5527union nixx_af_rx_mirror_buf_base { 5528 u64 u; 5529 struct nixx_af_rx_mirror_buf_base_s { 5530 u64 reserved_0_6 : 7; 5531 u64 addr : 46; 5532 u64 reserved_53_63 : 11; 5533 } s; 5534 /* struct nixx_af_rx_mirror_buf_base_s cn; */ 5535}; 5536 5537static inline u64 NIXX_AF_RX_MIRROR_BUF_BASE(void) 5538 __attribute__ ((pure, always_inline)); 5539static inline u64 NIXX_AF_RX_MIRROR_BUF_BASE(void) 5540{ 5541 return 0x140; 5542} 5543 5544/** 5545 * Register (RVU_PF_BAR0) nix#_af_rx_mirror_buf_cfg 5546 * 5547 * NIX AF Receive Mirror Buffer Configuration Register See 5548 * NIX_AF_RX_MIRROR_BUF_BASE. 5549 */ 5550union nixx_af_rx_mirror_buf_cfg { 5551 u64 u; 5552 struct nixx_af_rx_mirror_buf_cfg_s { 5553 u64 size : 4; 5554 u64 way_mask : 16; 5555 u64 caching : 1; 5556 u64 reserved_21_23 : 3; 5557 u64 npc_replay_pkind : 6; 5558 u64 reserved_30_31 : 2; 5559 u64 free_buf_level : 11; 5560 u64 reserved_43_61 : 19; 5561 u64 busy : 1; 5562 u64 ena : 1; 5563 } s; 5564 struct nixx_af_rx_mirror_buf_cfg_cn96xxp1 { 5565 u64 size : 4; 5566 u64 way_mask : 16; 5567 u64 caching : 1; 5568 u64 reserved_21_23 : 3; 5569 u64 npc_replay_pkind : 6; 5570 u64 reserved_30_31 : 2; 5571 u64 free_buf_level : 11; 5572 u64 reserved_43_61 : 19; 5573 u64 reserved_62 : 1; 5574 u64 ena : 1; 5575 } cn96xxp1; 5576 /* struct nixx_af_rx_mirror_buf_cfg_s cn96xxp3; */ 5577 struct nixx_af_rx_mirror_buf_cfg_cnf95xxp1 { 5578 u64 size : 4; 5579 u64 way_mask : 16; 5580 u64 caching : 1; 5581 u64 reserved_21_23 : 3; 5582 u64 npc_replay_pkind : 6; 5583 u64 reserved_30_31 : 2; 5584 u64 free_buf_level : 11; 5585 u64 reserved_43_62 : 20; 5586 u64 ena : 1; 5587 } cnf95xxp1; 5588 /* struct nixx_af_rx_mirror_buf_cfg_s cnf95xxp2; */ 5589}; 5590 5591static inline u64 NIXX_AF_RX_MIRROR_BUF_CFG(void) 5592 __attribute__ ((pure, always_inline)); 5593static inline u64 NIXX_AF_RX_MIRROR_BUF_CFG(void) 5594{ 5595 return 0x148; 5596} 5597 5598/** 5599 * Register (RVU_PF_BAR0) nix#_af_rx_npc_mc_drop 5600 * 5601 * NIX AF Multicast Drop Statistics Register The counter increments for 5602 * every dropped MC packet marked by the NPC. 5603 */ 5604union nixx_af_rx_npc_mc_drop { 5605 u64 u; 5606 struct nixx_af_rx_npc_mc_drop_s { 5607 u64 stat : 48; 5608 u64 reserved_48_63 : 16; 5609 } s; 5610 /* struct nixx_af_rx_npc_mc_drop_s cn; */ 5611}; 5612 5613static inline u64 NIXX_AF_RX_NPC_MC_DROP(void) 5614 __attribute__ ((pure, always_inline)); 5615static inline u64 NIXX_AF_RX_NPC_MC_DROP(void) 5616{ 5617 return 0x4710; 5618} 5619 5620/** 5621 * Register (RVU_PF_BAR0) nix#_af_rx_npc_mc_rcv 5622 * 5623 * NIX AF Multicast Receive Statistics Register The counter increments 5624 * for every received MC packet marked by the NPC. 5625 */ 5626union nixx_af_rx_npc_mc_rcv { 5627 u64 u; 5628 struct nixx_af_rx_npc_mc_rcv_s { 5629 u64 stat : 48; 5630 u64 reserved_48_63 : 16; 5631 } s; 5632 /* struct nixx_af_rx_npc_mc_rcv_s cn; */ 5633}; 5634 5635static inline u64 NIXX_AF_RX_NPC_MC_RCV(void) 5636 __attribute__ ((pure, always_inline)); 5637static inline u64 NIXX_AF_RX_NPC_MC_RCV(void) 5638{ 5639 return 0x4700; 5640} 5641 5642/** 5643 * Register (RVU_PF_BAR0) nix#_af_rx_npc_mirror_drop 5644 * 5645 * NIX AF Mirror Drop Statistics Register The counter increments for 5646 * every dropped MIRROR packet marked by the NPC. 5647 */ 5648union nixx_af_rx_npc_mirror_drop { 5649 u64 u; 5650 struct nixx_af_rx_npc_mirror_drop_s { 5651 u64 stat : 48; 5652 u64 reserved_48_63 : 16; 5653 } s; 5654 /* struct nixx_af_rx_npc_mirror_drop_s cn; */ 5655}; 5656 5657static inline u64 NIXX_AF_RX_NPC_MIRROR_DROP(void) 5658 __attribute__ ((pure, always_inline)); 5659static inline u64 NIXX_AF_RX_NPC_MIRROR_DROP(void) 5660{ 5661 return 0x4730; 5662} 5663 5664/** 5665 * Register (RVU_PF_BAR0) nix#_af_rx_npc_mirror_rcv 5666 * 5667 * NIX AF Mirror Receive Statistics Register The counter increments for 5668 * every received MIRROR packet marked by the NPC. 5669 */ 5670union nixx_af_rx_npc_mirror_rcv { 5671 u64 u; 5672 struct nixx_af_rx_npc_mirror_rcv_s { 5673 u64 stat : 48; 5674 u64 reserved_48_63 : 16; 5675 } s; 5676 /* struct nixx_af_rx_npc_mirror_rcv_s cn; */ 5677}; 5678 5679static inline u64 NIXX_AF_RX_NPC_MIRROR_RCV(void) 5680 __attribute__ ((pure, always_inline)); 5681static inline u64 NIXX_AF_RX_NPC_MIRROR_RCV(void) 5682{ 5683 return 0x4720; 5684} 5685 5686/** 5687 * Register (RVU_PF_BAR0) nix#_af_rx_sw_sync 5688 * 5689 * NIX AF Receive Software Sync Register 5690 */ 5691union nixx_af_rx_sw_sync { 5692 u64 u; 5693 struct nixx_af_rx_sw_sync_s { 5694 u64 ena : 1; 5695 u64 reserved_1_63 : 63; 5696 } s; 5697 /* struct nixx_af_rx_sw_sync_s cn; */ 5698}; 5699 5700static inline u64 NIXX_AF_RX_SW_SYNC(void) 5701 __attribute__ ((pure, always_inline)); 5702static inline u64 NIXX_AF_RX_SW_SYNC(void) 5703{ 5704 return 0x550; 5705} 5706 5707/** 5708 * Register (RVU_PF_BAR0) nix#_af_sdp_hw_xoff# 5709 * 5710 * NIX AF SDP Transmit Link Hardware Controlled XOFF Registers . 5711 */ 5712union nixx_af_sdp_hw_xoffx { 5713 u64 u; 5714 struct nixx_af_sdp_hw_xoffx_s { 5715 u64 chan_xoff : 64; 5716 } s; 5717 /* struct nixx_af_sdp_hw_xoffx_s cn; */ 5718}; 5719 5720static inline u64 NIXX_AF_SDP_HW_XOFFX(u64 a) 5721 __attribute__ ((pure, always_inline)); 5722static inline u64 NIXX_AF_SDP_HW_XOFFX(u64 a) 5723{ 5724 return 0xac0 + 8 * a; 5725} 5726 5727/** 5728 * Register (RVU_PF_BAR0) nix#_af_sdp_link_credit 5729 * 5730 * NIX AF Transmit Link SDP Credit Register This register tracks SDP link 5731 * credits. 5732 */ 5733union nixx_af_sdp_link_credit { 5734 u64 u; 5735 struct nixx_af_sdp_link_credit_s { 5736 u64 reserved_0 : 1; 5737 u64 cc_enable : 1; 5738 u64 cc_packet_cnt : 10; 5739 u64 cc_unit_cnt : 20; 5740 u64 reserved_32_62 : 31; 5741 u64 pse_pkt_id_lmt : 1; 5742 } s; 5743 struct nixx_af_sdp_link_credit_cn96xx { 5744 u64 reserved_0 : 1; 5745 u64 cc_enable : 1; 5746 u64 cc_packet_cnt : 10; 5747 u64 cc_unit_cnt : 20; 5748 u64 reserved_32_62 : 31; 5749 u64 reserved_63 : 1; 5750 } cn96xx; 5751 /* struct nixx_af_sdp_link_credit_s cnf95xx; */ 5752}; 5753 5754static inline u64 NIXX_AF_SDP_LINK_CREDIT(void) 5755 __attribute__ ((pure, always_inline)); 5756static inline u64 NIXX_AF_SDP_LINK_CREDIT(void) 5757{ 5758 return 0xa40; 5759} 5760 5761/** 5762 * Register (RVU_PF_BAR0) nix#_af_sdp_sw_xoff# 5763 * 5764 * INTERNAL: NIX AF SDP Transmit Link Software Controlled XOFF Registers 5765 * Internal: Defeatured registers. Software should use 5766 * NIX_AF_TL4()_SW_XOFF registers instead. 5767 */ 5768union nixx_af_sdp_sw_xoffx { 5769 u64 u; 5770 struct nixx_af_sdp_sw_xoffx_s { 5771 u64 chan_xoff : 64; 5772 } s; 5773 /* struct nixx_af_sdp_sw_xoffx_s cn; */ 5774}; 5775 5776static inline u64 NIXX_AF_SDP_SW_XOFFX(u64 a) 5777 __attribute__ ((pure, always_inline)); 5778static inline u64 NIXX_AF_SDP_SW_XOFFX(u64 a) 5779{ 5780 return 0xa60 + 8 * a; 5781} 5782 5783/** 5784 * Register (RVU_PF_BAR0) nix#_af_sdp_tx_fifo_status 5785 * 5786 * NIX AF SDP Transmit FIFO Status Register Status of FIFO which 5787 * transmits packets to SDP. 5788 */ 5789union nixx_af_sdp_tx_fifo_status { 5790 u64 u; 5791 struct nixx_af_sdp_tx_fifo_status_s { 5792 u64 count : 12; 5793 u64 reserved_12_63 : 52; 5794 } s; 5795 /* struct nixx_af_sdp_tx_fifo_status_s cn; */ 5796}; 5797 5798static inline u64 NIXX_AF_SDP_TX_FIFO_STATUS(void) 5799 __attribute__ ((pure, always_inline)); 5800static inline u64 NIXX_AF_SDP_TX_FIFO_STATUS(void) 5801{ 5802 return 0x650; 5803} 5804 5805/** 5806 * Register (RVU_PF_BAR0) nix#_af_seb_active_cycles_pc# 5807 * 5808 * NIX AF Active Cycles Register These registers are indexed by the 5809 * conditional clock domain number. 5810 */ 5811union nixx_af_seb_active_cycles_pcx { 5812 u64 u; 5813 struct nixx_af_seb_active_cycles_pcx_s { 5814 u64 act_cyc : 64; 5815 } s; 5816 /* struct nixx_af_seb_active_cycles_pcx_s cn; */ 5817}; 5818 5819static inline u64 NIXX_AF_SEB_ACTIVE_CYCLES_PCX(u64 a) 5820 __attribute__ ((pure, always_inline)); 5821static inline u64 NIXX_AF_SEB_ACTIVE_CYCLES_PCX(u64 a) 5822{ 5823 return 0x6c0 + 8 * a; 5824} 5825 5826/** 5827 * Register (RVU_PF_BAR0) nix#_af_seb_bp_test 5828 * 5829 * INTERNAL: NIX AF SEB Backpressure Test Register 5830 */ 5831union nixx_af_seb_bp_test { 5832 u64 u; 5833 struct nixx_af_seb_bp_test_s { 5834 u64 lfsr_freq : 12; 5835 u64 reserved_12_15 : 4; 5836 u64 bp_cfg : 14; 5837 u64 reserved_30_47 : 18; 5838 u64 enable : 7; 5839 u64 reserved_55_63 : 9; 5840 } s; 5841 /* struct nixx_af_seb_bp_test_s cn; */ 5842}; 5843 5844static inline u64 NIXX_AF_SEB_BP_TEST(void) 5845 __attribute__ ((pure, always_inline)); 5846static inline u64 NIXX_AF_SEB_BP_TEST(void) 5847{ 5848 return 0x630; 5849} 5850 5851/** 5852 * Register (RVU_PF_BAR0) nix#_af_seb_cfg 5853 * 5854 * NIX SEB Configuration Register 5855 */ 5856union nixx_af_seb_cfg { 5857 u64 u; 5858 struct nixx_af_seb_cfg_s { 5859 u64 sg_ndc_sel : 1; 5860 u64 reserved_1_63 : 63; 5861 } s; 5862 /* struct nixx_af_seb_cfg_s cn; */ 5863}; 5864 5865static inline u64 NIXX_AF_SEB_CFG(void) 5866 __attribute__ ((pure, always_inline)); 5867static inline u64 NIXX_AF_SEB_CFG(void) 5868{ 5869 return 0x5f0; 5870} 5871 5872/** 5873 * Register (RVU_PF_BAR0) nix#_af_seb_eco 5874 * 5875 * INTERNAL: AF SEB ECO Register 5876 */ 5877union nixx_af_seb_eco { 5878 u64 u; 5879 struct nixx_af_seb_eco_s { 5880 u64 eco_rw : 64; 5881 } s; 5882 /* struct nixx_af_seb_eco_s cn; */ 5883}; 5884 5885static inline u64 NIXX_AF_SEB_ECO(void) 5886 __attribute__ ((pure, always_inline)); 5887static inline u64 NIXX_AF_SEB_ECO(void) 5888{ 5889 return 0x5c0; 5890} 5891 5892/** 5893 * Register (RVU_PF_BAR0) nix#_af_seb_pipe_bp_test# 5894 * 5895 * INTERNAL: NIX AF SEB Pipe Backpressure Test Registers 5896 */ 5897union nixx_af_seb_pipe_bp_testx { 5898 u64 u; 5899 struct nixx_af_seb_pipe_bp_testx_s { 5900 u64 lfsr_freq : 12; 5901 u64 reserved_12_15 : 4; 5902 u64 bp_cfg : 24; 5903 u64 reserved_40_47 : 8; 5904 u64 enable : 12; 5905 u64 reserved_60_63 : 4; 5906 } s; 5907 /* struct nixx_af_seb_pipe_bp_testx_s cn; */ 5908}; 5909 5910static inline u64 NIXX_AF_SEB_PIPE_BP_TESTX(u64 a) 5911 __attribute__ ((pure, always_inline)); 5912static inline u64 NIXX_AF_SEB_PIPE_BP_TESTX(u64 a) 5913{ 5914 return 0x600 + 0x10 * a; 5915} 5916 5917/** 5918 * Register (RVU_PF_BAR0) nix#_af_seb_pipeb_bp_test# 5919 * 5920 * INTERNAL: NIX AF SEB Pipe Backpressure Test Registers 5921 */ 5922union nixx_af_seb_pipeb_bp_testx { 5923 u64 u; 5924 struct nixx_af_seb_pipeb_bp_testx_s { 5925 u64 lfsr_freq : 12; 5926 u64 reserved_12_15 : 4; 5927 u64 bp_cfg : 18; 5928 u64 reserved_34_47 : 14; 5929 u64 enable : 9; 5930 u64 reserved_57_63 : 7; 5931 } s; 5932 /* struct nixx_af_seb_pipeb_bp_testx_s cn; */ 5933}; 5934 5935static inline u64 NIXX_AF_SEB_PIPEB_BP_TESTX(u64 a) 5936 __attribute__ ((pure, always_inline)); 5937static inline u64 NIXX_AF_SEB_PIPEB_BP_TESTX(u64 a) 5938{ 5939 return 0x608 + 0x10 * a; 5940} 5941 5942/** 5943 * Register (RVU_PF_BAR0) nix#_af_seb_wd_tick_divider 5944 * 5945 * INTERNAL: NIX AF SEB TSTMP Watchdog Tick Divider Register 5946 */ 5947union nixx_af_seb_wd_tick_divider { 5948 u64 u; 5949 struct nixx_af_seb_wd_tick_divider_s { 5950 u64 tick_div_cfg : 7; 5951 u64 reserved_7_63 : 57; 5952 } s; 5953 /* struct nixx_af_seb_wd_tick_divider_s cn; */ 5954}; 5955 5956static inline u64 NIXX_AF_SEB_WD_TICK_DIVIDER(void) 5957 __attribute__ ((pure, always_inline)); 5958static inline u64 NIXX_AF_SEB_WD_TICK_DIVIDER(void) 5959{ 5960 return 0x6f0; 5961} 5962 5963/** 5964 * Register (RVU_PF_BAR0) nix#_af_smq#_cfg 5965 * 5966 * NIX AF SQM PSE Queue Configuration Registers 5967 */ 5968union nixx_af_smqx_cfg { 5969 u64 u; 5970 struct nixx_af_smqx_cfg_s { 5971 u64 minlen : 7; 5972 u64 desc_shp_ctl_dis : 1; 5973 u64 maxlen : 16; 5974 u64 lf : 7; 5975 u64 reserved_31_35 : 5; 5976 u64 max_vtag_ins : 3; 5977 u64 rr_minlen : 9; 5978 u64 express : 1; 5979 u64 flush : 1; 5980 u64 enq_xoff : 1; 5981 u64 pri_thr : 6; 5982 u64 reserved_57_63 : 7; 5983 } s; 5984 /* struct nixx_af_smqx_cfg_s cn; */ 5985}; 5986 5987static inline u64 NIXX_AF_SMQX_CFG(u64 a) 5988 __attribute__ ((pure, always_inline)); 5989static inline u64 NIXX_AF_SMQX_CFG(u64 a) 5990{ 5991 return 0x700 + 0x10000 * a; 5992} 5993 5994/** 5995 * Register (RVU_PF_BAR0) nix#_af_smq#_head 5996 * 5997 * NIX AF SQM SMQ Head Register These registers track the head of the SMQ 5998 * linked list. 5999 */ 6000union nixx_af_smqx_head { 6001 u64 u; 6002 struct nixx_af_smqx_head_s { 6003 u64 sq_idx : 20; 6004 u64 valid : 1; 6005 u64 reserved_21_63 : 43; 6006 } s; 6007 /* struct nixx_af_smqx_head_s cn; */ 6008}; 6009 6010static inline u64 NIXX_AF_SMQX_HEAD(u64 a) 6011 __attribute__ ((pure, always_inline)); 6012static inline u64 NIXX_AF_SMQX_HEAD(u64 a) 6013{ 6014 return 0x710 + 0x10000 * a; 6015} 6016 6017/** 6018 * Register (RVU_PF_BAR0) nix#_af_smq#_nxt_head 6019 * 6020 * NIX AF SQM SMQ Next Head Register These registers track the next head 6021 * of the SMQ linked list. 6022 */ 6023union nixx_af_smqx_nxt_head { 6024 u64 u; 6025 struct nixx_af_smqx_nxt_head_s { 6026 u64 sq_idx : 20; 6027 u64 valid : 1; 6028 u64 reserved_21_63 : 43; 6029 } s; 6030 /* struct nixx_af_smqx_nxt_head_s cn; */ 6031}; 6032 6033static inline u64 NIXX_AF_SMQX_NXT_HEAD(u64 a) 6034 __attribute__ ((pure, always_inline)); 6035static inline u64 NIXX_AF_SMQX_NXT_HEAD(u64 a) 6036{ 6037 return 0x740 + 0x10000 * a; 6038} 6039 6040/** 6041 * Register (RVU_PF_BAR0) nix#_af_smq#_status 6042 * 6043 * NIX AF SQM SMQ Status Register These registers track the status of the 6044 * SMQ FIFO. 6045 */ 6046union nixx_af_smqx_status { 6047 u64 u; 6048 struct nixx_af_smqx_status_s { 6049 u64 level : 7; 6050 u64 reserved_7_63 : 57; 6051 } s; 6052 /* struct nixx_af_smqx_status_s cn; */ 6053}; 6054 6055static inline u64 NIXX_AF_SMQX_STATUS(u64 a) 6056 __attribute__ ((pure, always_inline)); 6057static inline u64 NIXX_AF_SMQX_STATUS(u64 a) 6058{ 6059 return 0x730 + 0x10000 * a; 6060} 6061 6062/** 6063 * Register (RVU_PF_BAR0) nix#_af_smq#_tail 6064 * 6065 * NIX AF SQM SMQ Head Register These registers track the tail of SMQ 6066 * linked list. 6067 */ 6068union nixx_af_smqx_tail { 6069 u64 u; 6070 struct nixx_af_smqx_tail_s { 6071 u64 sq_idx : 20; 6072 u64 valid : 1; 6073 u64 reserved_21_63 : 43; 6074 } s; 6075 /* struct nixx_af_smqx_tail_s cn; */ 6076}; 6077 6078static inline u64 NIXX_AF_SMQX_TAIL(u64 a) 6079 __attribute__ ((pure, always_inline)); 6080static inline u64 NIXX_AF_SMQX_TAIL(u64 a) 6081{ 6082 return 0x720 + 0x10000 * a; 6083} 6084 6085/** 6086 * Register (RVU_PF_BAR0) nix#_af_sq_const 6087 * 6088 * NIX AF SQ Constants Register This register contains constants for 6089 * software discovery. 6090 */ 6091union nixx_af_sq_const { 6092 u64 u; 6093 struct nixx_af_sq_const_s { 6094 u64 queues_per_lf : 24; 6095 u64 smq_depth : 10; 6096 u64 sqb_size : 16; 6097 u64 reserved_50_63 : 14; 6098 } s; 6099 /* struct nixx_af_sq_const_s cn; */ 6100}; 6101 6102static inline u64 NIXX_AF_SQ_CONST(void) 6103 __attribute__ ((pure, always_inline)); 6104static inline u64 NIXX_AF_SQ_CONST(void) 6105{ 6106 return 0x40; 6107} 6108 6109/** 6110 * Register (RVU_PF_BAR0) nix#_af_sqm_active_cycles_pc 6111 * 6112 * NIX AF SQM Active Cycles Register These registers are indexed by the 6113 * conditional clock domain number. 6114 */ 6115union nixx_af_sqm_active_cycles_pc { 6116 u64 u; 6117 struct nixx_af_sqm_active_cycles_pc_s { 6118 u64 act_cyc : 64; 6119 } s; 6120 /* struct nixx_af_sqm_active_cycles_pc_s cn; */ 6121}; 6122 6123static inline u64 NIXX_AF_SQM_ACTIVE_CYCLES_PC(void) 6124 __attribute__ ((pure, always_inline)); 6125static inline u64 NIXX_AF_SQM_ACTIVE_CYCLES_PC(void) 6126{ 6127 return 0x770; 6128} 6129 6130/** 6131 * Register (RVU_PF_BAR0) nix#_af_sqm_bp_test# 6132 * 6133 * INTERNAL: NIX AF SQM Backpressure Test Register 6134 */ 6135union nixx_af_sqm_bp_testx { 6136 u64 u; 6137 struct nixx_af_sqm_bp_testx_s { 6138 u64 lfsr_freq : 12; 6139 u64 reserved_12_15 : 4; 6140 u64 bp_cfg : 8; 6141 u64 reserved_24_59 : 36; 6142 u64 enable : 4; 6143 } s; 6144 /* struct nixx_af_sqm_bp_testx_s cn; */ 6145}; 6146 6147static inline u64 NIXX_AF_SQM_BP_TESTX(u64 a) 6148 __attribute__ ((pure, always_inline)); 6149static inline u64 NIXX_AF_SQM_BP_TESTX(u64 a) 6150{ 6151 return 0x760 + 0x10000 * a; 6152} 6153 6154/** 6155 * Register (RVU_PF_BAR0) nix#_af_sqm_dbg_ctl_status 6156 * 6157 * NIX AF SQM Debug Register This register is for SQM diagnostic use 6158 * only. 6159 */ 6160union nixx_af_sqm_dbg_ctl_status { 6161 u64 u; 6162 struct nixx_af_sqm_dbg_ctl_status_s { 6163 u64 tm1 : 8; 6164 u64 tm2 : 1; 6165 u64 tm3 : 4; 6166 u64 tm4 : 1; 6167 u64 tm5 : 1; 6168 u64 tm6 : 1; 6169 u64 tm7 : 4; 6170 u64 tm8 : 1; 6171 u64 tm9 : 1; 6172 u64 tm10 : 1; 6173 u64 tm11 : 1; 6174 u64 tm12 : 1; 6175 u64 tm13 : 1; 6176 u64 reserved_26_63 : 38; 6177 } s; 6178 struct nixx_af_sqm_dbg_ctl_status_cn96xxp1 { 6179 u64 tm1 : 8; 6180 u64 tm2 : 1; 6181 u64 tm3 : 4; 6182 u64 tm4 : 1; 6183 u64 tm5 : 1; 6184 u64 tm6 : 1; 6185 u64 tm7 : 4; 6186 u64 tm8 : 1; 6187 u64 tm9 : 1; 6188 u64 reserved_22_63 : 42; 6189 } cn96xxp1; 6190 /* struct nixx_af_sqm_dbg_ctl_status_s cn96xxp3; */ 6191 /* struct nixx_af_sqm_dbg_ctl_status_cn96xxp1 cnf95xxp1; */ 6192 struct nixx_af_sqm_dbg_ctl_status_cnf95xxp2 { 6193 u64 tm1 : 8; 6194 u64 tm2 : 1; 6195 u64 tm3 : 4; 6196 u64 tm4 : 1; 6197 u64 tm5 : 1; 6198 u64 tm6 : 1; 6199 u64 tm7 : 4; 6200 u64 tm8 : 1; 6201 u64 tm9 : 1; 6202 u64 reserved_22 : 1; 6203 u64 reserved_23 : 1; 6204 u64 reserved_24 : 1; 6205 u64 reserved_25 : 1; 6206 u64 reserved_26_63 : 38; 6207 } cnf95xxp2; 6208}; 6209 6210static inline u64 NIXX_AF_SQM_DBG_CTL_STATUS(void) 6211 __attribute__ ((pure, always_inline)); 6212static inline u64 NIXX_AF_SQM_DBG_CTL_STATUS(void) 6213{ 6214 return 0x750; 6215} 6216 6217/** 6218 * Register (RVU_PF_BAR0) nix#_af_sqm_eco 6219 * 6220 * INTERNAL: AF SQM ECO Register 6221 */ 6222union nixx_af_sqm_eco { 6223 u64 u; 6224 struct nixx_af_sqm_eco_s { 6225 u64 eco_rw : 64; 6226 } s; 6227 /* struct nixx_af_sqm_eco_s cn; */ 6228}; 6229 6230static inline u64 NIXX_AF_SQM_ECO(void) 6231 __attribute__ ((pure, always_inline)); 6232static inline u64 NIXX_AF_SQM_ECO(void) 6233{ 6234 return 0x5b0; 6235} 6236 6237/** 6238 * Register (RVU_PF_BAR0) nix#_af_status 6239 * 6240 * NIX AF General Status Register 6241 */ 6242union nixx_af_status { 6243 u64 u; 6244 struct nixx_af_status_s { 6245 u64 blk_busy : 10; 6246 u64 calibrate_done : 1; 6247 u64 reserved_11_15 : 5; 6248 u64 calibrate_status : 15; 6249 u64 reserved_31_63 : 33; 6250 } s; 6251 /* struct nixx_af_status_s cn; */ 6252}; 6253 6254static inline u64 NIXX_AF_STATUS(void) 6255 __attribute__ ((pure, always_inline)); 6256static inline u64 NIXX_AF_STATUS(void) 6257{ 6258 return 0x10; 6259} 6260 6261/** 6262 * Register (RVU_PF_BAR0) nix#_af_tcp_timer 6263 * 6264 * NIX TCP Timer Register 6265 */ 6266union nixx_af_tcp_timer { 6267 u64 u; 6268 struct nixx_af_tcp_timer_s { 6269 u64 dur_counter : 16; 6270 u64 lf_counter : 8; 6271 u64 reserved_24_31 : 8; 6272 u64 duration : 16; 6273 u64 reserved_48_62 : 15; 6274 u64 ena : 1; 6275 } s; 6276 /* struct nixx_af_tcp_timer_s cn; */ 6277}; 6278 6279static inline u64 NIXX_AF_TCP_TIMER(void) 6280 __attribute__ ((pure, always_inline)); 6281static inline u64 NIXX_AF_TCP_TIMER(void) 6282{ 6283 return 0x1e0; 6284} 6285 6286/** 6287 * Register (RVU_PF_BAR0) nix#_af_tl1#_cir 6288 * 6289 * NIX AF Transmit Level 1 Committed Information Rate Register 6290 */ 6291union nixx_af_tl1x_cir { 6292 u64 u; 6293 struct nixx_af_tl1x_cir_s { 6294 u64 enable : 1; 6295 u64 rate_mantissa : 8; 6296 u64 rate_exponent : 4; 6297 u64 rate_divider_exponent : 4; 6298 u64 reserved_17_28 : 12; 6299 u64 burst_mantissa : 8; 6300 u64 burst_exponent : 4; 6301 u64 reserved_41_63 : 23; 6302 } s; 6303 /* struct nixx_af_tl1x_cir_s cn; */ 6304}; 6305 6306static inline u64 NIXX_AF_TL1X_CIR(u64 a) 6307 __attribute__ ((pure, always_inline)); 6308static inline u64 NIXX_AF_TL1X_CIR(u64 a) 6309{ 6310 return 0xc20 + 0x10000 * a; 6311} 6312 6313/** 6314 * Register (RVU_PF_BAR0) nix#_af_tl1#_dropped_bytes 6315 * 6316 * NIX AF Transmit Level 1 Dropped Bytes Registers This register has the 6317 * same bit fields as NIX_AF_TL1()_GREEN_BYTES. 6318 */ 6319union nixx_af_tl1x_dropped_bytes { 6320 u64 u; 6321 struct nixx_af_tl1x_dropped_bytes_s { 6322 u64 count : 48; 6323 u64 reserved_48_63 : 16; 6324 } s; 6325 /* struct nixx_af_tl1x_dropped_bytes_s cn; */ 6326}; 6327 6328static inline u64 NIXX_AF_TL1X_DROPPED_BYTES(u64 a) 6329 __attribute__ ((pure, always_inline)); 6330static inline u64 NIXX_AF_TL1X_DROPPED_BYTES(u64 a) 6331{ 6332 return 0xd30 + 0x10000 * a; 6333} 6334 6335/** 6336 * Register (RVU_PF_BAR0) nix#_af_tl1#_dropped_packets 6337 * 6338 * NIX AF Transmit Level 1 Dropped Packets Registers This register has 6339 * the same bit fields as NIX_AF_TL1()_GREEN_PACKETS. 6340 */ 6341union nixx_af_tl1x_dropped_packets { 6342 u64 u; 6343 struct nixx_af_tl1x_dropped_packets_s { 6344 u64 count : 40; 6345 u64 reserved_40_63 : 24; 6346 } s; 6347 /* struct nixx_af_tl1x_dropped_packets_s cn; */ 6348}; 6349 6350static inline u64 NIXX_AF_TL1X_DROPPED_PACKETS(u64 a) 6351 __attribute__ ((pure, always_inline)); 6352static inline u64 NIXX_AF_TL1X_DROPPED_PACKETS(u64 a) 6353{ 6354 return 0xd20 + 0x10000 * a; 6355} 6356 6357/** 6358 * Register (RVU_PF_BAR0) nix#_af_tl1#_green 6359 * 6360 * INTERNAL: NIX Transmit Level 1 Green State Debug Register 6361 */ 6362union nixx_af_tl1x_green { 6363 u64 u; 6364 struct nixx_af_tl1x_green_s { 6365 u64 tail : 8; 6366 u64 reserved_8_9 : 2; 6367 u64 head : 8; 6368 u64 reserved_18_19 : 2; 6369 u64 active_vec : 20; 6370 u64 rr_active : 1; 6371 u64 reserved_41_63 : 23; 6372 } s; 6373 /* struct nixx_af_tl1x_green_s cn; */ 6374}; 6375 6376static inline u64 NIXX_AF_TL1X_GREEN(u64 a) 6377 __attribute__ ((pure, always_inline)); 6378static inline u64 NIXX_AF_TL1X_GREEN(u64 a) 6379{ 6380 return 0xc90 + 0x10000 * a; 6381} 6382 6383/** 6384 * Register (RVU_PF_BAR0) nix#_af_tl1#_green_bytes 6385 * 6386 * NIX AF Transmit Level 1 Green Sent Bytes Registers 6387 */ 6388union nixx_af_tl1x_green_bytes { 6389 u64 u; 6390 struct nixx_af_tl1x_green_bytes_s { 6391 u64 count : 48; 6392 u64 reserved_48_63 : 16; 6393 } s; 6394 /* struct nixx_af_tl1x_green_bytes_s cn; */ 6395}; 6396 6397static inline u64 NIXX_AF_TL1X_GREEN_BYTES(u64 a) 6398 __attribute__ ((pure, always_inline)); 6399static inline u64 NIXX_AF_TL1X_GREEN_BYTES(u64 a) 6400{ 6401 return 0xd90 + 0x10000 * a; 6402} 6403 6404/** 6405 * Register (RVU_PF_BAR0) nix#_af_tl1#_green_packets 6406 * 6407 * NIX AF Transmit Level 1 Green Sent Packets Registers 6408 */ 6409union nixx_af_tl1x_green_packets { 6410 u64 u; 6411 struct nixx_af_tl1x_green_packets_s { 6412 u64 count : 40; 6413 u64 reserved_40_63 : 24; 6414 } s; 6415 /* struct nixx_af_tl1x_green_packets_s cn; */ 6416}; 6417 6418static inline u64 NIXX_AF_TL1X_GREEN_PACKETS(u64 a) 6419 __attribute__ ((pure, always_inline)); 6420static inline u64 NIXX_AF_TL1X_GREEN_PACKETS(u64 a) 6421{ 6422 return 0xd80 + 0x10000 * a; 6423} 6424 6425/** 6426 * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug0 6427 * 6428 * NIX AF Transmit Level 1 Meta Descriptor Debug 0 Registers 6429 * NIX_AF_TL1()_MD_DEBUG0, NIX_AF_TL1()_MD_DEBUG1, NIX_AF_TL1()_MD_DEBUG2 6430 * and NIX_AF_TL1()_MD_DEBUG3 provide access to the TLn queue meta 6431 * descriptor. A TLn queue can hold up to two packet meta descriptors 6432 * (PMD) and one flush meta descriptor (FMD): * PMD0 state is accessed 6433 * with [PMD0_VLD], [PMD0_LENGTH] and NIX_AF_TL1()_MD_DEBUG1. * PMD1 is 6434 * accessed with [PMD1_VLD], [PMD1_LENGTH] and NIX_AF_TL1()_MD_DEBUG2. * 6435 * FMD is accessed with NIX_AF_TL1()_MD_DEBUG3. 6436 */ 6437union nixx_af_tl1x_md_debug0 { 6438 u64 u; 6439 struct nixx_af_tl1x_md_debug0_s { 6440 u64 pmd0_length : 16; 6441 u64 pmd1_length : 16; 6442 u64 pmd0_vld : 1; 6443 u64 pmd1_vld : 1; 6444 u64 reserved_34_45 : 12; 6445 u64 drain_pri : 1; 6446 u64 drain : 1; 6447 u64 c_con : 1; 6448 u64 p_con : 1; 6449 u64 reserved_50_51 : 2; 6450 u64 child : 10; 6451 u64 reserved_62 : 1; 6452 u64 pmd_count : 1; 6453 } s; 6454 /* struct nixx_af_tl1x_md_debug0_s cn96xxp1; */ 6455 struct nixx_af_tl1x_md_debug0_cn96xxp3 { 6456 u64 pmd0_length : 16; 6457 u64 reserved_16_31 : 16; 6458 u64 pmd0_vld : 1; 6459 u64 reserved_33 : 1; 6460 u64 reserved_34_45 : 12; 6461 u64 reserved_46 : 1; 6462 u64 reserved_47 : 1; 6463 u64 c_con : 1; 6464 u64 p_con : 1; 6465 u64 reserved_50_51 : 2; 6466 u64 child : 10; 6467 u64 reserved_62 : 1; 6468 u64 reserved_63 : 1; 6469 } cn96xxp3; 6470 /* struct nixx_af_tl1x_md_debug0_s cnf95xx; */ 6471}; 6472 6473static inline u64 NIXX_AF_TL1X_MD_DEBUG0(u64 a) 6474 __attribute__ ((pure, always_inline)); 6475static inline u64 NIXX_AF_TL1X_MD_DEBUG0(u64 a) 6476{ 6477 return 0xcc0 + 0x10000 * a; 6478} 6479 6480/** 6481 * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug1 6482 * 6483 * NIX AF Transmit Level 1 Meta Descriptor Debug 1 Registers Packet meta 6484 * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0. 6485 */ 6486union nixx_af_tl1x_md_debug1 { 6487 u64 u; 6488 struct nixx_af_tl1x_md_debug1_s { 6489 u64 reserved_0_5 : 6; 6490 u64 red_algo_override : 2; 6491 u64 cir_dis : 1; 6492 u64 pir_dis : 1; 6493 u64 adjust : 9; 6494 u64 uid : 4; 6495 u64 reserved_23 : 1; 6496 u64 bubble : 1; 6497 u64 color : 2; 6498 u64 pse_pkt_id : 9; 6499 u64 reserved_36 : 1; 6500 u64 tx_pkt_p2x : 2; 6501 u64 sqm_pkt_id : 13; 6502 u64 mdq_idx : 10; 6503 u64 reserved_62 : 1; 6504 u64 vld : 1; 6505 } s; 6506 struct nixx_af_tl1x_md_debug1_cn96xxp1 { 6507 u64 reserved_0_5 : 6; 6508 u64 red_algo_override : 2; 6509 u64 cir_dis : 1; 6510 u64 pir_dis : 1; 6511 u64 adjust : 9; 6512 u64 uid : 4; 6513 u64 drain : 1; 6514 u64 bubble : 1; 6515 u64 color : 2; 6516 u64 pse_pkt_id : 9; 6517 u64 reserved_36 : 1; 6518 u64 tx_pkt_p2x : 2; 6519 u64 sqm_pkt_id : 13; 6520 u64 mdq_idx : 10; 6521 u64 reserved_62 : 1; 6522 u64 vld : 1; 6523 } cn96xxp1; 6524 struct nixx_af_tl1x_md_debug1_cn96xxp3 { 6525 u64 reserved_0_5 : 6; 6526 u64 red_algo_override : 2; 6527 u64 cir_dis : 1; 6528 u64 pir_dis : 1; 6529 u64 adjust : 9; 6530 u64 reserved_19_22 : 4; 6531 u64 flush : 1; 6532 u64 bubble : 1; 6533 u64 color : 2; 6534 u64 pse_pkt_id : 9; 6535 u64 reserved_36 : 1; 6536 u64 tx_pkt_p2x : 2; 6537 u64 sqm_pkt_id : 13; 6538 u64 mdq_idx : 10; 6539 u64 reserved_62 : 1; 6540 u64 vld : 1; 6541 } cn96xxp3; 6542 /* struct nixx_af_tl1x_md_debug1_cn96xxp1 cnf95xx; */ 6543}; 6544 6545static inline u64 NIXX_AF_TL1X_MD_DEBUG1(u64 a) 6546 __attribute__ ((pure, always_inline)); 6547static inline u64 NIXX_AF_TL1X_MD_DEBUG1(u64 a) 6548{ 6549 return 0xcc8 + 0x10000 * a; 6550} 6551 6552/** 6553 * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug2 6554 * 6555 * NIX AF Transmit Level 1 Meta Descriptor Debug 2 Registers Packet meta 6556 * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0. 6557 */ 6558union nixx_af_tl1x_md_debug2 { 6559 u64 u; 6560 struct nixx_af_tl1x_md_debug2_s { 6561 u64 reserved_0_5 : 6; 6562 u64 red_algo_override : 2; 6563 u64 cir_dis : 1; 6564 u64 pir_dis : 1; 6565 u64 adjust : 9; 6566 u64 uid : 4; 6567 u64 reserved_23 : 1; 6568 u64 bubble : 1; 6569 u64 color : 2; 6570 u64 pse_pkt_id : 9; 6571 u64 reserved_36 : 1; 6572 u64 tx_pkt_p2x : 2; 6573 u64 sqm_pkt_id : 13; 6574 u64 mdq_idx : 10; 6575 u64 reserved_62 : 1; 6576 u64 vld : 1; 6577 } s; 6578 struct nixx_af_tl1x_md_debug2_cn96xxp1 { 6579 u64 reserved_0_5 : 6; 6580 u64 red_algo_override : 2; 6581 u64 cir_dis : 1; 6582 u64 pir_dis : 1; 6583 u64 adjust : 9; 6584 u64 uid : 4; 6585 u64 drain : 1; 6586 u64 bubble : 1; 6587 u64 color : 2; 6588 u64 pse_pkt_id : 9; 6589 u64 reserved_36 : 1; 6590 u64 tx_pkt_p2x : 2; 6591 u64 sqm_pkt_id : 13; 6592 u64 mdq_idx : 10; 6593 u64 reserved_62 : 1; 6594 u64 vld : 1; 6595 } cn96xxp1; 6596 struct nixx_af_tl1x_md_debug2_cn96xxp3 { 6597 u64 reserved_0_5 : 6; 6598 u64 red_algo_override : 2; 6599 u64 cir_dis : 1; 6600 u64 pir_dis : 1; 6601 u64 adjust : 9; 6602 u64 reserved_19_22 : 4; 6603 u64 flush : 1; 6604 u64 bubble : 1; 6605 u64 color : 2; 6606 u64 pse_pkt_id : 9; 6607 u64 reserved_36 : 1; 6608 u64 tx_pkt_p2x : 2; 6609 u64 sqm_pkt_id : 13; 6610 u64 mdq_idx : 10; 6611 u64 reserved_62 : 1; 6612 u64 vld : 1; 6613 } cn96xxp3; 6614 /* struct nixx_af_tl1x_md_debug2_cn96xxp1 cnf95xx; */ 6615}; 6616 6617static inline u64 NIXX_AF_TL1X_MD_DEBUG2(u64 a) 6618 __attribute__ ((pure, always_inline)); 6619static inline u64 NIXX_AF_TL1X_MD_DEBUG2(u64 a) 6620{ 6621 return 0xcd0 + 0x10000 * a; 6622} 6623 6624/** 6625 * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug3 6626 * 6627 * NIX AF Transmit Level 1 Meta Descriptor Debug 3 Registers Flush meta 6628 * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0. 6629 */ 6630union nixx_af_tl1x_md_debug3 { 6631 u64 u; 6632 struct nixx_af_tl1x_md_debug3_s { 6633 u64 reserved_0_36 : 37; 6634 u64 tx_pkt_p2x : 2; 6635 u64 sqm_pkt_id : 13; 6636 u64 mdq_idx : 10; 6637 u64 reserved_62 : 1; 6638 u64 vld : 1; 6639 } s; 6640 /* struct nixx_af_tl1x_md_debug3_s cn96xxp1; */ 6641 struct nixx_af_tl1x_md_debug3_cn96xxp3 { 6642 u64 reserved_0_36 : 37; 6643 u64 reserved_37_38 : 2; 6644 u64 reserved_39_51 : 13; 6645 u64 reserved_52_61 : 10; 6646 u64 reserved_62 : 1; 6647 u64 reserved_63 : 1; 6648 } cn96xxp3; 6649 /* struct nixx_af_tl1x_md_debug3_s cnf95xx; */ 6650}; 6651 6652static inline u64 NIXX_AF_TL1X_MD_DEBUG3(u64 a) 6653 __attribute__ ((pure, always_inline)); 6654static inline u64 NIXX_AF_TL1X_MD_DEBUG3(u64 a) 6655{ 6656 return 0xcd8 + 0x10000 * a; 6657} 6658 6659/** 6660 * Register (RVU_PF_BAR0) nix#_af_tl1#_red 6661 * 6662 * INTERNAL: NIX Transmit Level 1 Red State Debug Register This register 6663 * has the same bit fields as NIX_AF_TL1()_YELLOW. 6664 */ 6665union nixx_af_tl1x_red { 6666 u64 u; 6667 struct nixx_af_tl1x_red_s { 6668 u64 tail : 8; 6669 u64 reserved_8_9 : 2; 6670 u64 head : 8; 6671 u64 reserved_18_63 : 46; 6672 } s; 6673 /* struct nixx_af_tl1x_red_s cn; */ 6674}; 6675 6676static inline u64 NIXX_AF_TL1X_RED(u64 a) 6677 __attribute__ ((pure, always_inline)); 6678static inline u64 NIXX_AF_TL1X_RED(u64 a) 6679{ 6680 return 0xcb0 + 0x10000 * a; 6681} 6682 6683/** 6684 * Register (RVU_PF_BAR0) nix#_af_tl1#_red_bytes 6685 * 6686 * NIX AF Transmit Level 1 Red Sent Bytes Registers This register has the 6687 * same bit fields as NIX_AF_TL1()_GREEN_BYTES. 6688 */ 6689union nixx_af_tl1x_red_bytes { 6690 u64 u; 6691 struct nixx_af_tl1x_red_bytes_s { 6692 u64 count : 48; 6693 u64 reserved_48_63 : 16; 6694 } s; 6695 /* struct nixx_af_tl1x_red_bytes_s cn; */ 6696}; 6697 6698static inline u64 NIXX_AF_TL1X_RED_BYTES(u64 a) 6699 __attribute__ ((pure, always_inline)); 6700static inline u64 NIXX_AF_TL1X_RED_BYTES(u64 a) 6701{ 6702 return 0xd50 + 0x10000 * a; 6703} 6704 6705/** 6706 * Register (RVU_PF_BAR0) nix#_af_tl1#_red_packets 6707 * 6708 * NIX AF Transmit Level 1 Red Sent Packets Registers This register has 6709 * the same bit fields as NIX_AF_TL1()_GREEN_PACKETS. 6710 */ 6711union nixx_af_tl1x_red_packets { 6712 u64 u; 6713 struct nixx_af_tl1x_red_packets_s { 6714 u64 count : 40; 6715 u64 reserved_40_63 : 24; 6716 } s; 6717 /* struct nixx_af_tl1x_red_packets_s cn; */ 6718}; 6719 6720static inline u64 NIXX_AF_TL1X_RED_PACKETS(u64 a) 6721 __attribute__ ((pure, always_inline)); 6722static inline u64 NIXX_AF_TL1X_RED_PACKETS(u64 a) 6723{ 6724 return 0xd40 + 0x10000 * a; 6725} 6726 6727/** 6728 * Register (RVU_PF_BAR0) nix#_af_tl1#_schedule 6729 * 6730 * NIX AF Transmit Level 1 Scheduling Control Register 6731 */ 6732union nixx_af_tl1x_schedule { 6733 u64 u; 6734 struct nixx_af_tl1x_schedule_s { 6735 u64 rr_quantum : 24; 6736 u64 reserved_24_63 : 40; 6737 } s; 6738 /* struct nixx_af_tl1x_schedule_s cn; */ 6739}; 6740 6741static inline u64 NIXX_AF_TL1X_SCHEDULE(u64 a) 6742 __attribute__ ((pure, always_inline)); 6743static inline u64 NIXX_AF_TL1X_SCHEDULE(u64 a) 6744{ 6745 return 0xc00 + 0x10000 * a; 6746} 6747 6748/** 6749 * Register (RVU_PF_BAR0) nix#_af_tl1#_shape 6750 * 6751 * NIX AF Transmit Level 1 Shaping Control Register 6752 */ 6753union nixx_af_tl1x_shape { 6754 u64 u; 6755 struct nixx_af_tl1x_shape_s { 6756 u64 adjust : 9; 6757 u64 reserved_9_23 : 15; 6758 u64 length_disable : 1; 6759 u64 reserved_25_63 : 39; 6760 } s; 6761 struct nixx_af_tl1x_shape_cn { 6762 u64 adjust : 9; 6763 u64 reserved_9_17 : 9; 6764 u64 reserved_18_23 : 6; 6765 u64 length_disable : 1; 6766 u64 reserved_25_63 : 39; 6767 } cn; 6768}; 6769 6770static inline u64 NIXX_AF_TL1X_SHAPE(u64 a) 6771 __attribute__ ((pure, always_inline)); 6772static inline u64 NIXX_AF_TL1X_SHAPE(u64 a) 6773{ 6774 return 0xc10 + 0x10000 * a; 6775} 6776 6777/** 6778 * Register (RVU_PF_BAR0) nix#_af_tl1#_shape_state 6779 * 6780 * NIX AF Transmit Level 1 Shape State Register This register must not be 6781 * written during normal operation. 6782 */ 6783union nixx_af_tl1x_shape_state { 6784 u64 u; 6785 struct nixx_af_tl1x_shape_state_s { 6786 u64 cir_accum : 26; 6787 u64 reserved_26_51 : 26; 6788 u64 color : 1; 6789 u64 reserved_53_63 : 11; 6790 } s; 6791 /* struct nixx_af_tl1x_shape_state_s cn; */ 6792}; 6793 6794static inline u64 NIXX_AF_TL1X_SHAPE_STATE(u64 a) 6795 __attribute__ ((pure, always_inline)); 6796static inline u64 NIXX_AF_TL1X_SHAPE_STATE(u64 a) 6797{ 6798 return 0xc50 + 0x10000 * a; 6799} 6800 6801/** 6802 * Register (RVU_PF_BAR0) nix#_af_tl1#_sw_xoff 6803 * 6804 * NIX AF Transmit Level 1 Software Controlled XOFF Registers 6805 */ 6806union nixx_af_tl1x_sw_xoff { 6807 u64 u; 6808 struct nixx_af_tl1x_sw_xoff_s { 6809 u64 xoff : 1; 6810 u64 drain : 1; 6811 u64 reserved_2 : 1; 6812 u64 drain_irq : 1; 6813 u64 reserved_4_63 : 60; 6814 } s; 6815 /* struct nixx_af_tl1x_sw_xoff_s cn; */ 6816}; 6817 6818static inline u64 NIXX_AF_TL1X_SW_XOFF(u64 a) 6819 __attribute__ ((pure, always_inline)); 6820static inline u64 NIXX_AF_TL1X_SW_XOFF(u64 a) 6821{ 6822 return 0xc70 + 0x10000 * a; 6823} 6824 6825/** 6826 * Register (RVU_PF_BAR0) nix#_af_tl1#_topology 6827 * 6828 * NIX AF Transmit Level 1 Topology Registers 6829 */ 6830union nixx_af_tl1x_topology { 6831 u64 u; 6832 struct nixx_af_tl1x_topology_s { 6833 u64 reserved_0 : 1; 6834 u64 rr_prio : 4; 6835 u64 reserved_5_31 : 27; 6836 u64 prio_anchor : 8; 6837 u64 reserved_40_63 : 24; 6838 } s; 6839 /* struct nixx_af_tl1x_topology_s cn; */ 6840}; 6841 6842static inline u64 NIXX_AF_TL1X_TOPOLOGY(u64 a) 6843 __attribute__ ((pure, always_inline)); 6844static inline u64 NIXX_AF_TL1X_TOPOLOGY(u64 a) 6845{ 6846 return 0xc80 + 0x10000 * a; 6847} 6848 6849/** 6850 * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow 6851 * 6852 * INTERNAL: NIX Transmit Level 1 Yellow State Debug Register 6853 */ 6854union nixx_af_tl1x_yellow { 6855 u64 u; 6856 struct nixx_af_tl1x_yellow_s { 6857 u64 tail : 8; 6858 u64 reserved_8_9 : 2; 6859 u64 head : 8; 6860 u64 reserved_18_63 : 46; 6861 } s; 6862 /* struct nixx_af_tl1x_yellow_s cn; */ 6863}; 6864 6865static inline u64 NIXX_AF_TL1X_YELLOW(u64 a) 6866 __attribute__ ((pure, always_inline)); 6867static inline u64 NIXX_AF_TL1X_YELLOW(u64 a) 6868{ 6869 return 0xca0 + 0x10000 * a; 6870} 6871 6872/** 6873 * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow_bytes 6874 * 6875 * NIX AF Transmit Level 1 Yellow Sent Bytes Registers This register has 6876 * the same bit fields as NIX_AF_TL1()_GREEN_BYTES. 6877 */ 6878union nixx_af_tl1x_yellow_bytes { 6879 u64 u; 6880 struct nixx_af_tl1x_yellow_bytes_s { 6881 u64 count : 48; 6882 u64 reserved_48_63 : 16; 6883 } s; 6884 /* struct nixx_af_tl1x_yellow_bytes_s cn; */ 6885}; 6886 6887static inline u64 NIXX_AF_TL1X_YELLOW_BYTES(u64 a) 6888 __attribute__ ((pure, always_inline)); 6889static inline u64 NIXX_AF_TL1X_YELLOW_BYTES(u64 a) 6890{ 6891 return 0xd70 + 0x10000 * a; 6892} 6893 6894/** 6895 * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow_packets 6896 * 6897 * NIX AF Transmit Level 1 Yellow Sent Packets Registers This register 6898 * has the same bit fields as NIX_AF_TL1()_GREEN_PACKETS. 6899 */ 6900union nixx_af_tl1x_yellow_packets { 6901 u64 u; 6902 struct nixx_af_tl1x_yellow_packets_s { 6903 u64 count : 40; 6904 u64 reserved_40_63 : 24; 6905 } s; 6906 /* struct nixx_af_tl1x_yellow_packets_s cn; */ 6907}; 6908 6909static inline u64 NIXX_AF_TL1X_YELLOW_PACKETS(u64 a) 6910 __attribute__ ((pure, always_inline)); 6911static inline u64 NIXX_AF_TL1X_YELLOW_PACKETS(u64 a) 6912{ 6913 return 0xd60 + 0x10000 * a; 6914} 6915 6916/** 6917 * Register (RVU_PF_BAR0) nix#_af_tl1_const 6918 * 6919 * NIX AF Transmit Level 1 Constants Register This register contains 6920 * constants for software discovery. 6921 */ 6922union nixx_af_tl1_const { 6923 u64 u; 6924 struct nixx_af_tl1_const_s { 6925 u64 count : 16; 6926 u64 reserved_16_63 : 48; 6927 } s; 6928 /* struct nixx_af_tl1_const_s cn; */ 6929}; 6930 6931static inline u64 NIXX_AF_TL1_CONST(void) 6932 __attribute__ ((pure, always_inline)); 6933static inline u64 NIXX_AF_TL1_CONST(void) 6934{ 6935 return 0x70; 6936} 6937 6938/** 6939 * Register (RVU_PF_BAR0) nix#_af_tl2#_cir 6940 * 6941 * NIX AF Transmit Level 2 Committed Information Rate Registers This 6942 * register has the same bit fields as NIX_AF_TL1()_CIR. 6943 */ 6944union nixx_af_tl2x_cir { 6945 u64 u; 6946 struct nixx_af_tl2x_cir_s { 6947 u64 enable : 1; 6948 u64 rate_mantissa : 8; 6949 u64 rate_exponent : 4; 6950 u64 rate_divider_exponent : 4; 6951 u64 reserved_17_28 : 12; 6952 u64 burst_mantissa : 8; 6953 u64 burst_exponent : 4; 6954 u64 reserved_41_63 : 23; 6955 } s; 6956 /* struct nixx_af_tl2x_cir_s cn; */ 6957}; 6958 6959static inline u64 NIXX_AF_TL2X_CIR(u64 a) 6960 __attribute__ ((pure, always_inline)); 6961static inline u64 NIXX_AF_TL2X_CIR(u64 a) 6962{ 6963 return 0xe20 + 0x10000 * a; 6964} 6965 6966/** 6967 * Register (RVU_PF_BAR0) nix#_af_tl2#_green 6968 * 6969 * INTERNAL: NIX Transmit Level 2 Green State Debug Register This 6970 * register has the same bit fields as NIX_AF_TL1()_GREEN. 6971 */ 6972union nixx_af_tl2x_green { 6973 u64 u; 6974 struct nixx_af_tl2x_green_s { 6975 u64 tail : 8; 6976 u64 reserved_8_9 : 2; 6977 u64 head : 8; 6978 u64 reserved_18_19 : 2; 6979 u64 active_vec : 20; 6980 u64 rr_active : 1; 6981 u64 reserved_41_63 : 23; 6982 } s; 6983 /* struct nixx_af_tl2x_green_s cn; */ 6984}; 6985 6986static inline u64 NIXX_AF_TL2X_GREEN(u64 a) 6987 __attribute__ ((pure, always_inline)); 6988static inline u64 NIXX_AF_TL2X_GREEN(u64 a) 6989{ 6990 return 0xe90 + 0x10000 * a; 6991} 6992 6993/** 6994 * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug0 6995 * 6996 * NIX AF Transmit Level 2 Meta Descriptor Debug 0 Registers See 6997 * NIX_AF_TL1()_MD_DEBUG0 6998 */ 6999union nixx_af_tl2x_md_debug0 { 7000 u64 u; 7001 struct nixx_af_tl2x_md_debug0_s { 7002 u64 pmd0_length : 16; 7003 u64 pmd1_length : 16; 7004 u64 pmd0_vld : 1; 7005 u64 pmd1_vld : 1; 7006 u64 reserved_34_45 : 12; 7007 u64 drain_pri : 1; 7008 u64 drain : 1; 7009 u64 c_con : 1; 7010 u64 p_con : 1; 7011 u64 reserved_50_51 : 2; 7012 u64 child : 10; 7013 u64 reserved_62 : 1; 7014 u64 pmd_count : 1; 7015 } s; 7016 /* struct nixx_af_tl2x_md_debug0_s cn96xxp1; */ 7017 struct nixx_af_tl2x_md_debug0_cn96xxp3 { 7018 u64 pmd0_length : 16; 7019 u64 reserved_16_31 : 16; 7020 u64 pmd0_vld : 1; 7021 u64 reserved_33 : 1; 7022 u64 reserved_34_45 : 12; 7023 u64 reserved_46 : 1; 7024 u64 reserved_47 : 1; 7025 u64 c_con : 1; 7026 u64 p_con : 1; 7027 u64 reserved_50_51 : 2; 7028 u64 child : 10; 7029 u64 reserved_62 : 1; 7030 u64 reserved_63 : 1; 7031 } cn96xxp3; 7032 /* struct nixx_af_tl2x_md_debug0_s cnf95xx; */ 7033}; 7034 7035static inline u64 NIXX_AF_TL2X_MD_DEBUG0(u64 a) 7036 __attribute__ ((pure, always_inline)); 7037static inline u64 NIXX_AF_TL2X_MD_DEBUG0(u64 a) 7038{ 7039 return 0xec0 + 0x10000 * a; 7040} 7041 7042/** 7043 * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug1 7044 * 7045 * NIX AF Transmit Level 2 Meta Descriptor Debug 1 Registers Packet meta 7046 * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0. 7047 */ 7048union nixx_af_tl2x_md_debug1 { 7049 u64 u; 7050 struct nixx_af_tl2x_md_debug1_s { 7051 u64 reserved_0_5 : 6; 7052 u64 red_algo_override : 2; 7053 u64 cir_dis : 1; 7054 u64 pir_dis : 1; 7055 u64 adjust : 9; 7056 u64 uid : 4; 7057 u64 reserved_23 : 1; 7058 u64 bubble : 1; 7059 u64 color : 2; 7060 u64 pse_pkt_id : 9; 7061 u64 reserved_36 : 1; 7062 u64 tx_pkt_p2x : 2; 7063 u64 sqm_pkt_id : 13; 7064 u64 mdq_idx : 10; 7065 u64 reserved_62 : 1; 7066 u64 vld : 1; 7067 } s; 7068 struct nixx_af_tl2x_md_debug1_cn96xxp1 { 7069 u64 reserved_0_5 : 6; 7070 u64 red_algo_override : 2; 7071 u64 cir_dis : 1; 7072 u64 pir_dis : 1; 7073 u64 adjust : 9; 7074 u64 uid : 4; 7075 u64 drain : 1; 7076 u64 bubble : 1; 7077 u64 color : 2; 7078 u64 pse_pkt_id : 9; 7079 u64 reserved_36 : 1; 7080 u64 tx_pkt_p2x : 2; 7081 u64 sqm_pkt_id : 13; 7082 u64 mdq_idx : 10; 7083 u64 reserved_62 : 1; 7084 u64 vld : 1; 7085 } cn96xxp1; 7086 struct nixx_af_tl2x_md_debug1_cn96xxp3 { 7087 u64 reserved_0_5 : 6; 7088 u64 red_algo_override : 2; 7089 u64 cir_dis : 1; 7090 u64 pir_dis : 1; 7091 u64 adjust : 9; 7092 u64 reserved_19_22 : 4; 7093 u64 flush : 1; 7094 u64 bubble : 1; 7095 u64 color : 2; 7096 u64 pse_pkt_id : 9; 7097 u64 reserved_36 : 1; 7098 u64 tx_pkt_p2x : 2; 7099 u64 sqm_pkt_id : 13; 7100 u64 mdq_idx : 10; 7101 u64 reserved_62 : 1; 7102 u64 vld : 1; 7103 } cn96xxp3; 7104 /* struct nixx_af_tl2x_md_debug1_cn96xxp1 cnf95xx; */ 7105}; 7106 7107static inline u64 NIXX_AF_TL2X_MD_DEBUG1(u64 a) 7108 __attribute__ ((pure, always_inline)); 7109static inline u64 NIXX_AF_TL2X_MD_DEBUG1(u64 a) 7110{ 7111 return 0xec8 + 0x10000 * a; 7112} 7113 7114/** 7115 * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug2 7116 * 7117 * NIX AF Transmit Level 2 Meta Descriptor Debug 2 Registers Packet meta 7118 * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0. 7119 */ 7120union nixx_af_tl2x_md_debug2 { 7121 u64 u; 7122 struct nixx_af_tl2x_md_debug2_s { 7123 u64 reserved_0_5 : 6; 7124 u64 red_algo_override : 2; 7125 u64 cir_dis : 1; 7126 u64 pir_dis : 1; 7127 u64 adjust : 9; 7128 u64 uid : 4; 7129 u64 reserved_23 : 1; 7130 u64 bubble : 1; 7131 u64 color : 2; 7132 u64 pse_pkt_id : 9; 7133 u64 reserved_36 : 1; 7134 u64 tx_pkt_p2x : 2; 7135 u64 sqm_pkt_id : 13; 7136 u64 mdq_idx : 10; 7137 u64 reserved_62 : 1; 7138 u64 vld : 1; 7139 } s; 7140 struct nixx_af_tl2x_md_debug2_cn96xxp1 { 7141 u64 reserved_0_5 : 6; 7142 u64 red_algo_override : 2; 7143 u64 cir_dis : 1; 7144 u64 pir_dis : 1; 7145 u64 adjust : 9; 7146 u64 uid : 4; 7147 u64 drain : 1; 7148 u64 bubble : 1; 7149 u64 color : 2; 7150 u64 pse_pkt_id : 9; 7151 u64 reserved_36 : 1; 7152 u64 tx_pkt_p2x : 2; 7153 u64 sqm_pkt_id : 13; 7154 u64 mdq_idx : 10; 7155 u64 reserved_62 : 1; 7156 u64 vld : 1; 7157 } cn96xxp1; 7158 struct nixx_af_tl2x_md_debug2_cn96xxp3 { 7159 u64 reserved_0_5 : 6; 7160 u64 red_algo_override : 2; 7161 u64 cir_dis : 1; 7162 u64 pir_dis : 1; 7163 u64 adjust : 9; 7164 u64 reserved_19_22 : 4; 7165 u64 flush : 1; 7166 u64 bubble : 1; 7167 u64 color : 2; 7168 u64 pse_pkt_id : 9; 7169 u64 reserved_36 : 1; 7170 u64 tx_pkt_p2x : 2; 7171 u64 sqm_pkt_id : 13; 7172 u64 mdq_idx : 10; 7173 u64 reserved_62 : 1; 7174 u64 vld : 1; 7175 } cn96xxp3; 7176 /* struct nixx_af_tl2x_md_debug2_cn96xxp1 cnf95xx; */ 7177}; 7178 7179static inline u64 NIXX_AF_TL2X_MD_DEBUG2(u64 a) 7180 __attribute__ ((pure, always_inline)); 7181static inline u64 NIXX_AF_TL2X_MD_DEBUG2(u64 a) 7182{ 7183 return 0xed0 + 0x10000 * a; 7184} 7185 7186/** 7187 * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug3 7188 * 7189 * NIX AF Transmit Level 2 Meta Descriptor Debug 3 Registers Flush meta 7190 * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0. 7191 */ 7192union nixx_af_tl2x_md_debug3 { 7193 u64 u; 7194 struct nixx_af_tl2x_md_debug3_s { 7195 u64 reserved_0_36 : 37; 7196 u64 tx_pkt_p2x : 2; 7197 u64 sqm_pkt_id : 13; 7198 u64 mdq_idx : 10; 7199 u64 reserved_62 : 1; 7200 u64 vld : 1; 7201 } s; 7202 /* struct nixx_af_tl2x_md_debug3_s cn96xxp1; */ 7203 struct nixx_af_tl2x_md_debug3_cn96xxp3 { 7204 u64 reserved_0_36 : 37; 7205 u64 reserved_37_38 : 2; 7206 u64 reserved_39_51 : 13; 7207 u64 reserved_52_61 : 10; 7208 u64 reserved_62 : 1; 7209 u64 reserved_63 : 1; 7210 } cn96xxp3; 7211 /* struct nixx_af_tl2x_md_debug3_s cnf95xx; */ 7212}; 7213 7214static inline u64 NIXX_AF_TL2X_MD_DEBUG3(u64 a) 7215 __attribute__ ((pure, always_inline)); 7216static inline u64 NIXX_AF_TL2X_MD_DEBUG3(u64 a) 7217{ 7218 return 0xed8 + 0x10000 * a; 7219} 7220 7221/** 7222 * Register (RVU_PF_BAR0) nix#_af_tl2#_parent 7223 * 7224 * NIX AF Transmit Level 2 Parent Registers 7225 */ 7226union nixx_af_tl2x_parent { 7227 u64 u; 7228 struct nixx_af_tl2x_parent_s { 7229 u64 reserved_0_15 : 16; 7230 u64 parent : 5; 7231 u64 reserved_21_63 : 43; 7232 } s; 7233 /* struct nixx_af_tl2x_parent_s cn; */ 7234}; 7235 7236static inline u64 NIXX_AF_TL2X_PARENT(u64 a) 7237 __attribute__ ((pure, always_inline)); 7238static inline u64 NIXX_AF_TL2X_PARENT(u64 a) 7239{ 7240 return 0xe88 + 0x10000 * a; 7241} 7242 7243/** 7244 * Register (RVU_PF_BAR0) nix#_af_tl2#_pir 7245 * 7246 * NIX AF Transmit Level 2 Peak Information Rate Registers This register 7247 * has the same bit fields as NIX_AF_TL1()_CIR. 7248 */ 7249union nixx_af_tl2x_pir { 7250 u64 u; 7251 struct nixx_af_tl2x_pir_s { 7252 u64 enable : 1; 7253 u64 rate_mantissa : 8; 7254 u64 rate_exponent : 4; 7255 u64 rate_divider_exponent : 4; 7256 u64 reserved_17_28 : 12; 7257 u64 burst_mantissa : 8; 7258 u64 burst_exponent : 4; 7259 u64 reserved_41_63 : 23; 7260 } s; 7261 /* struct nixx_af_tl2x_pir_s cn; */ 7262}; 7263 7264static inline u64 NIXX_AF_TL2X_PIR(u64 a) 7265 __attribute__ ((pure, always_inline)); 7266static inline u64 NIXX_AF_TL2X_PIR(u64 a) 7267{ 7268 return 0xe30 + 0x10000 * a; 7269} 7270 7271/** 7272 * Register (RVU_PF_BAR0) nix#_af_tl2#_pointers 7273 * 7274 * INTERNAL: NIX Transmit Level 2 Linked List Pointers Debug Register 7275 */ 7276union nixx_af_tl2x_pointers { 7277 u64 u; 7278 struct nixx_af_tl2x_pointers_s { 7279 u64 next : 8; 7280 u64 reserved_8_15 : 8; 7281 u64 prev : 8; 7282 u64 reserved_24_63 : 40; 7283 } s; 7284 /* struct nixx_af_tl2x_pointers_s cn; */ 7285}; 7286 7287static inline u64 NIXX_AF_TL2X_POINTERS(u64 a) 7288 __attribute__ ((pure, always_inline)); 7289static inline u64 NIXX_AF_TL2X_POINTERS(u64 a) 7290{ 7291 return 0xe60 + 0x10000 * a; 7292} 7293 7294/** 7295 * Register (RVU_PF_BAR0) nix#_af_tl2#_red 7296 * 7297 * INTERNAL: NIX Transmit Level 2 Red State Debug Register This register 7298 * has the same bit fields as NIX_AF_TL1()_RED. 7299 */ 7300union nixx_af_tl2x_red { 7301 u64 u; 7302 struct nixx_af_tl2x_red_s { 7303 u64 tail : 8; 7304 u64 reserved_8_9 : 2; 7305 u64 head : 8; 7306 u64 reserved_18_63 : 46; 7307 } s; 7308 /* struct nixx_af_tl2x_red_s cn; */ 7309}; 7310 7311static inline u64 NIXX_AF_TL2X_RED(u64 a) 7312 __attribute__ ((pure, always_inline)); 7313static inline u64 NIXX_AF_TL2X_RED(u64 a) 7314{ 7315 return 0xeb0 + 0x10000 * a; 7316} 7317 7318/** 7319 * Register (RVU_PF_BAR0) nix#_af_tl2#_sched_state 7320 * 7321 * NIX AF Transmit Level 2 Scheduling Control State Registers 7322 */ 7323union nixx_af_tl2x_sched_state { 7324 u64 u; 7325 struct nixx_af_tl2x_sched_state_s { 7326 u64 rr_count : 25; 7327 u64 reserved_25_63 : 39; 7328 } s; 7329 /* struct nixx_af_tl2x_sched_state_s cn; */ 7330}; 7331 7332static inline u64 NIXX_AF_TL2X_SCHED_STATE(u64 a) 7333 __attribute__ ((pure, always_inline)); 7334static inline u64 NIXX_AF_TL2X_SCHED_STATE(u64 a) 7335{ 7336 return 0xe40 + 0x10000 * a; 7337} 7338 7339/** 7340 * Register (RVU_PF_BAR0) nix#_af_tl2#_schedule 7341 * 7342 * NIX AF Transmit Level 2 Scheduling Control Registers 7343 */ 7344union nixx_af_tl2x_schedule { 7345 u64 u; 7346 struct nixx_af_tl2x_schedule_s { 7347 u64 rr_quantum : 24; 7348 u64 prio : 4; 7349 u64 reserved_28_63 : 36; 7350 } s; 7351 /* struct nixx_af_tl2x_schedule_s cn; */ 7352}; 7353 7354static inline u64 NIXX_AF_TL2X_SCHEDULE(u64 a) 7355 __attribute__ ((pure, always_inline)); 7356static inline u64 NIXX_AF_TL2X_SCHEDULE(u64 a) 7357{ 7358 return 0xe00 + 0x10000 * a; 7359} 7360 7361/** 7362 * Register (RVU_PF_BAR0) nix#_af_tl2#_shape 7363 * 7364 * NIX AF Transmit Level 2 Shaping Control Registers 7365 */ 7366union nixx_af_tl2x_shape { 7367 u64 u; 7368 struct nixx_af_tl2x_shape_s { 7369 u64 adjust : 9; 7370 u64 red_algo : 2; 7371 u64 red_disable : 1; 7372 u64 yellow_disable : 1; 7373 u64 reserved_13_23 : 11; 7374 u64 length_disable : 1; 7375 u64 schedule_list : 2; 7376 u64 reserved_27_63 : 37; 7377 } s; 7378 /* struct nixx_af_tl2x_shape_s cn; */ 7379}; 7380 7381static inline u64 NIXX_AF_TL2X_SHAPE(u64 a) 7382 __attribute__ ((pure, always_inline)); 7383static inline u64 NIXX_AF_TL2X_SHAPE(u64 a) 7384{ 7385 return 0xe10 + 0x10000 * a; 7386} 7387 7388/** 7389 * Register (RVU_PF_BAR0) nix#_af_tl2#_shape_state 7390 * 7391 * NIX AF Transmit Level 2 Shape State Registers This register must not 7392 * be written during normal operation. 7393 */ 7394union nixx_af_tl2x_shape_state { 7395 u64 u; 7396 struct nixx_af_tl2x_shape_state_s { 7397 u64 cir_accum : 26; 7398 u64 pir_accum : 26; 7399 u64 color : 2; 7400 u64 reserved_54_63 : 10; 7401 } s; 7402 /* struct nixx_af_tl2x_shape_state_s cn; */ 7403}; 7404 7405static inline u64 NIXX_AF_TL2X_SHAPE_STATE(u64 a) 7406 __attribute__ ((pure, always_inline)); 7407static inline u64 NIXX_AF_TL2X_SHAPE_STATE(u64 a) 7408{ 7409 return 0xe50 + 0x10000 * a; 7410} 7411 7412/** 7413 * Register (RVU_PF_BAR0) nix#_af_tl2#_sw_xoff 7414 * 7415 * NIX AF Transmit Level 2 Software Controlled XOFF Registers This 7416 * register has the same bit fields as NIX_AF_TL1()_SW_XOFF. 7417 */ 7418union nixx_af_tl2x_sw_xoff { 7419 u64 u; 7420 struct nixx_af_tl2x_sw_xoff_s { 7421 u64 xoff : 1; 7422 u64 drain : 1; 7423 u64 reserved_2 : 1; 7424 u64 drain_irq : 1; 7425 u64 reserved_4_63 : 60; 7426 } s; 7427 /* struct nixx_af_tl2x_sw_xoff_s cn; */ 7428}; 7429 7430static inline u64 NIXX_AF_TL2X_SW_XOFF(u64 a) 7431 __attribute__ ((pure, always_inline)); 7432static inline u64 NIXX_AF_TL2X_SW_XOFF(u64 a) 7433{ 7434 return 0xe70 + 0x10000 * a; 7435} 7436 7437/** 7438 * Register (RVU_PF_BAR0) nix#_af_tl2#_topology 7439 * 7440 * NIX AF Transmit Level 2 Topology Registers 7441 */ 7442union nixx_af_tl2x_topology { 7443 u64 u; 7444 struct nixx_af_tl2x_topology_s { 7445 u64 reserved_0 : 1; 7446 u64 rr_prio : 4; 7447 u64 reserved_5_31 : 27; 7448 u64 prio_anchor : 8; 7449 u64 reserved_40_63 : 24; 7450 } s; 7451 /* struct nixx_af_tl2x_topology_s cn; */ 7452}; 7453 7454static inline u64 NIXX_AF_TL2X_TOPOLOGY(u64 a) 7455 __attribute__ ((pure, always_inline)); 7456static inline u64 NIXX_AF_TL2X_TOPOLOGY(u64 a) 7457{ 7458 return 0xe80 + 0x10000 * a; 7459} 7460 7461/** 7462 * Register (RVU_PF_BAR0) nix#_af_tl2#_yellow 7463 * 7464 * INTERNAL: NIX Transmit Level 2 Yellow State Debug Register This 7465 * register has the same bit fields as NIX_AF_TL1()_YELLOW. 7466 */ 7467union nixx_af_tl2x_yellow { 7468 u64 u; 7469 struct nixx_af_tl2x_yellow_s { 7470 u64 tail : 8; 7471 u64 reserved_8_9 : 2; 7472 u64 head : 8; 7473 u64 reserved_18_63 : 46; 7474 } s; 7475 /* struct nixx_af_tl2x_yellow_s cn; */ 7476}; 7477 7478static inline u64 NIXX_AF_TL2X_YELLOW(u64 a) 7479 __attribute__ ((pure, always_inline)); 7480static inline u64 NIXX_AF_TL2X_YELLOW(u64 a) 7481{ 7482 return 0xea0 + 0x10000 * a; 7483} 7484 7485/** 7486 * Register (RVU_PF_BAR0) nix#_af_tl2_const 7487 * 7488 * NIX AF Transmit Level 2 Constants Register This register contains 7489 * constants for software discovery. 7490 */ 7491union nixx_af_tl2_const { 7492 u64 u; 7493 struct nixx_af_tl2_const_s { 7494 u64 count : 16; 7495 u64 reserved_16_63 : 48; 7496 } s; 7497 /* struct nixx_af_tl2_const_s cn; */ 7498}; 7499 7500static inline u64 NIXX_AF_TL2_CONST(void) 7501 __attribute__ ((pure, always_inline)); 7502static inline u64 NIXX_AF_TL2_CONST(void) 7503{ 7504 return 0x78; 7505} 7506 7507/** 7508 * Register (RVU_PF_BAR0) nix#_af_tl3#_cir 7509 * 7510 * NIX AF Transmit Level 3 Committed Information Rate Registers This 7511 * register has the same bit fields as NIX_AF_TL1()_CIR. 7512 */ 7513union nixx_af_tl3x_cir { 7514 u64 u; 7515 struct nixx_af_tl3x_cir_s { 7516 u64 enable : 1; 7517 u64 rate_mantissa : 8; 7518 u64 rate_exponent : 4; 7519 u64 rate_divider_exponent : 4; 7520 u64 reserved_17_28 : 12; 7521 u64 burst_mantissa : 8; 7522 u64 burst_exponent : 4; 7523 u64 reserved_41_63 : 23; 7524 } s; 7525 /* struct nixx_af_tl3x_cir_s cn; */ 7526}; 7527 7528static inline u64 NIXX_AF_TL3X_CIR(u64 a) 7529 __attribute__ ((pure, always_inline)); 7530static inline u64 NIXX_AF_TL3X_CIR(u64 a) 7531{ 7532 return 0x1020 + 0x10000 * a; 7533} 7534 7535/** 7536 * Register (RVU_PF_BAR0) nix#_af_tl3#_green 7537 * 7538 * INTERNAL: NIX Transmit Level 3 Green State Debug Register 7539 */ 7540union nixx_af_tl3x_green { 7541 u64 u; 7542 struct nixx_af_tl3x_green_s { 7543 u64 tail : 9; 7544 u64 reserved_9 : 1; 7545 u64 head : 9; 7546 u64 reserved_19 : 1; 7547 u64 active_vec : 20; 7548 u64 rr_active : 1; 7549 u64 reserved_41_63 : 23; 7550 } s; 7551 /* struct nixx_af_tl3x_green_s cn; */ 7552}; 7553 7554static inline u64 NIXX_AF_TL3X_GREEN(u64 a) 7555 __attribute__ ((pure, always_inline)); 7556static inline u64 NIXX_AF_TL3X_GREEN(u64 a) 7557{ 7558 return 0x1090 + 0x10000 * a; 7559} 7560 7561/** 7562 * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug0 7563 * 7564 * NIX AF Transmit Level 3 Meta Descriptor Debug 0 Registers See 7565 * NIX_AF_TL1()_MD_DEBUG0. 7566 */ 7567union nixx_af_tl3x_md_debug0 { 7568 u64 u; 7569 struct nixx_af_tl3x_md_debug0_s { 7570 u64 pmd0_length : 16; 7571 u64 pmd1_length : 16; 7572 u64 pmd0_vld : 1; 7573 u64 pmd1_vld : 1; 7574 u64 reserved_34_45 : 12; 7575 u64 drain_pri : 1; 7576 u64 drain : 1; 7577 u64 c_con : 1; 7578 u64 p_con : 1; 7579 u64 reserved_50_51 : 2; 7580 u64 child : 10; 7581 u64 reserved_62 : 1; 7582 u64 pmd_count : 1; 7583 } s; 7584 /* struct nixx_af_tl3x_md_debug0_s cn96xxp1; */ 7585 struct nixx_af_tl3x_md_debug0_cn96xxp3 { 7586 u64 pmd0_length : 16; 7587 u64 reserved_16_31 : 16; 7588 u64 pmd0_vld : 1; 7589 u64 reserved_33 : 1; 7590 u64 reserved_34_45 : 12; 7591 u64 reserved_46 : 1; 7592 u64 reserved_47 : 1; 7593 u64 c_con : 1; 7594 u64 p_con : 1; 7595 u64 reserved_50_51 : 2; 7596 u64 child : 10; 7597 u64 reserved_62 : 1; 7598 u64 reserved_63 : 1; 7599 } cn96xxp3; 7600 /* struct nixx_af_tl3x_md_debug0_s cnf95xx; */ 7601}; 7602 7603static inline u64 NIXX_AF_TL3X_MD_DEBUG0(u64 a) 7604 __attribute__ ((pure, always_inline)); 7605static inline u64 NIXX_AF_TL3X_MD_DEBUG0(u64 a) 7606{ 7607 return 0x10c0 + 0x10000 * a; 7608} 7609 7610/** 7611 * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug1 7612 * 7613 * NIX AF Transmit Level 3 Meta Descriptor Debug 1 Registers Packet meta 7614 * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0. 7615 */ 7616union nixx_af_tl3x_md_debug1 { 7617 u64 u; 7618 struct nixx_af_tl3x_md_debug1_s { 7619 u64 reserved_0_5 : 6; 7620 u64 red_algo_override : 2; 7621 u64 cir_dis : 1; 7622 u64 pir_dis : 1; 7623 u64 adjust : 9; 7624 u64 uid : 4; 7625 u64 reserved_23 : 1; 7626 u64 bubble : 1; 7627 u64 color : 2; 7628 u64 pse_pkt_id : 9; 7629 u64 reserved_36 : 1; 7630 u64 tx_pkt_p2x : 2; 7631 u64 sqm_pkt_id : 13; 7632 u64 mdq_idx : 10; 7633 u64 reserved_62 : 1; 7634 u64 vld : 1; 7635 } s; 7636 struct nixx_af_tl3x_md_debug1_cn96xxp1 { 7637 u64 reserved_0_5 : 6; 7638 u64 red_algo_override : 2; 7639 u64 cir_dis : 1; 7640 u64 pir_dis : 1; 7641 u64 adjust : 9; 7642 u64 uid : 4; 7643 u64 drain : 1; 7644 u64 bubble : 1; 7645 u64 color : 2; 7646 u64 pse_pkt_id : 9; 7647 u64 reserved_36 : 1; 7648 u64 tx_pkt_p2x : 2; 7649 u64 sqm_pkt_id : 13; 7650 u64 mdq_idx : 10; 7651 u64 reserved_62 : 1; 7652 u64 vld : 1; 7653 } cn96xxp1; 7654 struct nixx_af_tl3x_md_debug1_cn96xxp3 { 7655 u64 reserved_0_5 : 6; 7656 u64 red_algo_override : 2; 7657 u64 cir_dis : 1; 7658 u64 pir_dis : 1; 7659 u64 adjust : 9; 7660 u64 reserved_19_22 : 4; 7661 u64 flush : 1; 7662 u64 bubble : 1; 7663 u64 color : 2; 7664 u64 pse_pkt_id : 9; 7665 u64 reserved_36 : 1; 7666 u64 tx_pkt_p2x : 2; 7667 u64 sqm_pkt_id : 13; 7668 u64 mdq_idx : 10; 7669 u64 reserved_62 : 1; 7670 u64 vld : 1; 7671 } cn96xxp3; 7672 /* struct nixx_af_tl3x_md_debug1_cn96xxp1 cnf95xx; */ 7673}; 7674 7675static inline u64 NIXX_AF_TL3X_MD_DEBUG1(u64 a) 7676 __attribute__ ((pure, always_inline)); 7677static inline u64 NIXX_AF_TL3X_MD_DEBUG1(u64 a) 7678{ 7679 return 0x10c8 + 0x10000 * a; 7680} 7681 7682/** 7683 * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug2 7684 * 7685 * NIX AF Transmit Level 3 Meta Descriptor Debug 2 Registers Packet meta 7686 * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0. 7687 */ 7688union nixx_af_tl3x_md_debug2 { 7689 u64 u; 7690 struct nixx_af_tl3x_md_debug2_s { 7691 u64 reserved_0_5 : 6; 7692 u64 red_algo_override : 2; 7693 u64 cir_dis : 1; 7694 u64 pir_dis : 1; 7695 u64 adjust : 9; 7696 u64 uid : 4; 7697 u64 reserved_23 : 1; 7698 u64 bubble : 1; 7699 u64 color : 2; 7700 u64 pse_pkt_id : 9; 7701 u64 reserved_36 : 1; 7702 u64 tx_pkt_p2x : 2; 7703 u64 sqm_pkt_id : 13; 7704 u64 mdq_idx : 10; 7705 u64 reserved_62 : 1; 7706 u64 vld : 1; 7707 } s; 7708 struct nixx_af_tl3x_md_debug2_cn96xxp1 { 7709 u64 reserved_0_5 : 6; 7710 u64 red_algo_override : 2; 7711 u64 cir_dis : 1; 7712 u64 pir_dis : 1; 7713 u64 adjust : 9; 7714 u64 uid : 4; 7715 u64 drain : 1; 7716 u64 bubble : 1; 7717 u64 color : 2; 7718 u64 pse_pkt_id : 9; 7719 u64 reserved_36 : 1; 7720 u64 tx_pkt_p2x : 2; 7721 u64 sqm_pkt_id : 13; 7722 u64 mdq_idx : 10; 7723 u64 reserved_62 : 1; 7724 u64 vld : 1; 7725 } cn96xxp1; 7726 struct nixx_af_tl3x_md_debug2_cn96xxp3 { 7727 u64 reserved_0_5 : 6; 7728 u64 red_algo_override : 2; 7729 u64 cir_dis : 1; 7730 u64 pir_dis : 1; 7731 u64 adjust : 9; 7732 u64 reserved_19_22 : 4; 7733 u64 flush : 1; 7734 u64 bubble : 1; 7735 u64 color : 2; 7736 u64 pse_pkt_id : 9; 7737 u64 reserved_36 : 1; 7738 u64 tx_pkt_p2x : 2; 7739 u64 sqm_pkt_id : 13; 7740 u64 mdq_idx : 10; 7741 u64 reserved_62 : 1; 7742 u64 vld : 1; 7743 } cn96xxp3; 7744 /* struct nixx_af_tl3x_md_debug2_cn96xxp1 cnf95xx; */ 7745}; 7746 7747static inline u64 NIXX_AF_TL3X_MD_DEBUG2(u64 a) 7748 __attribute__ ((pure, always_inline)); 7749static inline u64 NIXX_AF_TL3X_MD_DEBUG2(u64 a) 7750{ 7751 return 0x10d0 + 0x10000 * a; 7752} 7753 7754/** 7755 * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug3 7756 * 7757 * NIX AF Transmit Level 3 Meta Descriptor Debug 3 Registers Flush meta 7758 * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0. 7759 */ 7760union nixx_af_tl3x_md_debug3 { 7761 u64 u; 7762 struct nixx_af_tl3x_md_debug3_s { 7763 u64 reserved_0_36 : 37; 7764 u64 tx_pkt_p2x : 2; 7765 u64 sqm_pkt_id : 13; 7766 u64 mdq_idx : 10; 7767 u64 reserved_62 : 1; 7768 u64 vld : 1; 7769 } s; 7770 /* struct nixx_af_tl3x_md_debug3_s cn96xxp1; */ 7771 struct nixx_af_tl3x_md_debug3_cn96xxp3 { 7772 u64 reserved_0_36 : 37; 7773 u64 reserved_37_38 : 2; 7774 u64 reserved_39_51 : 13; 7775 u64 reserved_52_61 : 10; 7776 u64 reserved_62 : 1; 7777 u64 reserved_63 : 1; 7778 } cn96xxp3; 7779 /* struct nixx_af_tl3x_md_debug3_s cnf95xx; */ 7780}; 7781 7782static inline u64 NIXX_AF_TL3X_MD_DEBUG3(u64 a) 7783 __attribute__ ((pure, always_inline)); 7784static inline u64 NIXX_AF_TL3X_MD_DEBUG3(u64 a) 7785{ 7786 return 0x10d8 + 0x10000 * a; 7787} 7788 7789/** 7790 * Register (RVU_PF_BAR0) nix#_af_tl3#_parent 7791 * 7792 * NIX AF Transmit Level 3 Parent Registers 7793 */ 7794union nixx_af_tl3x_parent { 7795 u64 u; 7796 struct nixx_af_tl3x_parent_s { 7797 u64 reserved_0_15 : 16; 7798 u64 parent : 8; 7799 u64 reserved_24_63 : 40; 7800 } s; 7801 /* struct nixx_af_tl3x_parent_s cn; */ 7802}; 7803 7804static inline u64 NIXX_AF_TL3X_PARENT(u64 a) 7805 __attribute__ ((pure, always_inline)); 7806static inline u64 NIXX_AF_TL3X_PARENT(u64 a) 7807{ 7808 return 0x1088 + 0x10000 * a; 7809} 7810 7811/** 7812 * Register (RVU_PF_BAR0) nix#_af_tl3#_pir 7813 * 7814 * NIX AF Transmit Level 3 Peak Information Rate Registers This register 7815 * has the same bit fields as NIX_AF_TL1()_CIR. 7816 */ 7817union nixx_af_tl3x_pir { 7818 u64 u; 7819 struct nixx_af_tl3x_pir_s { 7820 u64 enable : 1; 7821 u64 rate_mantissa : 8; 7822 u64 rate_exponent : 4; 7823 u64 rate_divider_exponent : 4; 7824 u64 reserved_17_28 : 12; 7825 u64 burst_mantissa : 8; 7826 u64 burst_exponent : 4; 7827 u64 reserved_41_63 : 23; 7828 } s; 7829 /* struct nixx_af_tl3x_pir_s cn; */ 7830}; 7831 7832static inline u64 NIXX_AF_TL3X_PIR(u64 a) 7833 __attribute__ ((pure, always_inline)); 7834static inline u64 NIXX_AF_TL3X_PIR(u64 a) 7835{ 7836 return 0x1030 + 0x10000 * a; 7837} 7838 7839/** 7840 * Register (RVU_PF_BAR0) nix#_af_tl3#_pointers 7841 * 7842 * INTERNAL: NIX Transmit Level 3 Linked List Pointers Debug Register 7843 * This register has the same bit fields as NIX_AF_TL2()_POINTERS. 7844 */ 7845union nixx_af_tl3x_pointers { 7846 u64 u; 7847 struct nixx_af_tl3x_pointers_s { 7848 u64 next : 8; 7849 u64 reserved_8_15 : 8; 7850 u64 prev : 8; 7851 u64 reserved_24_63 : 40; 7852 } s; 7853 /* struct nixx_af_tl3x_pointers_s cn; */ 7854}; 7855 7856static inline u64 NIXX_AF_TL3X_POINTERS(u64 a) 7857 __attribute__ ((pure, always_inline)); 7858static inline u64 NIXX_AF_TL3X_POINTERS(u64 a) 7859{ 7860 return 0x1060 + 0x10000 * a; 7861} 7862 7863/** 7864 * Register (RVU_PF_BAR0) nix#_af_tl3#_red 7865 * 7866 * INTERNAL: NIX Transmit Level 3 Red State Debug Register This register 7867 * has the same bit fields as NIX_AF_TL3()_YELLOW. 7868 */ 7869union nixx_af_tl3x_red { 7870 u64 u; 7871 struct nixx_af_tl3x_red_s { 7872 u64 tail : 9; 7873 u64 reserved_9 : 1; 7874 u64 head : 9; 7875 u64 reserved_19_63 : 45; 7876 } s; 7877 /* struct nixx_af_tl3x_red_s cn; */ 7878}; 7879 7880static inline u64 NIXX_AF_TL3X_RED(u64 a) 7881 __attribute__ ((pure, always_inline)); 7882static inline u64 NIXX_AF_TL3X_RED(u64 a) 7883{ 7884 return 0x10b0 + 0x10000 * a; 7885} 7886 7887/** 7888 * Register (RVU_PF_BAR0) nix#_af_tl3#_sched_state 7889 * 7890 * NIX AF Transmit Level 3 Scheduling Control State Registers This 7891 * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE. 7892 */ 7893union nixx_af_tl3x_sched_state { 7894 u64 u; 7895 struct nixx_af_tl3x_sched_state_s { 7896 u64 rr_count : 25; 7897 u64 reserved_25_63 : 39; 7898 } s; 7899 /* struct nixx_af_tl3x_sched_state_s cn; */ 7900}; 7901 7902static inline u64 NIXX_AF_TL3X_SCHED_STATE(u64 a) 7903 __attribute__ ((pure, always_inline)); 7904static inline u64 NIXX_AF_TL3X_SCHED_STATE(u64 a) 7905{ 7906 return 0x1040 + 0x10000 * a; 7907} 7908 7909/** 7910 * Register (RVU_PF_BAR0) nix#_af_tl3#_schedule 7911 * 7912 * NIX AF Transmit Level 3 Scheduling Control Registers This register has 7913 * the same bit fields as NIX_AF_TL2()_SCHEDULE. 7914 */ 7915union nixx_af_tl3x_schedule { 7916 u64 u; 7917 struct nixx_af_tl3x_schedule_s { 7918 u64 rr_quantum : 24; 7919 u64 prio : 4; 7920 u64 reserved_28_63 : 36; 7921 } s; 7922 /* struct nixx_af_tl3x_schedule_s cn; */ 7923}; 7924 7925static inline u64 NIXX_AF_TL3X_SCHEDULE(u64 a) 7926 __attribute__ ((pure, always_inline)); 7927static inline u64 NIXX_AF_TL3X_SCHEDULE(u64 a) 7928{ 7929 return 0x1000 + 0x10000 * a; 7930} 7931 7932/** 7933 * Register (RVU_PF_BAR0) nix#_af_tl3#_shape 7934 * 7935 * NIX AF Transmit Level 3 Shaping Control Registers 7936 */ 7937union nixx_af_tl3x_shape { 7938 u64 u; 7939 struct nixx_af_tl3x_shape_s { 7940 u64 adjust : 9; 7941 u64 red_algo : 2; 7942 u64 red_disable : 1; 7943 u64 yellow_disable : 1; 7944 u64 reserved_13_23 : 11; 7945 u64 length_disable : 1; 7946 u64 schedule_list : 2; 7947 u64 reserved_27_63 : 37; 7948 } s; 7949 /* struct nixx_af_tl3x_shape_s cn; */ 7950}; 7951 7952static inline u64 NIXX_AF_TL3X_SHAPE(u64 a) 7953 __attribute__ ((pure, always_inline)); 7954static inline u64 NIXX_AF_TL3X_SHAPE(u64 a) 7955{ 7956 return 0x1010 + 0x10000 * a; 7957} 7958 7959/** 7960 * Register (RVU_PF_BAR0) nix#_af_tl3#_shape_state 7961 * 7962 * NIX AF Transmit Level 3 Shaping State Registers This register has the 7963 * same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must not be 7964 * written during normal operation. 7965 */ 7966union nixx_af_tl3x_shape_state { 7967 u64 u; 7968 struct nixx_af_tl3x_shape_state_s { 7969 u64 cir_accum : 26; 7970 u64 pir_accum : 26; 7971 u64 color : 2; 7972 u64 reserved_54_63 : 10; 7973 } s; 7974 /* struct nixx_af_tl3x_shape_state_s cn; */ 7975}; 7976 7977static inline u64 NIXX_AF_TL3X_SHAPE_STATE(u64 a) 7978 __attribute__ ((pure, always_inline)); 7979static inline u64 NIXX_AF_TL3X_SHAPE_STATE(u64 a) 7980{ 7981 return 0x1050 + 0x10000 * a; 7982} 7983 7984/** 7985 * Register (RVU_PF_BAR0) nix#_af_tl3#_sw_xoff 7986 * 7987 * NIX AF Transmit Level 3 Software Controlled XOFF Registers This 7988 * register has the same bit fields as NIX_AF_TL1()_SW_XOFF 7989 */ 7990union nixx_af_tl3x_sw_xoff { 7991 u64 u; 7992 struct nixx_af_tl3x_sw_xoff_s { 7993 u64 xoff : 1; 7994 u64 drain : 1; 7995 u64 reserved_2 : 1; 7996 u64 drain_irq : 1; 7997 u64 reserved_4_63 : 60; 7998 } s; 7999 /* struct nixx_af_tl3x_sw_xoff_s cn; */ 8000}; 8001 8002static inline u64 NIXX_AF_TL3X_SW_XOFF(u64 a) 8003 __attribute__ ((pure, always_inline)); 8004static inline u64 NIXX_AF_TL3X_SW_XOFF(u64 a) 8005{ 8006 return 0x1070 + 0x10000 * a; 8007} 8008 8009/** 8010 * Register (RVU_PF_BAR0) nix#_af_tl3#_topology 8011 * 8012 * NIX AF Transmit Level 3 Topology Registers 8013 */ 8014union nixx_af_tl3x_topology { 8015 u64 u; 8016 struct nixx_af_tl3x_topology_s { 8017 u64 reserved_0 : 1; 8018 u64 rr_prio : 4; 8019 u64 reserved_5_31 : 27; 8020 u64 prio_anchor : 9; 8021 u64 reserved_41_63 : 23; 8022 } s; 8023 /* struct nixx_af_tl3x_topology_s cn; */ 8024}; 8025 8026static inline u64 NIXX_AF_TL3X_TOPOLOGY(u64 a) 8027 __attribute__ ((pure, always_inline)); 8028static inline u64 NIXX_AF_TL3X_TOPOLOGY(u64 a) 8029{ 8030 return 0x1080 + 0x10000 * a; 8031} 8032 8033/** 8034 * Register (RVU_PF_BAR0) nix#_af_tl3#_yellow 8035 * 8036 * INTERNAL: NIX Transmit Level 3 Yellow State Debug Register 8037 */ 8038union nixx_af_tl3x_yellow { 8039 u64 u; 8040 struct nixx_af_tl3x_yellow_s { 8041 u64 tail : 9; 8042 u64 reserved_9 : 1; 8043 u64 head : 9; 8044 u64 reserved_19_63 : 45; 8045 } s; 8046 /* struct nixx_af_tl3x_yellow_s cn; */ 8047}; 8048 8049static inline u64 NIXX_AF_TL3X_YELLOW(u64 a) 8050 __attribute__ ((pure, always_inline)); 8051static inline u64 NIXX_AF_TL3X_YELLOW(u64 a) 8052{ 8053 return 0x10a0 + 0x10000 * a; 8054} 8055 8056/** 8057 * Register (RVU_PF_BAR0) nix#_af_tl3_const 8058 * 8059 * NIX AF Transmit Level 3 Constants Register This register contains 8060 * constants for software discovery. 8061 */ 8062union nixx_af_tl3_const { 8063 u64 u; 8064 struct nixx_af_tl3_const_s { 8065 u64 count : 16; 8066 u64 reserved_16_63 : 48; 8067 } s; 8068 /* struct nixx_af_tl3_const_s cn; */ 8069}; 8070 8071static inline u64 NIXX_AF_TL3_CONST(void) 8072 __attribute__ ((pure, always_inline)); 8073static inline u64 NIXX_AF_TL3_CONST(void) 8074{ 8075 return 0x80; 8076} 8077 8078/** 8079 * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_bp_status 8080 * 8081 * NIX AF Transmit Level 3/2 Backpressure Status Registers 8082 */ 8083union nixx_af_tl3_tl2x_bp_status { 8084 u64 u; 8085 struct nixx_af_tl3_tl2x_bp_status_s { 8086 u64 hw_xoff : 1; 8087 u64 reserved_1_63 : 63; 8088 } s; 8089 /* struct nixx_af_tl3_tl2x_bp_status_s cn; */ 8090}; 8091 8092static inline u64 NIXX_AF_TL3_TL2X_BP_STATUS(u64 a) 8093 __attribute__ ((pure, always_inline)); 8094static inline u64 NIXX_AF_TL3_TL2X_BP_STATUS(u64 a) 8095{ 8096 return 0x1610 + 0x10000 * a; 8097} 8098 8099/** 8100 * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_cfg 8101 * 8102 * NIX AF Transmit Level 3/2 Configuration Registers 8103 */ 8104union nixx_af_tl3_tl2x_cfg { 8105 u64 u; 8106 struct nixx_af_tl3_tl2x_cfg_s { 8107 u64 express : 1; 8108 u64 reserved_1_63 : 63; 8109 } s; 8110 /* struct nixx_af_tl3_tl2x_cfg_s cn; */ 8111}; 8112 8113static inline u64 NIXX_AF_TL3_TL2X_CFG(u64 a) 8114 __attribute__ ((pure, always_inline)); 8115static inline u64 NIXX_AF_TL3_TL2X_CFG(u64 a) 8116{ 8117 return 0x1600 + 0x10000 * a; 8118} 8119 8120/** 8121 * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_link#_cfg 8122 * 8123 * NIX AF Transmit Level 3/2 Link Configuration Registers These registers 8124 * specify the links and associated channels that a given TL3 or TL2 8125 * queue (depending on NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL]) can transmit 8126 * on. Each TL3/TL2 queue can be enabled to transmit on and be 8127 * backpressured by one or more links and associated channels. The last 8128 * index (LINK) is enumerated by NIX_LINK_E. 8129 */ 8130union nixx_af_tl3_tl2x_linkx_cfg { 8131 u64 u; 8132 struct nixx_af_tl3_tl2x_linkx_cfg_s { 8133 u64 relchan : 8; 8134 u64 reserved_8_11 : 4; 8135 u64 ena : 1; 8136 u64 bp_ena : 1; 8137 u64 reserved_14_63 : 50; 8138 } s; 8139 /* struct nixx_af_tl3_tl2x_linkx_cfg_s cn; */ 8140}; 8141 8142static inline u64 NIXX_AF_TL3_TL2X_LINKX_CFG(u64 a, u64 b) 8143 __attribute__ ((pure, always_inline)); 8144static inline u64 NIXX_AF_TL3_TL2X_LINKX_CFG(u64 a, u64 b) 8145{ 8146 return 0x1700 + 0x10000 * a + 8 * b; 8147} 8148 8149/** 8150 * Register (RVU_PF_BAR0) nix#_af_tl4#_bp_status 8151 * 8152 * NIX AF Transmit Level 4 Backpressure Status Registers 8153 */ 8154union nixx_af_tl4x_bp_status { 8155 u64 u; 8156 struct nixx_af_tl4x_bp_status_s { 8157 u64 hw_xoff : 1; 8158 u64 reserved_1_63 : 63; 8159 } s; 8160 /* struct nixx_af_tl4x_bp_status_s cn; */ 8161}; 8162 8163static inline u64 NIXX_AF_TL4X_BP_STATUS(u64 a) 8164 __attribute__ ((pure, always_inline)); 8165static inline u64 NIXX_AF_TL4X_BP_STATUS(u64 a) 8166{ 8167 return 0xb00 + 0x10000 * a; 8168} 8169 8170/** 8171 * Register (RVU_PF_BAR0) nix#_af_tl4#_cir 8172 * 8173 * NIX AF Transmit Level 4 Committed Information Rate Registers This 8174 * register has the same bit fields as NIX_AF_TL1()_CIR. 8175 */ 8176union nixx_af_tl4x_cir { 8177 u64 u; 8178 struct nixx_af_tl4x_cir_s { 8179 u64 enable : 1; 8180 u64 rate_mantissa : 8; 8181 u64 rate_exponent : 4; 8182 u64 rate_divider_exponent : 4; 8183 u64 reserved_17_28 : 12; 8184 u64 burst_mantissa : 8; 8185 u64 burst_exponent : 4; 8186 u64 reserved_41_63 : 23; 8187 } s; 8188 /* struct nixx_af_tl4x_cir_s cn; */ 8189}; 8190 8191static inline u64 NIXX_AF_TL4X_CIR(u64 a) 8192 __attribute__ ((pure, always_inline)); 8193static inline u64 NIXX_AF_TL4X_CIR(u64 a) 8194{ 8195 return 0x1220 + 0x10000 * a; 8196} 8197 8198/** 8199 * Register (RVU_PF_BAR0) nix#_af_tl4#_green 8200 * 8201 * INTERNAL: NIX Transmit Level 4 Green State Debug Register This 8202 * register has the same bit fields as NIX_AF_TL3()_GREEN. 8203 */ 8204union nixx_af_tl4x_green { 8205 u64 u; 8206 struct nixx_af_tl4x_green_s { 8207 u64 tail : 9; 8208 u64 reserved_9 : 1; 8209 u64 head : 9; 8210 u64 reserved_19 : 1; 8211 u64 active_vec : 20; 8212 u64 rr_active : 1; 8213 u64 reserved_41_63 : 23; 8214 } s; 8215 /* struct nixx_af_tl4x_green_s cn; */ 8216}; 8217 8218static inline u64 NIXX_AF_TL4X_GREEN(u64 a) 8219 __attribute__ ((pure, always_inline)); 8220static inline u64 NIXX_AF_TL4X_GREEN(u64 a) 8221{ 8222 return 0x1290 + 0x10000 * a; 8223} 8224 8225/** 8226 * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug0 8227 * 8228 * NIX AF Transmit Level 4 Meta Descriptor Debug 0 Registers See 8229 * NIX_AF_TL1()_MD_DEBUG0. 8230 */ 8231union nixx_af_tl4x_md_debug0 { 8232 u64 u; 8233 struct nixx_af_tl4x_md_debug0_s { 8234 u64 pmd0_length : 16; 8235 u64 pmd1_length : 16; 8236 u64 pmd0_vld : 1; 8237 u64 pmd1_vld : 1; 8238 u64 reserved_34_45 : 12; 8239 u64 drain_pri : 1; 8240 u64 drain : 1; 8241 u64 c_con : 1; 8242 u64 p_con : 1; 8243 u64 reserved_50_51 : 2; 8244 u64 child : 10; 8245 u64 reserved_62 : 1; 8246 u64 pmd_count : 1; 8247 } s; 8248 /* struct nixx_af_tl4x_md_debug0_s cn96xxp1; */ 8249 struct nixx_af_tl4x_md_debug0_cn96xxp3 { 8250 u64 pmd0_length : 16; 8251 u64 reserved_16_31 : 16; 8252 u64 pmd0_vld : 1; 8253 u64 reserved_33 : 1; 8254 u64 reserved_34_45 : 12; 8255 u64 reserved_46 : 1; 8256 u64 reserved_47 : 1; 8257 u64 c_con : 1; 8258 u64 p_con : 1; 8259 u64 reserved_50_51 : 2; 8260 u64 child : 10; 8261 u64 reserved_62 : 1; 8262 u64 reserved_63 : 1; 8263 } cn96xxp3; 8264 /* struct nixx_af_tl4x_md_debug0_s cnf95xx; */ 8265}; 8266 8267static inline u64 NIXX_AF_TL4X_MD_DEBUG0(u64 a) 8268 __attribute__ ((pure, always_inline)); 8269static inline u64 NIXX_AF_TL4X_MD_DEBUG0(u64 a) 8270{ 8271 return 0x12c0 + 0x10000 * a; 8272} 8273 8274/** 8275 * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug1 8276 * 8277 * NIX AF Transmit Level 4 Meta Descriptor Debug 1 Registers Packet meta 8278 * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0. 8279 */ 8280union nixx_af_tl4x_md_debug1 { 8281 u64 u; 8282 struct nixx_af_tl4x_md_debug1_s { 8283 u64 reserved_0_5 : 6; 8284 u64 red_algo_override : 2; 8285 u64 cir_dis : 1; 8286 u64 pir_dis : 1; 8287 u64 adjust : 9; 8288 u64 uid : 4; 8289 u64 reserved_23 : 1; 8290 u64 bubble : 1; 8291 u64 color : 2; 8292 u64 pse_pkt_id : 9; 8293 u64 reserved_36 : 1; 8294 u64 tx_pkt_p2x : 2; 8295 u64 sqm_pkt_id : 13; 8296 u64 mdq_idx : 10; 8297 u64 reserved_62 : 1; 8298 u64 vld : 1; 8299 } s; 8300 struct nixx_af_tl4x_md_debug1_cn96xxp1 { 8301 u64 reserved_0_5 : 6; 8302 u64 red_algo_override : 2; 8303 u64 cir_dis : 1; 8304 u64 pir_dis : 1; 8305 u64 adjust : 9; 8306 u64 uid : 4; 8307 u64 drain : 1; 8308 u64 bubble : 1; 8309 u64 color : 2; 8310 u64 pse_pkt_id : 9; 8311 u64 reserved_36 : 1; 8312 u64 tx_pkt_p2x : 2; 8313 u64 sqm_pkt_id : 13; 8314 u64 mdq_idx : 10; 8315 u64 reserved_62 : 1; 8316 u64 vld : 1; 8317 } cn96xxp1; 8318 struct nixx_af_tl4x_md_debug1_cn96xxp3 { 8319 u64 reserved_0_5 : 6; 8320 u64 red_algo_override : 2; 8321 u64 cir_dis : 1; 8322 u64 pir_dis : 1; 8323 u64 adjust : 9; 8324 u64 reserved_19_22 : 4; 8325 u64 flush : 1; 8326 u64 bubble : 1; 8327 u64 color : 2; 8328 u64 pse_pkt_id : 9; 8329 u64 reserved_36 : 1; 8330 u64 tx_pkt_p2x : 2; 8331 u64 sqm_pkt_id : 13; 8332 u64 mdq_idx : 10; 8333 u64 reserved_62 : 1; 8334 u64 vld : 1; 8335 } cn96xxp3; 8336 /* struct nixx_af_tl4x_md_debug1_cn96xxp1 cnf95xx; */ 8337}; 8338 8339static inline u64 NIXX_AF_TL4X_MD_DEBUG1(u64 a) 8340 __attribute__ ((pure, always_inline)); 8341static inline u64 NIXX_AF_TL4X_MD_DEBUG1(u64 a) 8342{ 8343 return 0x12c8 + 0x10000 * a; 8344} 8345 8346/** 8347 * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug2 8348 * 8349 * NIX AF Transmit Level 4 Meta Descriptor Debug 2 Registers Packet meta 8350 * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0. 8351 */ 8352union nixx_af_tl4x_md_debug2 { 8353 u64 u; 8354 struct nixx_af_tl4x_md_debug2_s { 8355 u64 reserved_0_5 : 6; 8356 u64 red_algo_override : 2; 8357 u64 cir_dis : 1; 8358 u64 pir_dis : 1; 8359 u64 adjust : 9; 8360 u64 uid : 4; 8361 u64 reserved_23 : 1; 8362 u64 bubble : 1; 8363 u64 color : 2; 8364 u64 pse_pkt_id : 9; 8365 u64 reserved_36 : 1; 8366 u64 tx_pkt_p2x : 2; 8367 u64 sqm_pkt_id : 13; 8368 u64 mdq_idx : 10; 8369 u64 reserved_62 : 1; 8370 u64 vld : 1; 8371 } s; 8372 struct nixx_af_tl4x_md_debug2_cn96xxp1 { 8373 u64 reserved_0_5 : 6; 8374 u64 red_algo_override : 2; 8375 u64 cir_dis : 1; 8376 u64 pir_dis : 1; 8377 u64 adjust : 9; 8378 u64 uid : 4; 8379 u64 drain : 1; 8380 u64 bubble : 1; 8381 u64 color : 2; 8382 u64 pse_pkt_id : 9; 8383 u64 reserved_36 : 1; 8384 u64 tx_pkt_p2x : 2; 8385 u64 sqm_pkt_id : 13; 8386 u64 mdq_idx : 10; 8387 u64 reserved_62 : 1; 8388 u64 vld : 1; 8389 } cn96xxp1; 8390 struct nixx_af_tl4x_md_debug2_cn96xxp3 { 8391 u64 reserved_0_5 : 6; 8392 u64 red_algo_override : 2; 8393 u64 cir_dis : 1; 8394 u64 pir_dis : 1; 8395 u64 adjust : 9; 8396 u64 reserved_19_22 : 4; 8397 u64 flush : 1; 8398 u64 bubble : 1; 8399 u64 color : 2; 8400 u64 pse_pkt_id : 9; 8401 u64 reserved_36 : 1; 8402 u64 tx_pkt_p2x : 2; 8403 u64 sqm_pkt_id : 13; 8404 u64 mdq_idx : 10; 8405 u64 reserved_62 : 1; 8406 u64 vld : 1; 8407 } cn96xxp3; 8408 /* struct nixx_af_tl4x_md_debug2_cn96xxp1 cnf95xx; */ 8409}; 8410 8411static inline u64 NIXX_AF_TL4X_MD_DEBUG2(u64 a) 8412 __attribute__ ((pure, always_inline)); 8413static inline u64 NIXX_AF_TL4X_MD_DEBUG2(u64 a) 8414{ 8415 return 0x12d0 + 0x10000 * a; 8416} 8417 8418/** 8419 * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug3 8420 * 8421 * NIX AF Transmit Level 4 Meta Descriptor Debug 3 Registers Flush meta 8422 * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0. 8423 */ 8424union nixx_af_tl4x_md_debug3 { 8425 u64 u; 8426 struct nixx_af_tl4x_md_debug3_s { 8427 u64 reserved_0_36 : 37; 8428 u64 tx_pkt_p2x : 2; 8429 u64 sqm_pkt_id : 13; 8430 u64 mdq_idx : 10; 8431 u64 reserved_62 : 1; 8432 u64 vld : 1; 8433 } s; 8434 /* struct nixx_af_tl4x_md_debug3_s cn96xxp1; */ 8435 struct nixx_af_tl4x_md_debug3_cn96xxp3 { 8436 u64 reserved_0_36 : 37; 8437 u64 reserved_37_38 : 2; 8438 u64 reserved_39_51 : 13; 8439 u64 reserved_52_61 : 10; 8440 u64 reserved_62 : 1; 8441 u64 reserved_63 : 1; 8442 } cn96xxp3; 8443 /* struct nixx_af_tl4x_md_debug3_s cnf95xx; */ 8444}; 8445 8446static inline u64 NIXX_AF_TL4X_MD_DEBUG3(u64 a) 8447 __attribute__ ((pure, always_inline)); 8448static inline u64 NIXX_AF_TL4X_MD_DEBUG3(u64 a) 8449{ 8450 return 0x12d8 + 0x10000 * a; 8451} 8452 8453/** 8454 * Register (RVU_PF_BAR0) nix#_af_tl4#_parent 8455 * 8456 * NIX AF Transmit Level 4 Parent Registers 8457 */ 8458union nixx_af_tl4x_parent { 8459 u64 u; 8460 struct nixx_af_tl4x_parent_s { 8461 u64 reserved_0_15 : 16; 8462 u64 parent : 8; 8463 u64 reserved_24_63 : 40; 8464 } s; 8465 /* struct nixx_af_tl4x_parent_s cn; */ 8466}; 8467 8468static inline u64 NIXX_AF_TL4X_PARENT(u64 a) 8469 __attribute__ ((pure, always_inline)); 8470static inline u64 NIXX_AF_TL4X_PARENT(u64 a) 8471{ 8472 return 0x1288 + 0x10000 * a; 8473} 8474 8475/** 8476 * Register (RVU_PF_BAR0) nix#_af_tl4#_pir 8477 * 8478 * NIX AF Transmit Level 4 Peak Information Rate Registers This register 8479 * has the same bit fields as NIX_AF_TL1()_CIR. 8480 */ 8481union nixx_af_tl4x_pir { 8482 u64 u; 8483 struct nixx_af_tl4x_pir_s { 8484 u64 enable : 1; 8485 u64 rate_mantissa : 8; 8486 u64 rate_exponent : 4; 8487 u64 rate_divider_exponent : 4; 8488 u64 reserved_17_28 : 12; 8489 u64 burst_mantissa : 8; 8490 u64 burst_exponent : 4; 8491 u64 reserved_41_63 : 23; 8492 } s; 8493 /* struct nixx_af_tl4x_pir_s cn; */ 8494}; 8495 8496static inline u64 NIXX_AF_TL4X_PIR(u64 a) 8497 __attribute__ ((pure, always_inline)); 8498static inline u64 NIXX_AF_TL4X_PIR(u64 a) 8499{ 8500 return 0x1230 + 0x10000 * a; 8501} 8502 8503/** 8504 * Register (RVU_PF_BAR0) nix#_af_tl4#_pointers 8505 * 8506 * INTERNAL: NIX Transmit Level 4 Linked List Pointers Debug Register 8507 * This register has the same bit fields as NIX_AF_TL2()_POINTERS. 8508 */ 8509union nixx_af_tl4x_pointers { 8510 u64 u; 8511 struct nixx_af_tl4x_pointers_s { 8512 u64 next : 9; 8513 u64 reserved_9_15 : 7; 8514 u64 prev : 9; 8515 u64 reserved_25_63 : 39; 8516 } s; 8517 /* struct nixx_af_tl4x_pointers_s cn; */ 8518}; 8519 8520static inline u64 NIXX_AF_TL4X_POINTERS(u64 a) 8521 __attribute__ ((pure, always_inline)); 8522static inline u64 NIXX_AF_TL4X_POINTERS(u64 a) 8523{ 8524 return 0x1260 + 0x10000 * a; 8525} 8526 8527/** 8528 * Register (RVU_PF_BAR0) nix#_af_tl4#_red 8529 * 8530 * INTERNAL: NIX Transmit Level 4 Red State Debug Register This register 8531 * has the same bit fields as NIX_AF_TL3()_YELLOW. 8532 */ 8533union nixx_af_tl4x_red { 8534 u64 u; 8535 struct nixx_af_tl4x_red_s { 8536 u64 tail : 9; 8537 u64 reserved_9 : 1; 8538 u64 head : 9; 8539 u64 reserved_19_63 : 45; 8540 } s; 8541 /* struct nixx_af_tl4x_red_s cn; */ 8542}; 8543 8544static inline u64 NIXX_AF_TL4X_RED(u64 a) 8545 __attribute__ ((pure, always_inline)); 8546static inline u64 NIXX_AF_TL4X_RED(u64 a) 8547{ 8548 return 0x12b0 + 0x10000 * a; 8549} 8550 8551/** 8552 * Register (RVU_PF_BAR0) nix#_af_tl4#_sched_state 8553 * 8554 * NIX AF Transmit Level 4 Scheduling Control State Registers This 8555 * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE. 8556 */ 8557union nixx_af_tl4x_sched_state { 8558 u64 u; 8559 struct nixx_af_tl4x_sched_state_s { 8560 u64 rr_count : 25; 8561 u64 reserved_25_63 : 39; 8562 } s; 8563 /* struct nixx_af_tl4x_sched_state_s cn; */ 8564}; 8565 8566static inline u64 NIXX_AF_TL4X_SCHED_STATE(u64 a) 8567 __attribute__ ((pure, always_inline)); 8568static inline u64 NIXX_AF_TL4X_SCHED_STATE(u64 a) 8569{ 8570 return 0x1240 + 0x10000 * a; 8571} 8572 8573/** 8574 * Register (RVU_PF_BAR0) nix#_af_tl4#_schedule 8575 * 8576 * NIX AF Transmit Level 4 Scheduling Control Registers This register has 8577 * the same bit fields as NIX_AF_TL2()_SCHEDULE. 8578 */ 8579union nixx_af_tl4x_schedule { 8580 u64 u; 8581 struct nixx_af_tl4x_schedule_s { 8582 u64 rr_quantum : 24; 8583 u64 prio : 4; 8584 u64 reserved_28_63 : 36; 8585 } s; 8586 /* struct nixx_af_tl4x_schedule_s cn; */ 8587}; 8588 8589static inline u64 NIXX_AF_TL4X_SCHEDULE(u64 a) 8590 __attribute__ ((pure, always_inline)); 8591static inline u64 NIXX_AF_TL4X_SCHEDULE(u64 a) 8592{ 8593 return 0x1200 + 0x10000 * a; 8594} 8595 8596/** 8597 * Register (RVU_PF_BAR0) nix#_af_tl4#_sdp_link_cfg 8598 * 8599 * NIX AF Transmit Level 4 Link Configuration Registers These registers 8600 * specify which TL4 queues transmit to and are optionally backpressured 8601 * by SDP. 8602 */ 8603union nixx_af_tl4x_sdp_link_cfg { 8604 u64 u; 8605 struct nixx_af_tl4x_sdp_link_cfg_s { 8606 u64 relchan : 8; 8607 u64 reserved_8_11 : 4; 8608 u64 ena : 1; 8609 u64 bp_ena : 1; 8610 u64 reserved_14_63 : 50; 8611 } s; 8612 /* struct nixx_af_tl4x_sdp_link_cfg_s cn; */ 8613}; 8614 8615static inline u64 NIXX_AF_TL4X_SDP_LINK_CFG(u64 a) 8616 __attribute__ ((pure, always_inline)); 8617static inline u64 NIXX_AF_TL4X_SDP_LINK_CFG(u64 a) 8618{ 8619 return 0xb10 + 0x10000 * a; 8620} 8621 8622/** 8623 * Register (RVU_PF_BAR0) nix#_af_tl4#_shape 8624 * 8625 * NIX AF Transmit Level 4 Shaping Control Registers This register has 8626 * the same bit fields as NIX_AF_TL2()_SHAPE. 8627 */ 8628union nixx_af_tl4x_shape { 8629 u64 u; 8630 struct nixx_af_tl4x_shape_s { 8631 u64 adjust : 9; 8632 u64 red_algo : 2; 8633 u64 red_disable : 1; 8634 u64 yellow_disable : 1; 8635 u64 reserved_13_23 : 11; 8636 u64 length_disable : 1; 8637 u64 schedule_list : 2; 8638 u64 reserved_27_63 : 37; 8639 } s; 8640 /* struct nixx_af_tl4x_shape_s cn; */ 8641}; 8642 8643static inline u64 NIXX_AF_TL4X_SHAPE(u64 a) 8644 __attribute__ ((pure, always_inline)); 8645static inline u64 NIXX_AF_TL4X_SHAPE(u64 a) 8646{ 8647 return 0x1210 + 0x10000 * a; 8648} 8649 8650/** 8651 * Register (RVU_PF_BAR0) nix#_af_tl4#_shape_state 8652 * 8653 * NIX AF Transmit Level 4 Shaping State Registers This register has the 8654 * same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must not be 8655 * written during normal operation. 8656 */ 8657union nixx_af_tl4x_shape_state { 8658 u64 u; 8659 struct nixx_af_tl4x_shape_state_s { 8660 u64 cir_accum : 26; 8661 u64 pir_accum : 26; 8662 u64 color : 2; 8663 u64 reserved_54_63 : 10; 8664 } s; 8665 /* struct nixx_af_tl4x_shape_state_s cn; */ 8666}; 8667 8668static inline u64 NIXX_AF_TL4X_SHAPE_STATE(u64 a) 8669 __attribute__ ((pure, always_inline)); 8670static inline u64 NIXX_AF_TL4X_SHAPE_STATE(u64 a) 8671{ 8672 return 0x1250 + 0x10000 * a; 8673} 8674 8675/** 8676 * Register (RVU_PF_BAR0) nix#_af_tl4#_sw_xoff 8677 * 8678 * NIX AF Transmit Level 4 Software Controlled XOFF Registers This 8679 * register has the same bit fields as NIX_AF_TL1()_SW_XOFF 8680 */ 8681union nixx_af_tl4x_sw_xoff { 8682 u64 u; 8683 struct nixx_af_tl4x_sw_xoff_s { 8684 u64 xoff : 1; 8685 u64 drain : 1; 8686 u64 reserved_2 : 1; 8687 u64 drain_irq : 1; 8688 u64 reserved_4_63 : 60; 8689 } s; 8690 /* struct nixx_af_tl4x_sw_xoff_s cn; */ 8691}; 8692 8693static inline u64 NIXX_AF_TL4X_SW_XOFF(u64 a) 8694 __attribute__ ((pure, always_inline)); 8695static inline u64 NIXX_AF_TL4X_SW_XOFF(u64 a) 8696{ 8697 return 0x1270 + 0x10000 * a; 8698} 8699 8700/** 8701 * Register (RVU_PF_BAR0) nix#_af_tl4#_topology 8702 * 8703 * NIX AF Transmit Level 4 Topology Registers 8704 */ 8705union nixx_af_tl4x_topology { 8706 u64 u; 8707 struct nixx_af_tl4x_topology_s { 8708 u64 reserved_0 : 1; 8709 u64 rr_prio : 4; 8710 u64 reserved_5_31 : 27; 8711 u64 prio_anchor : 9; 8712 u64 reserved_41_63 : 23; 8713 } s; 8714 /* struct nixx_af_tl4x_topology_s cn; */ 8715}; 8716 8717static inline u64 NIXX_AF_TL4X_TOPOLOGY(u64 a) 8718 __attribute__ ((pure, always_inline)); 8719static inline u64 NIXX_AF_TL4X_TOPOLOGY(u64 a) 8720{ 8721 return 0x1280 + 0x10000 * a; 8722} 8723 8724/** 8725 * Register (RVU_PF_BAR0) nix#_af_tl4#_yellow 8726 * 8727 * INTERNAL: NIX Transmit Level 4 Yellow State Debug Register This 8728 * register has the same bit fields as NIX_AF_TL3()_YELLOW 8729 */ 8730union nixx_af_tl4x_yellow { 8731 u64 u; 8732 struct nixx_af_tl4x_yellow_s { 8733 u64 tail : 9; 8734 u64 reserved_9 : 1; 8735 u64 head : 9; 8736 u64 reserved_19_63 : 45; 8737 } s; 8738 /* struct nixx_af_tl4x_yellow_s cn; */ 8739}; 8740 8741static inline u64 NIXX_AF_TL4X_YELLOW(u64 a) 8742 __attribute__ ((pure, always_inline)); 8743static inline u64 NIXX_AF_TL4X_YELLOW(u64 a) 8744{ 8745 return 0x12a0 + 0x10000 * a; 8746} 8747 8748/** 8749 * Register (RVU_PF_BAR0) nix#_af_tl4_const 8750 * 8751 * NIX AF Transmit Level 4 Constants Register This register contains 8752 * constants for software discovery. 8753 */ 8754union nixx_af_tl4_const { 8755 u64 u; 8756 struct nixx_af_tl4_const_s { 8757 u64 count : 16; 8758 u64 reserved_16_63 : 48; 8759 } s; 8760 /* struct nixx_af_tl4_const_s cn; */ 8761}; 8762 8763static inline u64 NIXX_AF_TL4_CONST(void) 8764 __attribute__ ((pure, always_inline)); 8765static inline u64 NIXX_AF_TL4_CONST(void) 8766{ 8767 return 0x88; 8768} 8769 8770/** 8771 * Register (RVU_PF_BAR0) nix#_af_tx_link#_expr_credit 8772 * 8773 * INTERNAL: NIX AF Transmit Link Express Credit Registers Internal: 8774 * 802.3br frame preemption/express path is defeatured. Old definition: 8775 * These registers track credits per link for express packets that may 8776 * potentially preempt normal packets. Link index enumerated by 8777 * NIX_LINK_E. 8778 */ 8779union nixx_af_tx_linkx_expr_credit { 8780 u64 u; 8781 struct nixx_af_tx_linkx_expr_credit_s { 8782 u64 reserved_0 : 1; 8783 u64 cc_enable : 1; 8784 u64 cc_packet_cnt : 10; 8785 u64 cc_unit_cnt : 20; 8786 u64 reserved_32_63 : 32; 8787 } s; 8788 /* struct nixx_af_tx_linkx_expr_credit_s cn; */ 8789}; 8790 8791static inline u64 NIXX_AF_TX_LINKX_EXPR_CREDIT(u64 a) 8792 __attribute__ ((pure, always_inline)); 8793static inline u64 NIXX_AF_TX_LINKX_EXPR_CREDIT(u64 a) 8794{ 8795 return 0xa10 + 0x10000 * a; 8796} 8797 8798/** 8799 * Register (RVU_PF_BAR0) nix#_af_tx_link#_hw_xoff 8800 * 8801 * NIX AF Transmit Link Hardware Controlled XOFF Registers Link index 8802 * enumerated by NIX_LINK_E. 8803 */ 8804union nixx_af_tx_linkx_hw_xoff { 8805 u64 u; 8806 struct nixx_af_tx_linkx_hw_xoff_s { 8807 u64 chan_xoff : 64; 8808 } s; 8809 /* struct nixx_af_tx_linkx_hw_xoff_s cn; */ 8810}; 8811 8812static inline u64 NIXX_AF_TX_LINKX_HW_XOFF(u64 a) 8813 __attribute__ ((pure, always_inline)); 8814static inline u64 NIXX_AF_TX_LINKX_HW_XOFF(u64 a) 8815{ 8816 return 0xa30 + 0x10000 * a; 8817} 8818 8819/** 8820 * Register (RVU_PF_BAR0) nix#_af_tx_link#_norm_credit 8821 * 8822 * NIX AF Transmit Link Normal Credit Registers These registers track 8823 * credits per link for normal packets sent to CGX and LBK. Link index 8824 * enumerated by NIX_LINK_E. 8825 */ 8826union nixx_af_tx_linkx_norm_credit { 8827 u64 u; 8828 struct nixx_af_tx_linkx_norm_credit_s { 8829 u64 reserved_0 : 1; 8830 u64 cc_enable : 1; 8831 u64 cc_packet_cnt : 10; 8832 u64 cc_unit_cnt : 20; 8833 u64 reserved_32_63 : 32; 8834 } s; 8835 /* struct nixx_af_tx_linkx_norm_credit_s cn; */ 8836}; 8837 8838static inline u64 NIXX_AF_TX_LINKX_NORM_CREDIT(u64 a) 8839 __attribute__ ((pure, always_inline)); 8840static inline u64 NIXX_AF_TX_LINKX_NORM_CREDIT(u64 a) 8841{ 8842 return 0xa00 + 0x10000 * a; 8843} 8844 8845/** 8846 * Register (RVU_PF_BAR0) nix#_af_tx_link#_sw_xoff 8847 * 8848 * INTERNAL: NIX AF Transmit Link Software Controlled XOFF Registers 8849 * Link index enumerated by NIX_LINK_E. Internal: Defeatured registers. 8850 * Software should instead use NIX_AF_TL3()_SW_XOFF registers when 8851 * NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL] is set and NIX_AF_TL2()_SW_XOFF 8852 * registers when NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL] is clear. 8853 */ 8854union nixx_af_tx_linkx_sw_xoff { 8855 u64 u; 8856 struct nixx_af_tx_linkx_sw_xoff_s { 8857 u64 chan_xoff : 64; 8858 } s; 8859 /* struct nixx_af_tx_linkx_sw_xoff_s cn; */ 8860}; 8861 8862static inline u64 NIXX_AF_TX_LINKX_SW_XOFF(u64 a) 8863 __attribute__ ((pure, always_inline)); 8864static inline u64 NIXX_AF_TX_LINKX_SW_XOFF(u64 a) 8865{ 8866 return 0xa20 + 0x10000 * a; 8867} 8868 8869/** 8870 * Register (RVU_PF_BAR0) nix#_af_tx_mcast# 8871 * 8872 * NIX AF Transmit Multicast Registers These registers access transmit 8873 * multicast table entries used to specify multicast replication lists. 8874 * Each list consists of linked entries with [EOL] = 1 in the last entry. 8875 * A transmit packet is multicast when the action returned by NPC has 8876 * NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST. NIX_TX_ACTION_S[INDEX] 8877 * points to the start of the multicast replication list, and [EOL] = 1 8878 * indicates the end of list. 8879 */ 8880union nixx_af_tx_mcastx { 8881 u64 u; 8882 struct nixx_af_tx_mcastx_s { 8883 u64 channel : 12; 8884 u64 eol : 1; 8885 u64 reserved_13_15 : 3; 8886 u64 next : 16; 8887 u64 reserved_32_63 : 32; 8888 } s; 8889 /* struct nixx_af_tx_mcastx_s cn; */ 8890}; 8891 8892static inline u64 NIXX_AF_TX_MCASTX(u64 a) 8893 __attribute__ ((pure, always_inline)); 8894static inline u64 NIXX_AF_TX_MCASTX(u64 a) 8895{ 8896 return 0x1900 + 0x8000 * a; 8897} 8898 8899/** 8900 * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_config 8901 * 8902 * NIX AF Transmit NPC Response Capture Configuration Register Configures 8903 * the NPC response capture logic for transmit packets. When enabled, 8904 * allows NPC responses for selected packets to be captured in 8905 * NIX_AF_TX_NPC_CAPTURE_INFO and NIX_AF_TX_NPC_CAPTURE_RESP(). 8906 */ 8907union nixx_af_tx_npc_capture_config { 8908 u64 u; 8909 struct nixx_af_tx_npc_capture_config_s { 8910 u64 en : 1; 8911 u64 continuous : 1; 8912 u64 lso_segnum_en : 1; 8913 u64 sqe_id_en : 1; 8914 u64 sq_id_en : 1; 8915 u64 lf_id_en : 1; 8916 u64 reserved_6_11 : 6; 8917 u64 lso_segnum : 8; 8918 u64 sqe_id : 16; 8919 u64 sq_id : 20; 8920 u64 lf_id : 8; 8921 } s; 8922 /* struct nixx_af_tx_npc_capture_config_s cn; */ 8923}; 8924 8925static inline u64 NIXX_AF_TX_NPC_CAPTURE_CONFIG(void) 8926 __attribute__ ((pure, always_inline)); 8927static inline u64 NIXX_AF_TX_NPC_CAPTURE_CONFIG(void) 8928{ 8929 return 0x660; 8930} 8931 8932/** 8933 * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_info 8934 * 8935 * NIX AF Transmit NPC Response Capture Information Register This 8936 * register contains captured NPC response information for a transmit 8937 * packet. See NIX_AF_TX_NPC_CAPTURE_CONFIG. 8938 */ 8939union nixx_af_tx_npc_capture_info { 8940 u64 u; 8941 struct nixx_af_tx_npc_capture_info_s { 8942 u64 vld : 1; 8943 u64 reserved_1_11 : 11; 8944 u64 lso_segnum : 8; 8945 u64 sqe_id : 16; 8946 u64 sq_id : 20; 8947 u64 lf_id : 8; 8948 } s; 8949 /* struct nixx_af_tx_npc_capture_info_s cn; */ 8950}; 8951 8952static inline u64 NIXX_AF_TX_NPC_CAPTURE_INFO(void) 8953 __attribute__ ((pure, always_inline)); 8954static inline u64 NIXX_AF_TX_NPC_CAPTURE_INFO(void) 8955{ 8956 return 0x668; 8957} 8958 8959/** 8960 * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_resp# 8961 * 8962 * NIX AF Transmit NPC Capture Response Registers These registers contain 8963 * the captured NPC response for a transmit packet when 8964 * NIX_AF_TX_NPC_CAPTURE_INFO[VLD] is set. See also 8965 * NIX_AF_TX_NPC_CAPTURE_CONFIG. 8966 */ 8967union nixx_af_tx_npc_capture_respx { 8968 u64 u; 8969 struct nixx_af_tx_npc_capture_respx_s { 8970 u64 data : 64; 8971 } s; 8972 /* struct nixx_af_tx_npc_capture_respx_s cn; */ 8973}; 8974 8975static inline u64 NIXX_AF_TX_NPC_CAPTURE_RESPX(u64 a) 8976 __attribute__ ((pure, always_inline)); 8977static inline u64 NIXX_AF_TX_NPC_CAPTURE_RESPX(u64 a) 8978{ 8979 return 0x680 + 8 * a; 8980} 8981 8982/** 8983 * Register (RVU_PF_BAR0) nix#_af_tx_tstmp_cfg 8984 * 8985 * NIX AF Transmit Timestamp Configuration Register 8986 */ 8987union nixx_af_tx_tstmp_cfg { 8988 u64 u; 8989 struct nixx_af_tx_tstmp_cfg_s { 8990 u64 tstmp_wd_period : 4; 8991 u64 reserved_4_7 : 4; 8992 u64 express : 16; 8993 u64 reserved_24_63 : 40; 8994 } s; 8995 /* struct nixx_af_tx_tstmp_cfg_s cn; */ 8996}; 8997 8998static inline u64 NIXX_AF_TX_TSTMP_CFG(void) 8999 __attribute__ ((pure, always_inline)); 9000static inline u64 NIXX_AF_TX_TSTMP_CFG(void) 9001{ 9002 return 0xc0; 9003} 9004 9005/** 9006 * Register (RVU_PF_BAR0) nix#_af_tx_vtag_def#_ctl 9007 * 9008 * NIX AF Transmit Vtag Definition Control Registers The transmit Vtag 9009 * definition table specifies Vtag layers (e.g. VLAN, E-TAG) to 9010 * optionally insert or replace in the TX packet header. Indexed by 9011 * NIX_TX_VTAG_ACTION_S[VTAG*_DEF]. 9012 */ 9013union nixx_af_tx_vtag_defx_ctl { 9014 u64 u; 9015 struct nixx_af_tx_vtag_defx_ctl_s { 9016 u64 size : 1; 9017 u64 reserved_1_63 : 63; 9018 } s; 9019 /* struct nixx_af_tx_vtag_defx_ctl_s cn; */ 9020}; 9021 9022static inline u64 NIXX_AF_TX_VTAG_DEFX_CTL(u64 a) 9023 __attribute__ ((pure, always_inline)); 9024static inline u64 NIXX_AF_TX_VTAG_DEFX_CTL(u64 a) 9025{ 9026 return 0x1a00 + 0x10000 * a; 9027} 9028 9029/** 9030 * Register (RVU_PF_BAR0) nix#_af_tx_vtag_def#_data 9031 * 9032 * NIX AF Transmit Vtag Definition Data Registers See 9033 * NIX_AF_TX_VTAG_DEF()_CTL. 9034 */ 9035union nixx_af_tx_vtag_defx_data { 9036 u64 u; 9037 struct nixx_af_tx_vtag_defx_data_s { 9038 u64 data : 64; 9039 } s; 9040 /* struct nixx_af_tx_vtag_defx_data_s cn; */ 9041}; 9042 9043static inline u64 NIXX_AF_TX_VTAG_DEFX_DATA(u64 a) 9044 __attribute__ ((pure, always_inline)); 9045static inline u64 NIXX_AF_TX_VTAG_DEFX_DATA(u64 a) 9046{ 9047 return 0x1a10 + 0x10000 * a; 9048} 9049 9050/** 9051 * Register (RVU_PFVF_BAR2) nix#_lf_cfg 9052 * 9053 * NIX LF Configuration Register 9054 */ 9055union nixx_lf_cfg { 9056 u64 u; 9057 struct nixx_lf_cfg_s { 9058 u64 tcp_timer_int_ena : 1; 9059 u64 reserved_1_63 : 63; 9060 } s; 9061 /* struct nixx_lf_cfg_s cn; */ 9062}; 9063 9064static inline u64 NIXX_LF_CFG(void) 9065 __attribute__ ((pure, always_inline)); 9066static inline u64 NIXX_LF_CFG(void) 9067{ 9068 return 0x100; 9069} 9070 9071/** 9072 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_cnt 9073 * 9074 * NIX LF Completion Interrupt Count Registers 9075 */ 9076union nixx_lf_cintx_cnt { 9077 u64 u; 9078 struct nixx_lf_cintx_cnt_s { 9079 u64 ecount : 32; 9080 u64 qcount : 16; 9081 u64 reserved_48_63 : 16; 9082 } s; 9083 /* struct nixx_lf_cintx_cnt_s cn; */ 9084}; 9085 9086static inline u64 NIXX_LF_CINTX_CNT(u64 a) 9087 __attribute__ ((pure, always_inline)); 9088static inline u64 NIXX_LF_CINTX_CNT(u64 a) 9089{ 9090 return 0xd00 + 0x1000 * a; 9091} 9092 9093/** 9094 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_ena_w1c 9095 * 9096 * NIX LF Completion Interrupt Enable Clear Registers This register 9097 * clears interrupt enable bits. 9098 */ 9099union nixx_lf_cintx_ena_w1c { 9100 u64 u; 9101 struct nixx_lf_cintx_ena_w1c_s { 9102 u64 intr : 1; 9103 u64 reserved_1_63 : 63; 9104 } s; 9105 /* struct nixx_lf_cintx_ena_w1c_s cn; */ 9106}; 9107 9108static inline u64 NIXX_LF_CINTX_ENA_W1C(u64 a) 9109 __attribute__ ((pure, always_inline)); 9110static inline u64 NIXX_LF_CINTX_ENA_W1C(u64 a) 9111{ 9112 return 0xd50 + 0x1000 * a; 9113} 9114 9115/** 9116 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_ena_w1s 9117 * 9118 * NIX LF Completion Interrupt Enable Set Registers This register sets 9119 * interrupt enable bits. 9120 */ 9121union nixx_lf_cintx_ena_w1s { 9122 u64 u; 9123 struct nixx_lf_cintx_ena_w1s_s { 9124 u64 intr : 1; 9125 u64 reserved_1_63 : 63; 9126 } s; 9127 /* struct nixx_lf_cintx_ena_w1s_s cn; */ 9128}; 9129 9130static inline u64 NIXX_LF_CINTX_ENA_W1S(u64 a) 9131 __attribute__ ((pure, always_inline)); 9132static inline u64 NIXX_LF_CINTX_ENA_W1S(u64 a) 9133{ 9134 return 0xd40 + 0x1000 * a; 9135} 9136 9137/** 9138 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_int 9139 * 9140 * NIX LF Completion Interrupt Registers 9141 */ 9142union nixx_lf_cintx_int { 9143 u64 u; 9144 struct nixx_lf_cintx_int_s { 9145 u64 intr : 1; 9146 u64 reserved_1_63 : 63; 9147 } s; 9148 /* struct nixx_lf_cintx_int_s cn; */ 9149}; 9150 9151static inline u64 NIXX_LF_CINTX_INT(u64 a) 9152 __attribute__ ((pure, always_inline)); 9153static inline u64 NIXX_LF_CINTX_INT(u64 a) 9154{ 9155 return 0xd20 + 0x1000 * a; 9156} 9157 9158/** 9159 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_int_w1s 9160 * 9161 * NIX LF Completion Interrupt Set Registers This register sets interrupt 9162 * bits. 9163 */ 9164union nixx_lf_cintx_int_w1s { 9165 u64 u; 9166 struct nixx_lf_cintx_int_w1s_s { 9167 u64 intr : 1; 9168 u64 reserved_1_63 : 63; 9169 } s; 9170 /* struct nixx_lf_cintx_int_w1s_s cn; */ 9171}; 9172 9173static inline u64 NIXX_LF_CINTX_INT_W1S(u64 a) 9174 __attribute__ ((pure, always_inline)); 9175static inline u64 NIXX_LF_CINTX_INT_W1S(u64 a) 9176{ 9177 return 0xd30 + 0x1000 * a; 9178} 9179 9180/** 9181 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_wait 9182 * 9183 * NIX LF Completion Interrupt Count Registers 9184 */ 9185union nixx_lf_cintx_wait { 9186 u64 u; 9187 struct nixx_lf_cintx_wait_s { 9188 u64 ecount_wait : 32; 9189 u64 qcount_wait : 16; 9190 u64 time_wait : 8; 9191 u64 reserved_56_63 : 8; 9192 } s; 9193 /* struct nixx_lf_cintx_wait_s cn; */ 9194}; 9195 9196static inline u64 NIXX_LF_CINTX_WAIT(u64 a) 9197 __attribute__ ((pure, always_inline)); 9198static inline u64 NIXX_LF_CINTX_WAIT(u64 a) 9199{ 9200 return 0xd10 + 0x1000 * a; 9201} 9202 9203/** 9204 * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_door 9205 * 9206 * NIX LF CQ Doorbell Operation Register A write to this register 9207 * dequeues CQEs from a CQ ring within the LF. A read is RAZ. RSL 9208 * accesses to this register are RAZ/WI. 9209 */ 9210union nixx_lf_cq_op_door { 9211 u64 u; 9212 struct nixx_lf_cq_op_door_s { 9213 u64 count : 16; 9214 u64 reserved_16_31 : 16; 9215 u64 cq : 20; 9216 u64 reserved_52_63 : 12; 9217 } s; 9218 /* struct nixx_lf_cq_op_door_s cn; */ 9219}; 9220 9221static inline u64 NIXX_LF_CQ_OP_DOOR(void) 9222 __attribute__ ((pure, always_inline)); 9223static inline u64 NIXX_LF_CQ_OP_DOOR(void) 9224{ 9225 return 0xb30; 9226} 9227 9228/** 9229 * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_int 9230 * 9231 * NIX LF Completion Queue Interrupt Operation Register A 64-bit atomic 9232 * load-and-add to this register reads CQ interrupts and interrupt 9233 * enables. A write optionally sets or clears interrupts and interrupt 9234 * enables. A read is RAZ. RSL accesses to this register are RAZ/WI. 9235 */ 9236union nixx_lf_cq_op_int { 9237 u64 u; 9238 struct nixx_lf_cq_op_int_s { 9239 u64 cq_err_int : 8; 9240 u64 cq_err_int_ena : 8; 9241 u64 reserved_16_41 : 26; 9242 u64 op_err : 1; 9243 u64 setop : 1; 9244 u64 cq : 20; 9245 } s; 9246 /* struct nixx_lf_cq_op_int_s cn; */ 9247}; 9248 9249static inline u64 NIXX_LF_CQ_OP_INT(void) 9250 __attribute__ ((pure, always_inline)); 9251static inline u64 NIXX_LF_CQ_OP_INT(void) 9252{ 9253 return 0xb00; 9254} 9255 9256/** 9257 * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_status 9258 * 9259 * NIX LF Completion Queue Status Operation Register A 64-bit atomic 9260 * load-and-add to this register reads NIX_CQ_CTX_S[HEAD,TAIL]. The 9261 * atomic write data has format NIX_OP_Q_WDATA_S and selects the CQ 9262 * within LF. All other accesses to this register (e.g. reads and 9263 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. 9264 */ 9265union nixx_lf_cq_op_status { 9266 u64 u; 9267 struct nixx_lf_cq_op_status_s { 9268 u64 tail : 20; 9269 u64 head : 20; 9270 u64 reserved_40_45 : 6; 9271 u64 cq_err : 1; 9272 u64 reserved_47_62 : 16; 9273 u64 op_err : 1; 9274 } s; 9275 /* struct nixx_lf_cq_op_status_s cn; */ 9276}; 9277 9278static inline u64 NIXX_LF_CQ_OP_STATUS(void) 9279 __attribute__ ((pure, always_inline)); 9280static inline u64 NIXX_LF_CQ_OP_STATUS(void) 9281{ 9282 return 0xb40; 9283} 9284 9285/** 9286 * Register (RVU_PFVF_BAR2) nix#_lf_err_int 9287 * 9288 * NIX LF Error Interrupt Register 9289 */ 9290union nixx_lf_err_int { 9291 u64 u; 9292 struct nixx_lf_err_int_s { 9293 u64 sqb_fault : 1; 9294 u64 sq_ctx_fault : 1; 9295 u64 rq_ctx_fault : 1; 9296 u64 cq_ctx_fault : 1; 9297 u64 reserved_4 : 1; 9298 u64 rsse_fault : 1; 9299 u64 ipsec_dyno_fault : 1; 9300 u64 sq_disabled : 1; 9301 u64 sq_oor : 1; 9302 u64 send_jump_fault : 1; 9303 u64 send_sg_fault : 1; 9304 u64 rq_disabled : 1; 9305 u64 rq_oor : 1; 9306 u64 rx_wqe_fault : 1; 9307 u64 rss_err : 1; 9308 u64 reserved_15_19 : 5; 9309 u64 dyno_err : 1; 9310 u64 reserved_21_23 : 3; 9311 u64 cq_disabled : 1; 9312 u64 cq_oor : 1; 9313 u64 reserved_26_27 : 2; 9314 u64 qint_fault : 1; 9315 u64 cint_fault : 1; 9316 u64 reserved_30_63 : 34; 9317 } s; 9318 /* struct nixx_lf_err_int_s cn; */ 9319}; 9320 9321static inline u64 NIXX_LF_ERR_INT(void) 9322 __attribute__ ((pure, always_inline)); 9323static inline u64 NIXX_LF_ERR_INT(void) 9324{ 9325 return 0x220; 9326} 9327 9328/** 9329 * Register (RVU_PFVF_BAR2) nix#_lf_err_int_ena_w1c 9330 * 9331 * NIX LF Error Interrupt Enable Clear Register This register clears 9332 * interrupt enable bits. 9333 */ 9334union nixx_lf_err_int_ena_w1c { 9335 u64 u; 9336 struct nixx_lf_err_int_ena_w1c_s { 9337 u64 sqb_fault : 1; 9338 u64 sq_ctx_fault : 1; 9339 u64 rq_ctx_fault : 1; 9340 u64 cq_ctx_fault : 1; 9341 u64 reserved_4 : 1; 9342 u64 rsse_fault : 1; 9343 u64 ipsec_dyno_fault : 1; 9344 u64 sq_disabled : 1; 9345 u64 sq_oor : 1; 9346 u64 send_jump_fault : 1; 9347 u64 send_sg_fault : 1; 9348 u64 rq_disabled : 1; 9349 u64 rq_oor : 1; 9350 u64 rx_wqe_fault : 1; 9351 u64 rss_err : 1; 9352 u64 reserved_15_19 : 5; 9353 u64 dyno_err : 1; 9354 u64 reserved_21_23 : 3; 9355 u64 cq_disabled : 1; 9356 u64 cq_oor : 1; 9357 u64 reserved_26_27 : 2; 9358 u64 qint_fault : 1; 9359 u64 cint_fault : 1; 9360 u64 reserved_30_63 : 34; 9361 } s; 9362 /* struct nixx_lf_err_int_ena_w1c_s cn; */ 9363}; 9364 9365static inline u64 NIXX_LF_ERR_INT_ENA_W1C(void) 9366 __attribute__ ((pure, always_inline)); 9367static inline u64 NIXX_LF_ERR_INT_ENA_W1C(void) 9368{ 9369 return 0x230; 9370} 9371 9372/** 9373 * Register (RVU_PFVF_BAR2) nix#_lf_err_int_ena_w1s 9374 * 9375 * NIX LF Error Interrupt Enable Set Register This register sets 9376 * interrupt enable bits. 9377 */ 9378union nixx_lf_err_int_ena_w1s { 9379 u64 u; 9380 struct nixx_lf_err_int_ena_w1s_s { 9381 u64 sqb_fault : 1; 9382 u64 sq_ctx_fault : 1; 9383 u64 rq_ctx_fault : 1; 9384 u64 cq_ctx_fault : 1; 9385 u64 reserved_4 : 1; 9386 u64 rsse_fault : 1; 9387 u64 ipsec_dyno_fault : 1; 9388 u64 sq_disabled : 1; 9389 u64 sq_oor : 1; 9390 u64 send_jump_fault : 1; 9391 u64 send_sg_fault : 1; 9392 u64 rq_disabled : 1; 9393 u64 rq_oor : 1; 9394 u64 rx_wqe_fault : 1; 9395 u64 rss_err : 1; 9396 u64 reserved_15_19 : 5; 9397 u64 dyno_err : 1; 9398 u64 reserved_21_23 : 3; 9399 u64 cq_disabled : 1; 9400 u64 cq_oor : 1; 9401 u64 reserved_26_27 : 2; 9402 u64 qint_fault : 1; 9403 u64 cint_fault : 1; 9404 u64 reserved_30_63 : 34; 9405 } s; 9406 /* struct nixx_lf_err_int_ena_w1s_s cn; */ 9407}; 9408 9409static inline u64 NIXX_LF_ERR_INT_ENA_W1S(void) 9410 __attribute__ ((pure, always_inline)); 9411static inline u64 NIXX_LF_ERR_INT_ENA_W1S(void) 9412{ 9413 return 0x238; 9414} 9415 9416/** 9417 * Register (RVU_PFVF_BAR2) nix#_lf_err_int_w1s 9418 * 9419 * NIX LF Error Interrupt Set Register This register sets interrupt bits. 9420 */ 9421union nixx_lf_err_int_w1s { 9422 u64 u; 9423 struct nixx_lf_err_int_w1s_s { 9424 u64 sqb_fault : 1; 9425 u64 sq_ctx_fault : 1; 9426 u64 rq_ctx_fault : 1; 9427 u64 cq_ctx_fault : 1; 9428 u64 reserved_4 : 1; 9429 u64 rsse_fault : 1; 9430 u64 ipsec_dyno_fault : 1; 9431 u64 sq_disabled : 1; 9432 u64 sq_oor : 1; 9433 u64 send_jump_fault : 1; 9434 u64 send_sg_fault : 1; 9435 u64 rq_disabled : 1; 9436 u64 rq_oor : 1; 9437 u64 rx_wqe_fault : 1; 9438 u64 rss_err : 1; 9439 u64 reserved_15_19 : 5; 9440 u64 dyno_err : 1; 9441 u64 reserved_21_23 : 3; 9442 u64 cq_disabled : 1; 9443 u64 cq_oor : 1; 9444 u64 reserved_26_27 : 2; 9445 u64 qint_fault : 1; 9446 u64 cint_fault : 1; 9447 u64 reserved_30_63 : 34; 9448 } s; 9449 /* struct nixx_lf_err_int_w1s_s cn; */ 9450}; 9451 9452static inline u64 NIXX_LF_ERR_INT_W1S(void) 9453 __attribute__ ((pure, always_inline)); 9454static inline u64 NIXX_LF_ERR_INT_W1S(void) 9455{ 9456 return 0x228; 9457} 9458 9459/** 9460 * Register (RVU_PFVF_BAR2) nix#_lf_gint 9461 * 9462 * NIX LF General Interrupt Register 9463 */ 9464union nixx_lf_gint { 9465 u64 u; 9466 struct nixx_lf_gint_s { 9467 u64 drop : 1; 9468 u64 tcp_timer : 1; 9469 u64 reserved_2_63 : 62; 9470 } s; 9471 /* struct nixx_lf_gint_s cn; */ 9472}; 9473 9474static inline u64 NIXX_LF_GINT(void) 9475 __attribute__ ((pure, always_inline)); 9476static inline u64 NIXX_LF_GINT(void) 9477{ 9478 return 0x200; 9479} 9480 9481/** 9482 * Register (RVU_PFVF_BAR2) nix#_lf_gint_ena_w1c 9483 * 9484 * NIX LF General Interrupt Enable Clear Register This register clears 9485 * interrupt enable bits. 9486 */ 9487union nixx_lf_gint_ena_w1c { 9488 u64 u; 9489 struct nixx_lf_gint_ena_w1c_s { 9490 u64 drop : 1; 9491 u64 tcp_timer : 1; 9492 u64 reserved_2_63 : 62; 9493 } s; 9494 /* struct nixx_lf_gint_ena_w1c_s cn; */ 9495}; 9496 9497static inline u64 NIXX_LF_GINT_ENA_W1C(void) 9498 __attribute__ ((pure, always_inline)); 9499static inline u64 NIXX_LF_GINT_ENA_W1C(void) 9500{ 9501 return 0x210; 9502} 9503 9504/** 9505 * Register (RVU_PFVF_BAR2) nix#_lf_gint_ena_w1s 9506 * 9507 * NIX LF General Interrupt Enable Set Register This register sets 9508 * interrupt enable bits. 9509 */ 9510union nixx_lf_gint_ena_w1s { 9511 u64 u; 9512 struct nixx_lf_gint_ena_w1s_s { 9513 u64 drop : 1; 9514 u64 tcp_timer : 1; 9515 u64 reserved_2_63 : 62; 9516 } s; 9517 /* struct nixx_lf_gint_ena_w1s_s cn; */ 9518}; 9519 9520static inline u64 NIXX_LF_GINT_ENA_W1S(void) 9521 __attribute__ ((pure, always_inline)); 9522static inline u64 NIXX_LF_GINT_ENA_W1S(void) 9523{ 9524 return 0x218; 9525} 9526 9527/** 9528 * Register (RVU_PFVF_BAR2) nix#_lf_gint_w1s 9529 * 9530 * NIX LF General Interrupt Set Register This register sets interrupt 9531 * bits. 9532 */ 9533union nixx_lf_gint_w1s { 9534 u64 u; 9535 struct nixx_lf_gint_w1s_s { 9536 u64 drop : 1; 9537 u64 tcp_timer : 1; 9538 u64 reserved_2_63 : 62; 9539 } s; 9540 /* struct nixx_lf_gint_w1s_s cn; */ 9541}; 9542 9543static inline u64 NIXX_LF_GINT_W1S(void) 9544 __attribute__ ((pure, always_inline)); 9545static inline u64 NIXX_LF_GINT_W1S(void) 9546{ 9547 return 0x208; 9548} 9549 9550/** 9551 * Register (RVU_PFVF_BAR2) nix#_lf_mnq_err_dbg 9552 * 9553 * NIX LF Meta-descriptor Enqueue Error Debug Register This register 9554 * captures debug info for an error detected during send meta-descriptor 9555 * enqueue from an SQ to an SMQ. Hardware sets [VALID] when the debug 9556 * info is captured, and subsequent errors are not captured until 9557 * software clears [VALID] by writing a one to it. 9558 */ 9559union nixx_lf_mnq_err_dbg { 9560 u64 u; 9561 struct nixx_lf_mnq_err_dbg_s { 9562 u64 errcode : 8; 9563 u64 sq : 20; 9564 u64 sqe_id : 16; 9565 u64 valid : 1; 9566 u64 reserved_45_63 : 19; 9567 } s; 9568 /* struct nixx_lf_mnq_err_dbg_s cn; */ 9569}; 9570 9571static inline u64 NIXX_LF_MNQ_ERR_DBG(void) 9572 __attribute__ ((pure, always_inline)); 9573static inline u64 NIXX_LF_MNQ_ERR_DBG(void) 9574{ 9575 return 0x270; 9576} 9577 9578/** 9579 * Register (RVU_PFVF_BAR2) nix#_lf_op_ipsec_dyno_cnt 9580 * 9581 * INTERNAL: NIX LF IPSEC Dynamic Ordering Counter Operation Register 9582 * Internal: Not used; no IPSEC fast-path. All accesses are RAZ/WI. 9583 */ 9584union nixx_lf_op_ipsec_dyno_cnt { 9585 u64 u; 9586 struct nixx_lf_op_ipsec_dyno_cnt_s { 9587 u64 count : 32; 9588 u64 reserved_32_46 : 15; 9589 u64 storeop : 1; 9590 u64 dyno_sel : 15; 9591 u64 op_err : 1; 9592 } s; 9593 /* struct nixx_lf_op_ipsec_dyno_cnt_s cn; */ 9594}; 9595 9596static inline u64 NIXX_LF_OP_IPSEC_DYNO_CNT(void) 9597 __attribute__ ((pure, always_inline)); 9598static inline u64 NIXX_LF_OP_IPSEC_DYNO_CNT(void) 9599{ 9600 return 0x980; 9601} 9602 9603/** 9604 * Register (RVU_PFVF_BAR2) nix#_lf_op_send# 9605 * 9606 * NIX LF Send Operation Registers An LMTST (or large store from CPT) to 9607 * this address enqueues one or more SQEs to a send queue. 9608 * NIX_SEND_HDR_S[SQ] in the first SQE selects the send queue.The maximum 9609 * size of each SQE is specified by NIX_SQ_CTX_S[MAX_SQE_SIZE]. A read 9610 * to this address is RAZ. An RSL access to this address will fault. 9611 * The endianness of the instruction write data is controlled by 9612 * NIX_AF_LF()_CFG[BE]. When a NIX_SEND_JUMP_S is not present in the 9613 * SQE, the SQE consists of the entire send descriptor. When a 9614 * NIX_SEND_JUMP_S is present in the SQE, the SQE must contain exactly 9615 * the portion of the send descriptor up to and including the 9616 * NIX_SEND_JUMP_S, and the remainder of the send descriptor must be at 9617 * LF IOVA NIX_SEND_JUMP_S[ADDR] in LLC/DRAM. Software must ensure that 9618 * all LLC/DRAM locations that will be referenced by NIX while processing 9619 * this descriptor, including all packet data and post-jump 9620 * subdescriptors contain the latest updates before issuing the LMTST. A 9621 * DMB instruction may be required prior to the LMTST to ensure this. A 9622 * DMB following the LMTST may be useful if SQ descriptor ordering 9623 * matters and more than one CPU core is simultaneously enqueueing to the 9624 * same SQ. 9625 */ 9626union nixx_lf_op_sendx { 9627 u64 u; 9628 struct nixx_lf_op_sendx_s { 9629 u64 data : 64; 9630 } s; 9631 /* struct nixx_lf_op_sendx_s cn; */ 9632}; 9633 9634static inline u64 NIXX_LF_OP_SENDX(u64 a) 9635 __attribute__ ((pure, always_inline)); 9636static inline u64 NIXX_LF_OP_SENDX(u64 a) 9637{ 9638 return 0x800 + 8 * a; 9639} 9640 9641/** 9642 * Register (RVU_PFVF_BAR2) nix#_lf_qint#_cnt 9643 * 9644 * NIX LF Queue Interrupt Count Registers 9645 */ 9646union nixx_lf_qintx_cnt { 9647 u64 u; 9648 struct nixx_lf_qintx_cnt_s { 9649 u64 count : 22; 9650 u64 reserved_22_63 : 42; 9651 } s; 9652 /* struct nixx_lf_qintx_cnt_s cn; */ 9653}; 9654 9655static inline u64 NIXX_LF_QINTX_CNT(u64 a) 9656 __attribute__ ((pure, always_inline)); 9657static inline u64 NIXX_LF_QINTX_CNT(u64 a) 9658{ 9659 return 0xc00 + 0x1000 * a; 9660} 9661 9662/** 9663 * Register (RVU_PFVF_BAR2) nix#_lf_qint#_ena_w1c 9664 * 9665 * NIX LF Queue Interrupt Enable Clear Registers This register clears 9666 * interrupt enable bits. 9667 */ 9668union nixx_lf_qintx_ena_w1c { 9669 u64 u; 9670 struct nixx_lf_qintx_ena_w1c_s { 9671 u64 intr : 1; 9672 u64 reserved_1_63 : 63; 9673 } s; 9674 /* struct nixx_lf_qintx_ena_w1c_s cn; */ 9675}; 9676 9677static inline u64 NIXX_LF_QINTX_ENA_W1C(u64 a) 9678 __attribute__ ((pure, always_inline)); 9679static inline u64 NIXX_LF_QINTX_ENA_W1C(u64 a) 9680{ 9681 return 0xc30 + 0x1000 * a; 9682} 9683 9684/** 9685 * Register (RVU_PFVF_BAR2) nix#_lf_qint#_ena_w1s 9686 * 9687 * NIX LF Queue Interrupt Enable Set Registers This register sets 9688 * interrupt enable bits. 9689 */ 9690union nixx_lf_qintx_ena_w1s { 9691 u64 u; 9692 struct nixx_lf_qintx_ena_w1s_s { 9693 u64 intr : 1; 9694 u64 reserved_1_63 : 63; 9695 } s; 9696 /* struct nixx_lf_qintx_ena_w1s_s cn; */ 9697}; 9698 9699static inline u64 NIXX_LF_QINTX_ENA_W1S(u64 a) 9700 __attribute__ ((pure, always_inline)); 9701static inline u64 NIXX_LF_QINTX_ENA_W1S(u64 a) 9702{ 9703 return 0xc20 + 0x1000 * a; 9704} 9705 9706/** 9707 * Register (RVU_PFVF_BAR2) nix#_lf_qint#_int 9708 * 9709 * NIX LF Queue Interrupt Registers 9710 */ 9711union nixx_lf_qintx_int { 9712 u64 u; 9713 struct nixx_lf_qintx_int_s { 9714 u64 intr : 1; 9715 u64 reserved_1_63 : 63; 9716 } s; 9717 /* struct nixx_lf_qintx_int_s cn; */ 9718}; 9719 9720static inline u64 NIXX_LF_QINTX_INT(u64 a) 9721 __attribute__ ((pure, always_inline)); 9722static inline u64 NIXX_LF_QINTX_INT(u64 a) 9723{ 9724 return 0xc10 + 0x1000 * a; 9725} 9726 9727/** 9728 * Register (RVU_PFVF_BAR2) nix#_lf_qint#_int_w1s 9729 * 9730 * INTERNAL: NIX LF Queue Interrupt Set Registers 9731 */ 9732union nixx_lf_qintx_int_w1s { 9733 u64 u; 9734 struct nixx_lf_qintx_int_w1s_s { 9735 u64 intr : 1; 9736 u64 reserved_1_63 : 63; 9737 } s; 9738 /* struct nixx_lf_qintx_int_w1s_s cn; */ 9739}; 9740 9741static inline u64 NIXX_LF_QINTX_INT_W1S(u64 a) 9742 __attribute__ ((pure, always_inline)); 9743static inline u64 NIXX_LF_QINTX_INT_W1S(u64 a) 9744{ 9745 return 0xc18 + 0x1000 * a; 9746} 9747 9748/** 9749 * Register (RVU_PFVF_BAR2) nix#_lf_ras 9750 * 9751 * NIX LF RAS Interrupt Register 9752 */ 9753union nixx_lf_ras { 9754 u64 u; 9755 struct nixx_lf_ras_s { 9756 u64 sqb_poison : 1; 9757 u64 sq_ctx_poison : 1; 9758 u64 rq_ctx_poison : 1; 9759 u64 cq_ctx_poison : 1; 9760 u64 reserved_4 : 1; 9761 u64 rsse_poison : 1; 9762 u64 ipsec_dyno_poison : 1; 9763 u64 send_jump_poison : 1; 9764 u64 send_sg_poison : 1; 9765 u64 qint_poison : 1; 9766 u64 cint_poison : 1; 9767 u64 reserved_11_63 : 53; 9768 } s; 9769 /* struct nixx_lf_ras_s cn; */ 9770}; 9771 9772static inline u64 NIXX_LF_RAS(void) 9773 __attribute__ ((pure, always_inline)); 9774static inline u64 NIXX_LF_RAS(void) 9775{ 9776 return 0x240; 9777} 9778 9779/** 9780 * Register (RVU_PFVF_BAR2) nix#_lf_ras_ena_w1c 9781 * 9782 * NIX LF RAS Interrupt Enable Clear Register This register clears 9783 * interrupt enable bits. 9784 */ 9785union nixx_lf_ras_ena_w1c { 9786 u64 u; 9787 struct nixx_lf_ras_ena_w1c_s { 9788 u64 sqb_poison : 1; 9789 u64 sq_ctx_poison : 1; 9790 u64 rq_ctx_poison : 1; 9791 u64 cq_ctx_poison : 1; 9792 u64 reserved_4 : 1; 9793 u64 rsse_poison : 1; 9794 u64 ipsec_dyno_poison : 1; 9795 u64 send_jump_poison : 1; 9796 u64 send_sg_poison : 1; 9797 u64 qint_poison : 1; 9798 u64 cint_poison : 1; 9799 u64 reserved_11_63 : 53; 9800 } s; 9801 /* struct nixx_lf_ras_ena_w1c_s cn; */ 9802}; 9803 9804static inline u64 NIXX_LF_RAS_ENA_W1C(void) 9805 __attribute__ ((pure, always_inline)); 9806static inline u64 NIXX_LF_RAS_ENA_W1C(void) 9807{ 9808 return 0x250; 9809} 9810 9811/** 9812 * Register (RVU_PFVF_BAR2) nix#_lf_ras_ena_w1s 9813 * 9814 * NIX LF RAS Interrupt Enable Set Register This register sets interrupt 9815 * enable bits. 9816 */ 9817union nixx_lf_ras_ena_w1s { 9818 u64 u; 9819 struct nixx_lf_ras_ena_w1s_s { 9820 u64 sqb_poison : 1; 9821 u64 sq_ctx_poison : 1; 9822 u64 rq_ctx_poison : 1; 9823 u64 cq_ctx_poison : 1; 9824 u64 reserved_4 : 1; 9825 u64 rsse_poison : 1; 9826 u64 ipsec_dyno_poison : 1; 9827 u64 send_jump_poison : 1; 9828 u64 send_sg_poison : 1; 9829 u64 qint_poison : 1; 9830 u64 cint_poison : 1; 9831 u64 reserved_11_63 : 53; 9832 } s; 9833 /* struct nixx_lf_ras_ena_w1s_s cn; */ 9834}; 9835 9836static inline u64 NIXX_LF_RAS_ENA_W1S(void) 9837 __attribute__ ((pure, always_inline)); 9838static inline u64 NIXX_LF_RAS_ENA_W1S(void) 9839{ 9840 return 0x258; 9841} 9842 9843/** 9844 * Register (RVU_PFVF_BAR2) nix#_lf_ras_w1s 9845 * 9846 * NIX LF RAS Interrupt Set Register This register sets interrupt bits. 9847 */ 9848union nixx_lf_ras_w1s { 9849 u64 u; 9850 struct nixx_lf_ras_w1s_s { 9851 u64 sqb_poison : 1; 9852 u64 sq_ctx_poison : 1; 9853 u64 rq_ctx_poison : 1; 9854 u64 cq_ctx_poison : 1; 9855 u64 reserved_4 : 1; 9856 u64 rsse_poison : 1; 9857 u64 ipsec_dyno_poison : 1; 9858 u64 send_jump_poison : 1; 9859 u64 send_sg_poison : 1; 9860 u64 qint_poison : 1; 9861 u64 cint_poison : 1; 9862 u64 reserved_11_63 : 53; 9863 } s; 9864 /* struct nixx_lf_ras_w1s_s cn; */ 9865}; 9866 9867static inline u64 NIXX_LF_RAS_W1S(void) 9868 __attribute__ ((pure, always_inline)); 9869static inline u64 NIXX_LF_RAS_W1S(void) 9870{ 9871 return 0x248; 9872} 9873 9874/** 9875 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_drop_octs 9876 * 9877 * NIX LF Receive Queue Dropped Octets Operation Register A 64-bit atomic 9878 * load-and-add to this register reads NIX_RQ_CTX_S[DROP_OCTS]. The 9879 * atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ 9880 * within LF. All other accesses to this register (e.g. reads and 9881 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. 9882 */ 9883union nixx_lf_rq_op_drop_octs { 9884 u64 u; 9885 struct nixx_lf_rq_op_drop_octs_s { 9886 u64 cnt : 48; 9887 u64 reserved_48_62 : 15; 9888 u64 op_err : 1; 9889 } s; 9890 /* struct nixx_lf_rq_op_drop_octs_s cn; */ 9891}; 9892 9893static inline u64 NIXX_LF_RQ_OP_DROP_OCTS(void) 9894 __attribute__ ((pure, always_inline)); 9895static inline u64 NIXX_LF_RQ_OP_DROP_OCTS(void) 9896{ 9897 return 0x930; 9898} 9899 9900/** 9901 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_drop_pkts 9902 * 9903 * NIX LF Receive Queue Dropped Packets Operation Register A 64-bit 9904 * atomic load-and-add to this register reads NIX_RQ_CTX_S[DROP_PKTS]. 9905 * The atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ 9906 * within LF. All other accesses to this register (e.g. reads and 9907 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. 9908 */ 9909union nixx_lf_rq_op_drop_pkts { 9910 u64 u; 9911 struct nixx_lf_rq_op_drop_pkts_s { 9912 u64 cnt : 48; 9913 u64 reserved_48_62 : 15; 9914 u64 op_err : 1; 9915 } s; 9916 /* struct nixx_lf_rq_op_drop_pkts_s cn; */ 9917}; 9918 9919static inline u64 NIXX_LF_RQ_OP_DROP_PKTS(void) 9920 __attribute__ ((pure, always_inline)); 9921static inline u64 NIXX_LF_RQ_OP_DROP_PKTS(void) 9922{ 9923 return 0x940; 9924} 9925 9926/** 9927 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_int 9928 * 9929 * NIX LF Receive Queue Interrupt Operation Register A 64-bit atomic 9930 * load-and-add to this register reads RQ interrupts and interrupt 9931 * enables. A 64-bit write optionally sets or clears interrupts and 9932 * interrupt enables. All other accesses to this register (e.g. reads, 9933 * 128-bit accesses) are RAZ/WI. RSL accesses to this register are 9934 * RAZ/WI. 9935 */ 9936union nixx_lf_rq_op_int { 9937 u64 u; 9938 struct nixx_lf_rq_op_int_s { 9939 u64 rq_int : 8; 9940 u64 rq_int_ena : 8; 9941 u64 reserved_16_41 : 26; 9942 u64 op_err : 1; 9943 u64 setop : 1; 9944 u64 rq : 20; 9945 } s; 9946 /* struct nixx_lf_rq_op_int_s cn; */ 9947}; 9948 9949static inline u64 NIXX_LF_RQ_OP_INT(void) 9950 __attribute__ ((pure, always_inline)); 9951static inline u64 NIXX_LF_RQ_OP_INT(void) 9952{ 9953 return 0x900; 9954} 9955 9956/** 9957 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_octs 9958 * 9959 * NIX LF Receive Queue Octets Operation Register A 64-bit atomic load- 9960 * and-add to this register reads NIX_RQ_CTX_S[OCTS]. The atomic write 9961 * data has format NIX_OP_Q_WDATA_S and selects the RQ within LF. All 9962 * other accesses to this register (e.g. reads and writes) are RAZ/WI. 9963 * RSL accesses to this register are RAZ/WI. 9964 */ 9965union nixx_lf_rq_op_octs { 9966 u64 u; 9967 struct nixx_lf_rq_op_octs_s { 9968 u64 cnt : 48; 9969 u64 reserved_48_62 : 15; 9970 u64 op_err : 1; 9971 } s; 9972 /* struct nixx_lf_rq_op_octs_s cn; */ 9973}; 9974 9975static inline u64 NIXX_LF_RQ_OP_OCTS(void) 9976 __attribute__ ((pure, always_inline)); 9977static inline u64 NIXX_LF_RQ_OP_OCTS(void) 9978{ 9979 return 0x910; 9980} 9981 9982/** 9983 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_pkts 9984 * 9985 * NIX LF Receive Queue Packets Operation Register A 64-bit atomic load- 9986 * and-add to this register reads NIX_RQ_CTX_S[PKTS]. The atomic write 9987 * data has format NIX_OP_Q_WDATA_S and selects the RQ within LF. All 9988 * other accesses to this register (e.g. reads and writes) are RAZ/WI. 9989 * RSL accesses to this register are RAZ/WI. 9990 */ 9991union nixx_lf_rq_op_pkts { 9992 u64 u; 9993 struct nixx_lf_rq_op_pkts_s { 9994 u64 cnt : 48; 9995 u64 reserved_48_62 : 15; 9996 u64 op_err : 1; 9997 } s; 9998 /* struct nixx_lf_rq_op_pkts_s cn; */ 9999}; 10000 10001static inline u64 NIXX_LF_RQ_OP_PKTS(void) 10002 __attribute__ ((pure, always_inline)); 10003static inline u64 NIXX_LF_RQ_OP_PKTS(void) 10004{ 10005 return 0x920; 10006} 10007 10008/** 10009 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_re_pkts 10010 * 10011 * NIX LF Receive Queue Errored Packets Operation Register A 64-bit 10012 * atomic load-and-add to this register reads NIX_RQ_CTX_S[RE_PKTS]. The 10013 * atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ 10014 * within LF. All other accesses to this register (e.g. reads and 10015 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. 10016 */ 10017union nixx_lf_rq_op_re_pkts { 10018 u64 u; 10019 struct nixx_lf_rq_op_re_pkts_s { 10020 u64 cnt : 48; 10021 u64 reserved_48_62 : 15; 10022 u64 op_err : 1; 10023 } s; 10024 /* struct nixx_lf_rq_op_re_pkts_s cn; */ 10025}; 10026 10027static inline u64 NIXX_LF_RQ_OP_RE_PKTS(void) 10028 __attribute__ ((pure, always_inline)); 10029static inline u64 NIXX_LF_RQ_OP_RE_PKTS(void) 10030{ 10031 return 0x950; 10032} 10033 10034/** 10035 * Register (RVU_PFVF_BAR2) nix#_lf_rx_secret# 10036 * 10037 * NIX LF Receive Secret Key Registers 10038 */ 10039union nixx_lf_rx_secretx { 10040 u64 u; 10041 struct nixx_lf_rx_secretx_s { 10042 u64 key : 64; 10043 } s; 10044 /* struct nixx_lf_rx_secretx_s cn; */ 10045}; 10046 10047static inline u64 NIXX_LF_RX_SECRETX(u64 a) 10048 __attribute__ ((pure, always_inline)); 10049static inline u64 NIXX_LF_RX_SECRETX(u64 a) 10050{ 10051 return 0 + 8 * a; 10052} 10053 10054/** 10055 * Register (RVU_PFVF_BAR2) nix#_lf_rx_stat# 10056 * 10057 * NIX LF Receive Statistics Registers The last dimension indicates which 10058 * statistic, and is enumerated by NIX_STAT_LF_RX_E. 10059 */ 10060union nixx_lf_rx_statx { 10061 u64 u; 10062 struct nixx_lf_rx_statx_s { 10063 u64 stat : 48; 10064 u64 reserved_48_63 : 16; 10065 } s; 10066 /* struct nixx_lf_rx_statx_s cn; */ 10067}; 10068 10069static inline u64 NIXX_LF_RX_STATX(u64 a) 10070 __attribute__ ((pure, always_inline)); 10071static inline u64 NIXX_LF_RX_STATX(u64 a) 10072{ 10073 return 0x400 + 8 * a; 10074} 10075 10076/** 10077 * Register (RVU_PFVF_BAR2) nix#_lf_send_err_dbg 10078 * 10079 * NIX LF Send Error Debug Register This register captures debug info an 10080 * error detected on packet send after a meta-descriptor is granted by 10081 * PSE. Hardware sets [VALID] when the debug info is captured, and 10082 * subsequent errors are not captured until software clears [VALID] by 10083 * writing a one to it. 10084 */ 10085union nixx_lf_send_err_dbg { 10086 u64 u; 10087 struct nixx_lf_send_err_dbg_s { 10088 u64 errcode : 8; 10089 u64 sq : 20; 10090 u64 sqe_id : 16; 10091 u64 valid : 1; 10092 u64 reserved_45_63 : 19; 10093 } s; 10094 /* struct nixx_lf_send_err_dbg_s cn; */ 10095}; 10096 10097static inline u64 NIXX_LF_SEND_ERR_DBG(void) 10098 __attribute__ ((pure, always_inline)); 10099static inline u64 NIXX_LF_SEND_ERR_DBG(void) 10100{ 10101 return 0x280; 10102} 10103 10104/** 10105 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_drop_octs 10106 * 10107 * NIX LF Send Queue Dropped Octets Operation Register A 64-bit atomic 10108 * load-and-add to this register reads NIX_SQ_CTX_S[DROP_OCTS]. The 10109 * atomic write data has format NIX_OP_Q_WDATA_S and selects the SQ 10110 * within LF. All other accesses to this register (e.g. reads and 10111 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. 10112 */ 10113union nixx_lf_sq_op_drop_octs { 10114 u64 u; 10115 struct nixx_lf_sq_op_drop_octs_s { 10116 u64 cnt : 48; 10117 u64 reserved_48_62 : 15; 10118 u64 op_err : 1; 10119 } s; 10120 /* struct nixx_lf_sq_op_drop_octs_s cn; */ 10121}; 10122 10123static inline u64 NIXX_LF_SQ_OP_DROP_OCTS(void) 10124 __attribute__ ((pure, always_inline)); 10125static inline u64 NIXX_LF_SQ_OP_DROP_OCTS(void) 10126{ 10127 return 0xa40; 10128} 10129 10130/** 10131 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_drop_pkts 10132 * 10133 * NIX LF Send Queue Dropped Packets Operation Register A 64-bit atomic 10134 * load-and-add to this register reads NIX_SQ_CTX_S[DROP_PKTS]. The 10135 * atomic write data has format NIX_OP_Q_WDATA_S and selects the SQ 10136 * within LF. All other accesses to this register (e.g. reads and 10137 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI. 10138 */ 10139union nixx_lf_sq_op_drop_pkts { 10140 u64 u; 10141 struct nixx_lf_sq_op_drop_pkts_s { 10142 u64 cnt : 48; 10143 u64 reserved_48_62 : 15; 10144 u64 op_err : 1; 10145 } s; 10146 /* struct nixx_lf_sq_op_drop_pkts_s cn; */ 10147}; 10148 10149static inline u64 NIXX_LF_SQ_OP_DROP_PKTS(void) 10150 __attribute__ ((pure, always_inline)); 10151static inline u64 NIXX_LF_SQ_OP_DROP_PKTS(void) 10152{ 10153 return 0xa50; 10154} 10155 10156/** 10157 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_err_dbg 10158 * 10159 * NIX LF SQ Operation Error Debug Register This register captures debug 10160 * info for an error detected on LMT store to NIX_LF_OP_SEND() or when a 10161 * NIX_LF_SQ_OP_* register is accessed. Hardware sets [VALID] when the 10162 * debug info is captured, and subsequent errors are not captured until 10163 * software clears [VALID] by writing a one to it. 10164 */ 10165union nixx_lf_sq_op_err_dbg { 10166 u64 u; 10167 struct nixx_lf_sq_op_err_dbg_s { 10168 u64 errcode : 8; 10169 u64 sq : 20; 10170 u64 sqe_id : 16; 10171 u64 valid : 1; 10172 u64 reserved_45_63 : 19; 10173 } s; 10174 /* struct nixx_lf_sq_op_err_dbg_s cn; */ 10175}; 10176 10177static inline u64 NIXX_LF_SQ_OP_ERR_DBG(void) 10178 __attribute__ ((pure, always_inline)); 10179static inline u64 NIXX_LF_SQ_OP_ERR_DBG(void) 10180{ 10181 return 0x260; 10182} 10183 10184/** 10185 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_int 10186 * 10187 * NIX LF Send Queue Interrupt Operation Register A 64-bit atomic load- 10188 * and-add to this register reads SQ interrupts, interrupt enables and 10189 * XOFF status. A write optionally sets or clears interrupts, interrupt 10190 * enables and XOFF status. A read is RAZ. RSL accesses to this register 10191 * are RAZ/WI. 10192 */ 10193union nixx_lf_sq_op_int { 10194 u64 u; 10195 struct nixx_lf_sq_op_int_s { 10196 u64 sq_int : 8; 10197 u64 sq_int_ena : 8; 10198 u64 xoff : 1; 10199 u64 reserved_17_41 : 25; 10200 u64 op_err : 1; 10201 u64 setop : 1; 10202 u64 sq : 20; 10203 } s; 10204 /* struct nixx_lf_sq_op_int_s cn; */ 10205}; 10206 10207static inline u64 NIXX_LF_SQ_OP_INT(void) 10208 __attribute__ ((pure, always_inline)); 10209static inline u64 NIXX_LF_SQ_OP_INT(void) 10210{ 10211 return 0xa00; 10212} 10213 10214/** 10215 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_octs 10216 * 10217 * NIX LF Send Queue Octets Operation Register A 64-bit atomic load-and- 10218 * add to this register reads NIX_SQ_CTX_S[OCTS]. The atomic write data 10219 * has format NIX_OP_Q_WDATA_S and selects the SQ within LF. All other 10220 * accesses to this register (e.g. reads and writes) are RAZ/WI. RSL 10221 * accesses to this register are RAZ/WI. 10222 */ 10223union nixx_lf_sq_op_octs { 10224 u64 u; 10225 struct nixx_lf_sq_op_octs_s { 10226 u64 cnt : 48; 10227 u64 reserved_48_62 : 15; 10228 u64 op_err : 1; 10229 } s; 10230 /* struct nixx_lf_sq_op_octs_s cn; */ 10231}; 10232 10233static inline u64 NIXX_LF_SQ_OP_OCTS(void) 10234 __attribute__ ((pure, always_inline)); 10235static inline u64 NIXX_LF_SQ_OP_OCTS(void) 10236{ 10237 return 0xa10; 10238} 10239 10240/** 10241 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_pkts 10242 * 10243 * NIX LF Send Queue Packets Operation Register A 64-bit atomic load-and- 10244 * add to this register reads NIX_SQ_CTX_S[PKTS]. The atomic write data 10245 * has format NIX_OP_Q_WDATA_S and selects the SQ within LF. All other 10246 * accesses to this register (e.g. reads and writes) are RAZ/WI. RSL 10247 * accesses to this register are RAZ/WI. 10248 */ 10249union nixx_lf_sq_op_pkts { 10250 u64 u; 10251 struct nixx_lf_sq_op_pkts_s { 10252 u64 cnt : 48; 10253 u64 reserved_48_62 : 15; 10254 u64 op_err : 1; 10255 } s; 10256 /* struct nixx_lf_sq_op_pkts_s cn; */ 10257}; 10258 10259static inline u64 NIXX_LF_SQ_OP_PKTS(void) 10260 __attribute__ ((pure, always_inline)); 10261static inline u64 NIXX_LF_SQ_OP_PKTS(void) 10262{ 10263 return 0xa20; 10264} 10265 10266/** 10267 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_status 10268 * 10269 * NIX LF Send Queue Status Operation Register A 64-bit atomic load-and- 10270 * add to this register reads status fields in NIX_SQ_CTX_S. The atomic 10271 * write data has format NIX_OP_Q_WDATA_S and selects the SQ within LF. 10272 * Completion of the load-and-add operation also ensures that all 10273 * previously issued LMT stores to NIX_LF_OP_SEND() have completed. All 10274 * other accesses to this register (e.g. reads and writes) are RAZ/WI. 10275 * RSL accesses to this register are RAZ/WI. 10276 */ 10277union nixx_lf_sq_op_status { 10278 u64 u; 10279 struct nixx_lf_sq_op_status_s { 10280 u64 sqb_count : 16; 10281 u64 reserved_16_19 : 4; 10282 u64 head_offset : 6; 10283 u64 reserved_26_27 : 2; 10284 u64 tail_offset : 6; 10285 u64 reserved_34_62 : 29; 10286 u64 op_err : 1; 10287 } s; 10288 struct nixx_lf_sq_op_status_cn { 10289 u64 sqb_count : 16; 10290 u64 reserved_16_19 : 4; 10291 u64 head_offset : 6; 10292 u64 reserved_26_27 : 2; 10293 u64 tail_offset : 6; 10294 u64 reserved_34_35 : 2; 10295 u64 reserved_36_62 : 27; 10296 u64 op_err : 1; 10297 } cn; 10298}; 10299 10300static inline u64 NIXX_LF_SQ_OP_STATUS(void) 10301 __attribute__ ((pure, always_inline)); 10302static inline u64 NIXX_LF_SQ_OP_STATUS(void) 10303{ 10304 return 0xa30; 10305} 10306 10307/** 10308 * Register (RVU_PFVF_BAR2) nix#_lf_tx_stat# 10309 * 10310 * NIX LF Transmit Statistics Registers The last dimension indicates 10311 * which statistic, and is enumerated by NIX_STAT_LF_TX_E. 10312 */ 10313union nixx_lf_tx_statx { 10314 u64 u; 10315 struct nixx_lf_tx_statx_s { 10316 u64 stat : 48; 10317 u64 reserved_48_63 : 16; 10318 } s; 10319 /* struct nixx_lf_tx_statx_s cn; */ 10320}; 10321 10322static inline u64 NIXX_LF_TX_STATX(u64 a) 10323 __attribute__ ((pure, always_inline)); 10324static inline u64 NIXX_LF_TX_STATX(u64 a) 10325{ 10326 return 0x300 + 8 * a; 10327} 10328 10329/** 10330 * Register (RVU_PF_BAR0) nix#_priv_af_int_cfg 10331 * 10332 * NIX Privileged Admin Function Interrupt Configuration Register 10333 */ 10334union nixx_priv_af_int_cfg { 10335 u64 u; 10336 struct nixx_priv_af_int_cfg_s { 10337 u64 msix_offset : 11; 10338 u64 reserved_11 : 1; 10339 u64 msix_size : 8; 10340 u64 reserved_20_63 : 44; 10341 } s; 10342 /* struct nixx_priv_af_int_cfg_s cn; */ 10343}; 10344 10345static inline u64 NIXX_PRIV_AF_INT_CFG(void) 10346 __attribute__ ((pure, always_inline)); 10347static inline u64 NIXX_PRIV_AF_INT_CFG(void) 10348{ 10349 return 0x8000000; 10350} 10351 10352/** 10353 * Register (RVU_PF_BAR0) nix#_priv_lf#_cfg 10354 * 10355 * NIX Privileged Local Function Configuration Registers These registers 10356 * allow each NIX local function (LF) to be provisioned to a VF/PF for 10357 * RVU. See also NIX_AF_RVU_LF_CFG_DEBUG. Software should read this 10358 * register after write to ensure that the LF is mapped to [PF_FUNC] 10359 * before issuing transactions to the mapped PF and function. [SLOT] 10360 * must be zero. Internal: Hardware ignores [SLOT] and always assumes 10361 * 0x0. 10362 */ 10363union nixx_priv_lfx_cfg { 10364 u64 u; 10365 struct nixx_priv_lfx_cfg_s { 10366 u64 slot : 8; 10367 u64 pf_func : 16; 10368 u64 reserved_24_62 : 39; 10369 u64 ena : 1; 10370 } s; 10371 /* struct nixx_priv_lfx_cfg_s cn; */ 10372}; 10373 10374static inline u64 NIXX_PRIV_LFX_CFG(u64 a) 10375 __attribute__ ((pure, always_inline)); 10376static inline u64 NIXX_PRIV_LFX_CFG(u64 a) 10377{ 10378 return 0x8000010 + 0x100 * a; 10379} 10380 10381/** 10382 * Register (RVU_PF_BAR0) nix#_priv_lf#_int_cfg 10383 * 10384 * NIX Privileged LF Interrupt Configuration Registers 10385 */ 10386union nixx_priv_lfx_int_cfg { 10387 u64 u; 10388 struct nixx_priv_lfx_int_cfg_s { 10389 u64 msix_offset : 11; 10390 u64 reserved_11 : 1; 10391 u64 msix_size : 8; 10392 u64 reserved_20_63 : 44; 10393 } s; 10394 /* struct nixx_priv_lfx_int_cfg_s cn; */ 10395}; 10396 10397static inline u64 NIXX_PRIV_LFX_INT_CFG(u64 a) 10398 __attribute__ ((pure, always_inline)); 10399static inline u64 NIXX_PRIV_LFX_INT_CFG(u64 a) 10400{ 10401 return 0x8000020 + 0x100 * a; 10402} 10403 10404#endif /* __CSRS_NIX_H__ */ 10405