1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * https://spdx.org/licenses 6 */ 7#ifndef __CSRS_XCV_H__ 8#define __CSRS_XCV_H__ 9 10/** 11 * @file 12 * 13 * Configuration and status register (CSR) address and type definitions for 14 * XCV. 15 * 16 * This file is auto generated. Do not edit. 17 * 18 */ 19 20/** 21 * Enumeration xcv_bar_e 22 * 23 * XCV Base Address Register Enumeration Enumerates the base address 24 * registers. 25 */ 26#define XCV_BAR_E_XCVX_PF_BAR0(a) (0x87e0db000000ll + 0ll * (a)) 27#define XCV_BAR_E_XCVX_PF_BAR0_SIZE 0x100000ull 28#define XCV_BAR_E_XCVX_PF_BAR4(a) (0x87e0dbf00000ll + 0ll * (a)) 29#define XCV_BAR_E_XCVX_PF_BAR4_SIZE 0x100000ull 30 31/** 32 * Enumeration xcv_int_vec_e 33 * 34 * XCV MSI-X Vector Enumeration Enumerates the MSI-X interrupt vectors. 35 */ 36#define XCV_INT_VEC_E_INT (0) 37 38/** 39 * Register (RSL) xcv#_batch_crd_ret 40 * 41 * XCV Batch Credit Return Register 42 */ 43union xcvx_batch_crd_ret { 44 u64 u; 45 struct xcvx_batch_crd_ret_s { 46 u64 crd_ret : 1; 47 u64 reserved_1_63 : 63; 48 } s; 49 /* struct xcvx_batch_crd_ret_s cn; */ 50}; 51 52static inline u64 XCVX_BATCH_CRD_RET(u64 a) 53 __attribute__ ((pure, always_inline)); 54static inline u64 XCVX_BATCH_CRD_RET(u64 a) 55{ 56 return 0x100 + 0 * a; 57} 58 59/** 60 * Register (RSL) xcv#_comp_ctl 61 * 62 * XCV Compensation Controller Register This register controls 63 * programmable compensation. 64 */ 65union xcvx_comp_ctl { 66 u64 u; 67 struct xcvx_comp_ctl_s { 68 u64 nctl_sat : 1; 69 u64 reserved_1_26 : 26; 70 u64 nctl_lock : 1; 71 u64 reserved_28 : 1; 72 u64 pctl_sat : 1; 73 u64 pctl_lock : 1; 74 u64 reserved_31 : 1; 75 u64 drv_nctl : 5; 76 u64 reserved_37_39 : 3; 77 u64 drv_pctl : 5; 78 u64 reserved_45_47 : 3; 79 u64 cmp_nctl : 5; 80 u64 reserved_53_55 : 3; 81 u64 cmp_pctl : 5; 82 u64 reserved_61_62 : 2; 83 u64 drv_byp : 1; 84 } s; 85 /* struct xcvx_comp_ctl_s cn; */ 86}; 87 88static inline u64 XCVX_COMP_CTL(u64 a) 89 __attribute__ ((pure, always_inline)); 90static inline u64 XCVX_COMP_CTL(u64 a) 91{ 92 return 0x20 + 0 * a; 93} 94 95/** 96 * Register (RSL) xcv#_ctl 97 * 98 * XCV Control Register This register contains the status control bits. 99 */ 100union xcvx_ctl { 101 u64 u; 102 struct xcvx_ctl_s { 103 u64 speed : 2; 104 u64 lpbk_int : 1; 105 u64 lpbk_ext : 1; 106 u64 reserved_4_63 : 60; 107 } s; 108 /* struct xcvx_ctl_s cn; */ 109}; 110 111static inline u64 XCVX_CTL(u64 a) 112 __attribute__ ((pure, always_inline)); 113static inline u64 XCVX_CTL(u64 a) 114{ 115 return 0x30 + 0 * a; 116} 117 118/** 119 * Register (RSL) xcv#_dll_ctl 120 * 121 * XCV DLL Controller Register The RGMII timing specification requires 122 * that devices transmit clock and data synchronously. The specification 123 * requires external sources (namely the PC board trace routes) to 124 * introduce the appropriate 1.5 to 2.0 ns of delay. To eliminate the 125 * need for the PC board delays, the RGMII interface has optional on- 126 * board DLLs for both transmit and receive. For correct operation, at 127 * most one of the transmitter, board, or receiver involved in an RGMII 128 * link should introduce delay. By default/reset, the RGMII receivers 129 * delay the received clock, and the RGMII transmitters do not delay the 130 * transmitted clock. Whether this default works as-is with a given link 131 * partner depends on the behavior of the link partner and the PC board. 132 * These are the possible modes of RGMII receive operation: * 133 * XCV()_DLL_CTL[CLKRX_BYP] = 0 (reset value) - The RGMII receive 134 * interface introduces clock delay using its internal DLL. This mode is 135 * appropriate if neither the remote transmitter nor the PC board delays 136 * the clock. * XCV()_DLL_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The 137 * RGMII receive interface introduces no clock delay. This mode is 138 * appropriate if either the remote transmitter or the PC board delays 139 * the clock. These are the possible modes of RGMII transmit operation: 140 * * XCV()_DLL_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) - The 141 * RGMII transmit interface introduces no clock delay. This mode is 142 * appropriate is either the remote receiver or the PC board delays the 143 * clock. * XCV()_DLL_CTL[CLKTX_BYP] = 0 - The RGMII transmit interface 144 * introduces clock delay using its internal DLL. This mode is 145 * appropriate if neither the remote receiver nor the PC board delays the 146 * clock. 147 */ 148union xcvx_dll_ctl { 149 u64 u; 150 struct xcvx_dll_ctl_s { 151 u64 refclk_sel : 2; 152 u64 reserved_2_7 : 6; 153 u64 clktx_set : 7; 154 u64 clktx_byp : 1; 155 u64 clkrx_set : 7; 156 u64 clkrx_byp : 1; 157 u64 clk_set : 7; 158 u64 lock : 1; 159 u64 reserved_32_63 : 32; 160 } s; 161 /* struct xcvx_dll_ctl_s cn; */ 162}; 163 164static inline u64 XCVX_DLL_CTL(u64 a) 165 __attribute__ ((pure, always_inline)); 166static inline u64 XCVX_DLL_CTL(u64 a) 167{ 168 return 0x10 + 0 * a; 169} 170 171/** 172 * Register (RSL) xcv#_eco 173 * 174 * INTERNAL: XCV ECO Register 175 */ 176union xcvx_eco { 177 u64 u; 178 struct xcvx_eco_s { 179 u64 eco_rw : 16; 180 u64 reserved_16_63 : 48; 181 } s; 182 /* struct xcvx_eco_s cn; */ 183}; 184 185static inline u64 XCVX_ECO(u64 a) 186 __attribute__ ((pure, always_inline)); 187static inline u64 XCVX_ECO(u64 a) 188{ 189 return 0x200 + 0 * a; 190} 191 192/** 193 * Register (RSL) xcv#_inbnd_status 194 * 195 * XCV Inband Status Register This register contains RGMII inband status. 196 */ 197union xcvx_inbnd_status { 198 u64 u; 199 struct xcvx_inbnd_status_s { 200 u64 link : 1; 201 u64 speed : 2; 202 u64 duplex : 1; 203 u64 reserved_4_63 : 60; 204 } s; 205 /* struct xcvx_inbnd_status_s cn; */ 206}; 207 208static inline u64 XCVX_INBND_STATUS(u64 a) 209 __attribute__ ((pure, always_inline)); 210static inline u64 XCVX_INBND_STATUS(u64 a) 211{ 212 return 0x80 + 0 * a; 213} 214 215/** 216 * Register (RSL) xcv#_int 217 * 218 * XCV Interrupt Register This register flags error for TX FIFO overflow, 219 * TX FIFO underflow and incomplete byte for 10/100 Mode. It also flags 220 * status change for link duplex, link speed and link up/down. 221 */ 222union xcvx_int { 223 u64 u; 224 struct xcvx_int_s { 225 u64 link : 1; 226 u64 speed : 1; 227 u64 reserved_2 : 1; 228 u64 duplex : 1; 229 u64 incomp_byte : 1; 230 u64 tx_undflw : 1; 231 u64 tx_ovrflw : 1; 232 u64 reserved_7_63 : 57; 233 } s; 234 /* struct xcvx_int_s cn; */ 235}; 236 237static inline u64 XCVX_INT(u64 a) 238 __attribute__ ((pure, always_inline)); 239static inline u64 XCVX_INT(u64 a) 240{ 241 return 0x40 + 0 * a; 242} 243 244/** 245 * Register (RSL) xcv#_int_ena_w1c 246 * 247 * Loopback Error Interrupt Enable Clear Register This register clears 248 * interrupt enable bits. 249 */ 250union xcvx_int_ena_w1c { 251 u64 u; 252 struct xcvx_int_ena_w1c_s { 253 u64 link : 1; 254 u64 speed : 1; 255 u64 reserved_2 : 1; 256 u64 duplex : 1; 257 u64 incomp_byte : 1; 258 u64 tx_undflw : 1; 259 u64 tx_ovrflw : 1; 260 u64 reserved_7_63 : 57; 261 } s; 262 /* struct xcvx_int_ena_w1c_s cn; */ 263}; 264 265static inline u64 XCVX_INT_ENA_W1C(u64 a) 266 __attribute__ ((pure, always_inline)); 267static inline u64 XCVX_INT_ENA_W1C(u64 a) 268{ 269 return 0x50 + 0 * a; 270} 271 272/** 273 * Register (RSL) xcv#_int_ena_w1s 274 * 275 * Loopback Error Interrupt Enable Set Register This register sets 276 * interrupt enable bits. 277 */ 278union xcvx_int_ena_w1s { 279 u64 u; 280 struct xcvx_int_ena_w1s_s { 281 u64 link : 1; 282 u64 speed : 1; 283 u64 reserved_2 : 1; 284 u64 duplex : 1; 285 u64 incomp_byte : 1; 286 u64 tx_undflw : 1; 287 u64 tx_ovrflw : 1; 288 u64 reserved_7_63 : 57; 289 } s; 290 /* struct xcvx_int_ena_w1s_s cn; */ 291}; 292 293static inline u64 XCVX_INT_ENA_W1S(u64 a) 294 __attribute__ ((pure, always_inline)); 295static inline u64 XCVX_INT_ENA_W1S(u64 a) 296{ 297 return 0x58 + 0 * a; 298} 299 300/** 301 * Register (RSL) xcv#_int_w1s 302 * 303 * Loopback Error Interrupt Set Register This register sets interrupt 304 * bits. 305 */ 306union xcvx_int_w1s { 307 u64 u; 308 struct xcvx_int_w1s_s { 309 u64 link : 1; 310 u64 speed : 1; 311 u64 reserved_2 : 1; 312 u64 duplex : 1; 313 u64 incomp_byte : 1; 314 u64 tx_undflw : 1; 315 u64 tx_ovrflw : 1; 316 u64 reserved_7_63 : 57; 317 } s; 318 /* struct xcvx_int_w1s_s cn; */ 319}; 320 321static inline u64 XCVX_INT_W1S(u64 a) 322 __attribute__ ((pure, always_inline)); 323static inline u64 XCVX_INT_W1S(u64 a) 324{ 325 return 0x48 + 0 * a; 326} 327 328/** 329 * Register (RSL) xcv#_msix_pba# 330 * 331 * XCV MSI-X Pending Bit Array Registers This register is the MSI-X PBA 332 * table; the bit number is indexed by the XCV_INT_VEC_E enumeration. 333 */ 334union xcvx_msix_pbax { 335 u64 u; 336 struct xcvx_msix_pbax_s { 337 u64 pend : 64; 338 } s; 339 /* struct xcvx_msix_pbax_s cn; */ 340}; 341 342static inline u64 XCVX_MSIX_PBAX(u64 a, u64 b) 343 __attribute__ ((pure, always_inline)); 344static inline u64 XCVX_MSIX_PBAX(u64 a, u64 b) 345{ 346 return 0xf0000 + 0 * a + 8 * b; 347} 348 349/** 350 * Register (RSL) xcv#_msix_vec#_addr 351 * 352 * XCV MSI-X Vector-Table Address Register This register is the MSI-X 353 * vector table, indexed by the XCV_INT_VEC_E enumeration. 354 */ 355union xcvx_msix_vecx_addr { 356 u64 u; 357 struct xcvx_msix_vecx_addr_s { 358 u64 secvec : 1; 359 u64 reserved_1 : 1; 360 u64 addr : 47; 361 u64 reserved_49_63 : 15; 362 } s; 363 /* struct xcvx_msix_vecx_addr_s cn; */ 364}; 365 366static inline u64 XCVX_MSIX_VECX_ADDR(u64 a, u64 b) 367 __attribute__ ((pure, always_inline)); 368static inline u64 XCVX_MSIX_VECX_ADDR(u64 a, u64 b) 369{ 370 return 0 + 0 * a + 0x10 * b; 371} 372 373/** 374 * Register (RSL) xcv#_msix_vec#_ctl 375 * 376 * XCV MSI-X Vector-Table Control and Data Register This register is the 377 * MSI-X vector table, indexed by the XCV_INT_VEC_E enumeration. 378 */ 379union xcvx_msix_vecx_ctl { 380 u64 u; 381 struct xcvx_msix_vecx_ctl_s { 382 u64 data : 20; 383 u64 reserved_20_31 : 12; 384 u64 mask : 1; 385 u64 reserved_33_63 : 31; 386 } s; 387 /* struct xcvx_msix_vecx_ctl_s cn; */ 388}; 389 390static inline u64 XCVX_MSIX_VECX_CTL(u64 a, u64 b) 391 __attribute__ ((pure, always_inline)); 392static inline u64 XCVX_MSIX_VECX_CTL(u64 a, u64 b) 393{ 394 return 8 + 0 * a + 0x10 * b; 395} 396 397/** 398 * Register (RSL) xcv#_reset 399 * 400 * XCV Reset Registers This register controls reset. 401 */ 402union xcvx_reset { 403 u64 u; 404 struct xcvx_reset_s { 405 u64 rx_dat_rst_n : 1; 406 u64 rx_pkt_rst_n : 1; 407 u64 tx_dat_rst_n : 1; 408 u64 tx_pkt_rst_n : 1; 409 u64 reserved_4_6 : 3; 410 u64 comp : 1; 411 u64 reserved_8_10 : 3; 412 u64 dllrst : 1; 413 u64 reserved_12_14 : 3; 414 u64 clkrst : 1; 415 u64 reserved_16_62 : 47; 416 u64 enable : 1; 417 } s; 418 /* struct xcvx_reset_s cn; */ 419}; 420 421static inline u64 XCVX_RESET(u64 a) 422 __attribute__ ((pure, always_inline)); 423static inline u64 XCVX_RESET(u64 a) 424{ 425 return 0 + 0 * a; 426} 427 428#endif /* __CSRS_XCV_H__ */ 429