1/* SPDX-License-Identifier: GPL-2.0+ */
2
3#ifndef _NPCM_AES_H_
4#define _NPCM_AES_H_
5
6#define AES_OP_ENCRYPT          0
7#define AES_OP_DECRYPT          1
8#define SIZE_AES_BLOCK          (AES128_KEY_LENGTH)
9
10struct npcm_aes_regs {
11	unsigned char reserved_0[0x400];    // 0x000
12	unsigned int aes_key_0;             // 0x400
13	unsigned int aes_key_1;             // 0x404
14	unsigned int aes_key_2;             // 0x408
15	unsigned int aes_key_3;             // 0x40c
16	unsigned char reserved_1[0x30];     // 0x410
17	unsigned int aes_iv_0;              // 0x440
18	unsigned char reserved_2[0x1c];     // 0x444
19	unsigned int aes_ctr_0;             // 0x460
20	unsigned char reserved_3[0x0c];     // 0x464
21	unsigned int aes_busy;              // 0x470
22	unsigned char reserved_4[0x04];     // 0x474
23	unsigned int aes_sk;                // 0x478
24	unsigned char reserved_5[0x14];     // 0x47c
25	unsigned int aes_prev_iv_0;         // 0x490
26	unsigned char reserved_6[0x0c];     // 0x494
27	unsigned int aes_din_dout;          // 0x4a0
28	unsigned char reserved_7[0x1c];     // 0x4a4
29	unsigned int aes_control;           // 0x4c0
30	unsigned int aes_version;           // 0x4c4
31	unsigned int aes_hw_flags;          // 0x4c8
32	unsigned char reserved_8[0x28];     // 0x4cc
33	unsigned int aes_sw_reset;          // 0x4f4
34	unsigned char reserved_9[0x08];     // 0x4f8
35	unsigned int aes_fifo_data;         // 0x500
36	unsigned char reserved_10[0xfc];    // 0x504
37	unsigned int aes_fifo_status;       // 0x600
38};
39
40#define AES_BUSY_BIT            BIT(0)
41#define SW_RESET_BIT            BIT(0)
42#define AES_SK_BIT              BIT(0)
43
44#define DIN_FIFO_FULL           BIT(0)
45#define DIN_FIFO_EMPTY          BIT(1)
46#define DOUT_FIFO_FULL          BIT(2)
47#define DOUT_FIFO_EMPTY         BIT(3)
48#define DIN_FIFO_OVERFLOW       BIT(4)
49#define DOUT_FIFO_UNDERFLOW     BIT(5)
50
51int npcm_aes_select_key(u8 fkeyind);
52
53#endif
54