1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
4 */
5
6#ifndef _LPC32XX_CPU_H
7#define _LPC32XX_CPU_H
8
9/* LPC32XX Memory map */
10
11/* AHB physical base addresses */
12#define SLC_NAND_BASE	0x20020000	/* SLC NAND Flash registers base    */
13#define SSP0_BASE	0x20084000	/* SSP0 registers base              */
14#define SD_CARD_BASE	0x20098000	/* SD card interface registers base */
15#define MLC_NAND_BASE	0x200A8000	/* MLC NAND Flash registers base    */
16#define DMA_BASE	0x31000000	/* DMA controller registers base    */
17#define USB_BASE	0x31020000	/* USB registers base               */
18#define LCD_BASE	0x31040000	/* LCD registers base               */
19#define ETHERNET_BASE	0x31060000	/* Ethernet registers base          */
20#define EMC_BASE	0x31080000	/* EMC configuration registers base */
21
22/* FAB peripherals base addresses */
23#define CLK_PM_BASE	0x40004000	/* System control registers base    */
24#define HS_UART1_BASE	0x40014000	/* High speed UART 1 registers base */
25#define HS_UART2_BASE	0x40018000	/* High speed UART 2 registers base */
26#define HS_UART7_BASE	0x4001C000	/* High speed UART 7 registers base */
27#define RTC_BASE	0x40024000	/* RTC registers base               */
28#define GPIO_BASE	0x40028000	/* GPIO registers base              */
29#define MUX_BASE	0x40028000	/* MUX registers base               */
30#define WDT_BASE	0x4003C000	/* Watchdog timer registers base    */
31#define TIMER0_BASE	0x40044000	/* Timer0 registers base            */
32#define TIMER1_BASE	0x4004C000	/* Timer1 registers base            */
33#define UART_CTRL_BASE	0x40054000	/* UART control regsisters base     */
34
35/* APB peripherals base addresses */
36#define UART3_BASE	0x40080000	/* UART 3 registers base            */
37#define UART4_BASE	0x40088000	/* UART 4 registers base            */
38#define UART5_BASE	0x40090000	/* UART 5 registers base            */
39#define UART6_BASE	0x40098000	/* UART 6 registers base            */
40#define I2C1_BASE	0x400A0000	/* I2C  1 registers base            */
41#define I2C2_BASE	0x400A8000	/* I2C  2 registers base            */
42
43/* External SDRAM Memory Bank base addresses */
44#define EMC_DYCS0_BASE	0x80000000	/* SDRAM DYCS0 base address         */
45#define EMC_DYCS1_BASE	0xA0000000	/* SDRAM DYCS1 base address         */
46
47/* External Static Memory Bank base addresses */
48#define EMC_CS0_BASE	0xE0000000
49#define EMC_CS1_BASE	0xE1000000
50#define EMC_CS2_BASE	0xE2000000
51#define EMC_CS3_BASE	0xE3000000
52
53#endif /* _LPC32XX_CPU_H */
54